A New Realization of Electronically Tunable Multiple-Input Single-Voltage Output Second-Order LP/BP Filter Using VCII

Abstract

In this paper, a new realization of electronically tunable voltage output second-order low-pass (LP) and band-pass (BP) filter is presented. The circuit has a multiple-input single-output structure, and LP and BP outputs are provided using the same structure. One electronically variable second-generation voltage conveyor (VCII), whose impedance at the Y port can be electronically varied using a control current (I_con), two capacitors, and one resistor are used. By changing the value of I_con, the impedance value at the Y port can be electronically varied; therefore, the value of ω₀ can be tuned. This feature helps to reduce the number of passive components used. Interestingly, the LP and BP outputs are provided at the low-impedance Z port of the VCII, and there is no need for an extra voltage buffer for practical use. The circuit enjoys a simple realization consisting of only 24 MOS transistors. Simulation results using PSpice and 0.18 μm CMOS parameters are provided. The value of ω₀ can be varied from 1.2 MHz to 1.7 MHz, while I_con varies from 0 to 50 µA, with a power consumption variation from 244 µW to 515 µW.

1. Introduction

Filter design represents a widespread and important topic, due to the interesting application in communication, measurement, instrumentation, control, and signal processing [1,2,3]. In recent years, current mode signal processing has been the focus of researchers in the design of various types of active filters. This is attributed to the numerous advantages offered by current mode signal processing, such as simple realization, high-frequency performance, low-voltage operation, etc. [4,5,6,7,8,9]. Importantly, current mode signal processing provides the opportunity of realizing electronically tunable filters, which are highly suitable for the requirements of full integration. These features have enabled various innovative current mode solutions in the realization of active filters [1,2,3,10,11,12,13,14,15,16,17,18,19].

A survey of the literature shows that considerable effort has been devoted to realizing filter topologies based on various current mode active building blocks (ABBs), such as current buffers (CBs) [1,3], second-generation current conveyors (CCIIs) [8,9,10,11], current differential transconductance amplifiers (CDTAs) [13], differential voltage current conveyors (DVCCs) [15,17], current differencing transconductance amplifiers (CCCTAs) [12,18], current feedback operational amplifiers (CFOAs) [19], current differencing buffered amplifiers (CDBAs) [20,21], fully differential CCIIs (FDCCIIs) [22], etc. However, the current mode active filters reported in [1,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,22] suffered from a common weakness of applications requiring voltage signals. In these circuits, the output signal was either in current form, making them unsuitable for applications requiring voltage signals, or in voltage form provided on a high impedance port, necessitating additional voltage buffers for practical use. In addition, the circuits reported in [1,3,10,11,15,17,18,19,20,21,22] were not electronically tunable. Moreover, the CB-based circuit reported in [3], which was able to realize all-pass and notch functions, required additional current followers (CFs) at the outputs for practical application. In the CCII-based circuit presented in [11], up to five active building blocks were used. The CCCTA- and CDTA-based filters presented in [12,13,18] were implemented using BJT technology. The filter reported in [16] suffered from circuit complications, because the FDCCII used as the active building block was realized using 60 MOS transistors, and thus required a high supply voltage of ±1.65 V. The topology of [17] employed three dual-output DVCC blocks with a total number of 84 transistors. The CFOA-based filter presented in [19] required extra current buffers at the outputs for practical use.

Recently, researchers’ focus has been concentrated on the dual circuit of the CCII, referred to as a second-generation voltage conveyor (VCII) [22,23,24,25,26,27]. Owing to the low-impedance voltage output port, VCII is highly suitable for applications requiring output signal in voltage form. A new research area has opened up related to the design and possible applications of the VCII. VCII-based voltage output second-order high-pass (HP), low-pass (LP), band-stop (BS), band-pass (BP) and all-pass (AP) filters have been reported recently [28,29]. However, these structures include more than one ABB. They also lack electronic tuning capability. In this paper, we aim to present second-order LP and BP filters using only one VCII with electronic tunability. The ω₀ of the proposed filters can be tuned using a control current. The organization of this paper is as follows: in Section 2, the proposed circuit is presented. A non-ideal analysis is given in Section 3. Section 4 includes the simulation results, and finally, Section 5 presents the conclusions.

2. The Proposed Circuit

A symbolic representation and internal structure of an electronically tunable VCII is shown in Figure 1 [23]. An E-VCII consists principally of a current buffer between the Y and X ports, and a voltage buffer between the X and Z ports. In the electronically tunable VCII, the input resistance of the CB is shown by r_Y, which is electronically tunable. Matrix Equation (1) shows the operation of the VCII with electronically tunable impedance at Y:

$$\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{X}}\\ {\mathrm{V}}_{\mathrm{Z}}\\ {\mathrm{V}}_{\mathrm{Y}}\end{array}\right]=\left[\begin{array}{ccc}\pm 1& 0& 0\\ 0& 1& 0\\ {\mathrm{r}}_{\mathrm{Y}}& 0& 0\end{array}\right]\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{Y}}\\ {\mathrm{V}}_{\mathrm{X}}\\ {\mathrm{I}}_{\mathrm{Z}}\end{array}\right]$$

(1)

In Equation (1), + and − indicate a VCII⁺ and a VCII⁻, respectively. There is a current buffer between the Y and X ports with a current gain of unity, while there is a voltage buffer between the X and Z ports with a voltage gain of unity. The resistance at the Y port is shown by r_Y, which is electronically tunable. We take advantage of the electronically tunable r_Y instead of adding an external passive resistor.

Figure 2 shows the schematic of the proposed VCII⁻-based BP/LP filter. It is composed of one VCII⁻, one external resistor, and two grounded capacitors. The internal resistance at Y is shown as r_Y, and is exploited to electronically vary the natural frequency of the filter. BP/LP outputs as voltage signals are produced at the Z port.

As can be seen in Figure 3, for I_in = 0, there will be a second-order BP transfer function. The analysis of the proposed BP circuit under ideal conditions is as follows:

By assuming Y port at ground, for I_Y we have:

$${\mathrm{I}}_{\mathrm{Y}}=\frac{{\mathrm{sC}}_1}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}}}{\mathrm{V}}_{\mathrm{in}}$$

(2)

Using Equation (1):

$${\mathrm{I}}_{\mathrm{X}}={\mathrm{I}}_{\mathrm{Y}}$$

(3)

Using Equations (2) and (3), V_X is found as:

$${\mathrm{V}}_{\mathrm{X}}=\frac{{\mathrm{sC}}_1{\mathrm{R}}_2}{\left(1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}}\right)\left(1+{\mathrm{sC}}_2{\mathrm{R}}_2\right)}{\mathrm{V}}_{\mathrm{in}}$$

(4)

Using Equations (1) and (4), V_BP is:

$${\mathrm{V}}_{\mathrm{BP}}=\frac{{\mathrm{sC}}_1{\mathrm{R}}_2}{\left(1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}}\right)\left(1+{\mathrm{sC}}_2{\mathrm{R}}_2\right)}{\mathrm{V}}_{\mathrm{in}}$$

(5)

From Equation (5), ω₀ and Q are found, respectively, as:

$${\mathsf{\omega }}_0=\frac{1}{\sqrt{{\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}}{\mathrm{C}}_2{\mathrm{R}}_2}}$$

(6)

$$\mathrm{Q}=\frac{\sqrt{{\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}}{\mathrm{C}}_2{\mathrm{R}}_2}}{{\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}}+{\mathrm{C}}_2{\mathrm{R}}_2}$$

(7)

As can be seen from (6), the value of ω₀ can be electronically tuned by varying r_Y.

If V_in = 0 and the input signal is applied as I_in, a second-order LP transfer function is achieved, as shown in Figure 4. A similar analysis gives the second-order LP transfer function as:

$${\mathrm{V}}_{\mathrm{LP}}=\frac{{\mathrm{R}}_2}{\left(1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}}\right)\left(1+{\mathrm{sC}}_2{\mathrm{R}}_2\right)}{\mathrm{I}}_{\mathrm{in}}$$

(8)

3. Non-Ideal Analysis

The operation of a VCII⁻ in non-ideal conditions is given by Equation (9). Here, β and α are current gain between the Y and X terminals and voltage gain between the X and Z terminals, respectively. The main parasitic impedances associated with the VCII⁻ ports are shown by r_x (the parasitic resistance related to X port), C_x (parasitic capacitance related to X port) and r_Y (parasitic resistance related to Y port). The ideal values of r_x and C_x are infinity and zero, respectively.

$$\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{X}}\\ {\mathrm{V}}_{\mathrm{Z}}\\ {\mathrm{V}}_{\mathrm{Y}}\end{array}\right]=\left[\begin{array}{ccc}-\mathsf{\beta }& \frac{1}{{\mathrm{r}}_{\mathrm{x}}}+{\mathrm{sC}}_{\mathrm{x}}& 0\\ 0& \mathsf{\alpha }& 0\\ {\mathrm{r}}_{\mathrm{Y}}& 0& 0\end{array}\right]\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{Y}}\\ {\mathrm{V}}_{\mathrm{X}}\\ {\mathrm{I}}_{\mathrm{Z}}\end{array}\right]$$

(9)

Figure 5 shows the proposed second-order BP filter in which all parasitic elements are modeled. Using Equation (9), the transfer function of Figure 5 is found as:

$${\mathrm{V}}_{\mathrm{BP}}=\frac{{\mathrm{s}\mathsf{\alpha }\mathsf{\beta }\mathrm{C}}_1{\mathrm{R}}_{\mathrm{eq}}}{\left[1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}}\right)\left]\left[1+\mathrm{s}({\mathrm{C}}_2+{\mathrm{C}}_{\mathrm{X}}\right){\mathrm{R}}_{\mathrm{eq}}\right]}{\mathrm{V}}_{\mathrm{in}}$$

(10)

where:

$${\mathrm{R}}_{\mathrm{eq}}={\mathrm{r}}_{\mathrm{X}}\left|\right|{\mathrm{R}}_2$$

(11)

From Equation (9), ω₀ and Q are found, respectively, as:

$${\mathsf{\omega }}_0=\frac{1}{\sqrt{{\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}}({\mathrm{C}}_2+{\mathrm{C}}_{\mathrm{X}}){\mathrm{R}}_{\mathrm{eq}}}}$$

(12)

$$\mathrm{Q}=\frac{\sqrt{{\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}}({\mathrm{C}}_2+{\mathrm{C}}_{\mathrm{X}}){\mathrm{R}}_{\mathrm{eq}}}}{{\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}}+({\mathrm{C}}_2+{\mathrm{C}}_{\mathrm{X}}){\mathrm{R}}_{\mathrm{eq}}}$$

(13)

Similar analysis for the proposed second-order LP filter gives:

$${\mathrm{V}}_{\mathrm{LP}}=\frac{{\mathsf{\alpha }\mathsf{\beta }\mathrm{R}}_{\mathrm{eq}}}{\left(1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}}\right)\left(1+\mathrm{s}\left({\mathrm{C}}_2+{\mathrm{C}}_{\mathrm{X}}\right){\mathrm{R}}_{\mathrm{eq}}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(14)

4. CMOS Implementation of VCII⁻ with Electronically Tunable Impedance at the Y Port

Figure 6 shows the CMOS implementation of VCII⁻ with electronically tunable impedance at the Y port. It consists of 24 MOS transistors. Inversion of the current buffer comprising transistors M₁–M₆ is performed to transfer the Y port input current to the X port. The control current I_con is used to change the bias current of common gate transistor M₂; therefore, electronically variable impedance at the Y port is provided. To maintain a constant bias current at the other branches, I_con is also applied to node 2; therefore, only the bias current of M₂ is varied. In addition, to maintain a zero offset voltage at the Y port, bias currents of M₁ and M₂ must be kept equal, so I_con is also applied to node 1.

The voltage buffer consists of transistors M₇–M₁₁, which are a differential pair cascaded by a voltage follower. They are connected in a closed loop configuration so as to decrease Z port impedance and improve the overall accuracy of the buffering action of transferring the X node voltage to the Z node. Transistors M_Bi for i = 1–12 provide the bias and control currents. The electronically variable impedance at the Y port is given by (with the usual meanings of the symbols):

$${\mathrm{r}}_{\mathrm{Y}}=\frac{1}{{\mathrm{gm}}_{\mathrm{M}2}}={\left[\sqrt{{\mathsf{\mu }\mathrm{C}}_{\mathrm{ox}}\frac{{\mathrm{W}}_{\mathrm{M}2}}{{\mathrm{L}}_{\mathrm{M}2}}\left({\mathrm{I}}_{\mathrm{B}1}+{\mathrm{I}}_{\mathrm{con}}\right)}\right]}^{-1}$$

(15)

5. Proposed LP/BP Second-Order Filter Simulation Results

PSpice simulations of the VCII⁻ using 0.18 μm CMOS TSMC technology and a supply voltage of ±0.9 V are presented in Figure 6. The transistor sizes for the used PMOS and NMOS transistors were W = 9 µm, L = 0.9 µm and W = 27 µm, L = 0.9 µm, respectively. The values of bias currents were I_B = I_B1 = I_B2 = I_B3 = 20 µA. The control current I_con was varied from 0 μA to 50 μA. All bias currents were realized by simple current mirrors so as to ensure the best possible voltage swing at each terminal. To validate the proposed tuning technique, a comparison between the theoretical behavior of r_Y according to (15), and the values of the same magnitude extracted from the simulations is presented in Figure 7. In particular, µ = µ_electrons = 0.13 m²/Vs, C_ox = 9.51 × 10⁻⁴ F/m² are constant values dependent on the technology. As can be seen, the trend between the theoretical and simulated curves matches, while the percentage error always remains below 10%. This error mirrors the inaccuracies of M_B1, M_B2 and M_B5–M_B10, which generate I_B1 and I_con, directly impacting the simulated value of r_Y.

The large signal behavior of the used VCII was evaluated by extracting the slew rate (SR) figures both for the current output, X, and for the voltage output, Z. For the former, a ±20 µA step was used, which corresponds to the full ±I_B range, while for the latter, a ±500 mV step was applied to the X terminal, with a 3 pF capacitive load at Z. The current slew rates were: SR⁺_I = 13 × 10³ A/s and SR⁻_I = −0.64 × 10³ A/s, and the voltage slew rates were: SR⁺_V = 1.4 × 10⁸ V/s and SR⁻_V = −6.64 × 10⁶ V/s. As expected, the class A biasing of the input and output stages determines the difference between positive and negative values, with the latter remaining lower due to the sinking capability of the architecture being limited by the biasing current.

Table 1. The simulated characteristics of VCII⁻ with electronically variable impedance at the Y port.

Parameter		Value
rY	Icon = 0 µA	3.43 kΩ
	Icon = 25 µA	2.18 kΩ
	Icon = 50 µA	1.8 kΩ
rX		244 kΩ
rz		48 Ω
α		0.981
β	Icon = 0 µA	1.04
	Icon = 25 µA	1.03
	Icon = 50 µA	1.023
Cx		64 fF
Power dissipation		244–515 µW
SRI (positive, negative)		13 × 103 A/s, −0.64 × 103 A/s
SRV (positive, negative)		1.4 × 108 V/s, −6.64 × 106 V/s

shows the simulation results for the performance parameters and parasitic elements of the used VCII⁻.

The proposed filter presented in Figure 2 was simulated using the VCII⁻ presented in Figure 6. The values of the passive components were C₁ = 100 pF, C₂ = 10 pF and R₂ = 5 kΩ. Figure 8 shows the AC frequency performance of the LP and BP outputs for different values of I_con. On the basis of the simulation results, ω₀ was 1.2 MHz, 1.59 MHz and 1.7 MHz for I_con values of 0 μA, 25 μA and 50 μA, respectively. On the basis of Equation (12), the values of ω₀ were 1.22 MHz, 1.54 MHz and 1.69 MHz, respectively. Fortunately, there is good agreement between the simulation and the calculation.

The robustness of the proposed solutions was tested by running 30 Monte Carlo (MC) simulations at each of the fast, typical, and slow corners. PVT combinations were as follows: SS, ±0.85 V, 80 °C; TT, ±0.9 V, 25 °C; FF, ±0.95 V, −20 °C, whereas for the MC analysis, we considered 3% mismatches in V_th and C_ox of all transistors alongside a 5% variation in the value of the passive elements. The results are summarized in

Table 2. PVT and Monte Carlo simulation results for the magnitude of the filters and their ω₀.

	Value	Max	Min	Mean
Icon = 0 µA	MagnitudeBP	2.78 dB	1.67 dB	2.16 dB
	MagnitudeLP	74.16 dBΩ	73.96 dBΩ	74.05 dBΩ
	ω0	1.25 MHz	1.13 MHz	1.19 MHz
Icon = 25 µA	MagnitudeBP	5.91 dB	4.66 dB	5.23 dB
	MagnitudeLP	74.05 dBΩ	73.84 dBΩ	73.94 dBΩ
	ω0	1.55 MHz	1.40 MHz	1.48 MHz
Icon = 50 µA	MagnitudeBP	7.11 dB	5.70 dB	6.36 dB
	MagnitudeLP	73.94 dBΩ	73.73 dBΩ	73.83 dBΩ
	ω0	1.70 MHz	1.52 MHz	1.61 MHz

. As can be seen, the proposed circuit is robust against mismatches.

The linearity performance of the proposed circuit was checked for different values of I_con at ω₀. The peak-to-peak values of V_in and I_in were 100 mV and 40 µA, respectively. The resulting THD is reported in Figure 9. As can be seen, the maximum value of THD remained below 4% and 8% for the LP and BP outputs, respectively.

Finally, Figure 10 and Figure 11 show a time domain example of both the low-pass and band-pass filters. For the LP filter, an input current of 5 µA was used with frequencies of 100 kHz and 3 MHz. I_con was set to 50 µA. Similarly, for the BP, an input voltage of 10 mV was applied at three different frequencies, of 1.6 MHz, 1 MHz and 3 MHz. I_con was set equal to 50 µA.

Table 3. Comparison between the proposed circuit and other reported works.

Ref	ABB	#of			Electronic Tunability	Outputs	VDD-VSS	Power Dissipation	Extra VB/CB
		ABB	R	C
[1]	CF	1	2	2	No	ILP, IHP, IBP	NA	NA	No
[3]	CF	1	4	2	No	IAP, Inotch	NA	NA	Yes
[10]	CCII	1	2	2	No	VBP, VHP, VLP	±0.75 V	NA	Yes
[13]	CDTA	2	0	2	yes	IBP, ILP, IHP	±2.5 V	870 μW	No
[15]	VDCC	1	1	2	No	ILP, IBP, IHP, IBS, IAP	±0.9 V	NA	No
[16]	FDCCII	1	2	2	No	ILP, IBP, IHP, IBS, IAP	±1.65 V	2.28 mW	No
[17]	DVCC	3	3	2	No	VLP, VBP, VHP, VBR, VAP	±0.9 V	NA	Yes
[18]	CCCTA	3	0	2	yes	IHP, ILP, IBP	±1.85 V	NA	No
[19]	CFOA	1	3	2	No	VBP, VLP	NA	NA	Yes
[20]	CDBA	3	5	2	No	VHP, VBP, VLP	±1.25 V	NA	No
[21]	CDBA	3	3	2	No	VHP, VBP, VLP	±5 V	NA	No
[29]	VCII	1	2	2	No	VBP, VLP	±1.65 V	700 μW	No
Proposed	VCII	1	1	2	yes	VBP, VLP	±0.9 V	244–515 μW	No

shows a comparison between the proposed circuit and others reported in the literature. As can be seen, the structures proposed in [1,3,13,14,15,16,17] provide output signal in current form, and therefore they are not suitable for applications requiring output signal in voltage form. In addition, the circuit of [3] requires an additional current buffer for practical use. The circuit reported in [10] produces output signal in voltage form; however, it needs extra voltage buffer at the output. Similarly, additional voltage buffer is necessary for the circuits presented in [17,19]. The circuits in [20,21] are not electronically tunable, and they suffer from a high supply voltage requirement. The VCII-based topology of [29] provides BP and LP outputs at the low-impedance Z port of VCII. Unfortunately, it is not electronically tunable. In contrast to other works, the proposed VCII-based circuit is electronically tunable, and does not require additional voltage buffers at the output node. More importantly, by taking advantage of the internal impedance at the Y port, the number of passive components is reduced.

6. Conclusions

In this paper, a new realization of an electronically tunable second-order LP/BP filter using VCII⁻ with the property of electronically tunable impedance at the Y port is presented. The proposed circuit consists of one VCII⁻, two capacitors, and one resistor. The output signal is in voltage form provided at the low-impedance Z port of the VCII, which makes it unnecessary to use extra voltage buffer in practical applications. The ω₀ of the proposed transfer functions can be tuned using a control current (I_con), by means of which the impedance at the Y port of VCII can be varied. Therefore, the number of passive resistors used is also reduced, resulting in a simpler circuit and a reduced chip area. A non-ideal analysis is provided. Spice simulation results are reported to show the functionality of the proposed structure.