# Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

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## Abstract

**:**

## 1. Introduction

_{1}and L

_{2}, passive resistors R

_{1}and R

_{2}, and passive capacitors C

_{1}and C

_{2}in Figure 1 is easily achieved by replacing the grounded inductance simulator and the floating inductance simulator instead of these passive inductors [2].

## 2. The Compact CMOS Structure of the VD-DIBA

#### 2.1. Basic Concept of VD-DIBA

_{+}, v

_{−}, z, and v. The low-impedance output voltage terminal is w. Note that the z terminal is also the output current terminal. Figure 2b shows the equivalent schematic of VD-DIBA in an ideal case. The circuit performance is described by the matrix Equation (1) [18].

#### 2.2. Internal Construction of Compact CMOS VD-DIBA

_{1}with a negative feedback connection and the resistor R

_{set}create a transconductance stage (g

_{m}). The transconductance is adjustable with R

_{set}and its value is approximately given by g

_{m}≈1/R

_{set}[41]. If the transconductance value needs to be electronically controlled, then R

_{set}can be replaced, for instance, by a voltage-controlled resistance based on a simple CMOS circuitry. It is worth noting that the negative feedback connection of OTA

_{1}significantly enhances the linearity of the transconductor compared with conventional OTA, which uses the bias current to set its transconductance value [41]. The second multiple-input OTA

_{2}with unity gain feedback is used to transfer the voltage difference between z and v terminals to the output terminal w.

_{1}consists of a differential stage (M1, M2, M5, M10, and M11), followed by two class AB output stages (M6 and M12 and M7 and M13). The C

_{c}

_{1}is the frequency compensation capacitor that ensures the stability of the OTA. The large resistance R

_{MOS}

_{1}is used to set the DC bias voltage V

_{b}at the gates of M12 and M13, whereas the capacitor C

_{1}creates an AC signal path, so class AB output stages are obtained. The differential pair (M1 and M2) is based on multiple-input transistors, realized by an MOS transistor with its gate connected to a parallel connection of a couple of large value resistances R

_{MOSi}along with capacitor C

_{Gi}(i = 1, 2, …, n), where n is the number of required inputs, as depicted in Figure 5. The resistor R

_{MOS}is realized by two MOS transistors operating in a cut-off region, so the chip area occupied by this resistor is minimal. Note that unlike the conventional multiple-input OTA that requires multiple differential pairs, which increase the circuit complexity and power consumption, the proposed only OTA requires one differential pair. Consequently, the CMOS circuitries that use the multiple-input MOS transistors are compact, with a reduced power consumption [34,35,36,37,40,42,43]. The bias current I

_{b}and the transistor M17 set the bias currents and voltages for the OTA. The OTA

_{2}is a copy of OTA

_{1}with one output stage that serves as a voltage differencing unit. It is worth mentioning that the principle of the multiple-input MOS transistor was first presented and experimentally verified in [34,35,36].

## 3. Simulation Result of VD-DIBA’s Performances

_{set}= 15, 20, 25, and 30 kΩ. It is worth noting the tunability and the good linearity obtained over a differential input range of −0.5 to 0.5 V. Figure 7 shows the output voltage V

_{w}against the input voltage V

_{v}for different values of V

_{z}. The correct operation of the voltage differential unit is clearly visible. The frequency responses of V

_{w}/V

_{v}and V

_{w}/V

_{z}are shown in Figure 8. The histogram of the low frequency gain at 1 kHz and the −3 dB bandwidth of these responses with Monte Carlo (MC) analysis are shown in Figure 9, Figure 10, Figure 11 and Figure 12. For Figure 9 and Figure 10, the mean value of the gain is −7.07 and 5.79 mdB, while the standard deviation is 0.19 and 0.39 mdB for the V

_{w}/V

_{v}and V

_{w}/V

_{z}gain, respectively. For Figure 11 and Figure 12, the mean value of the −3 dB bandwidth is 6.37 and 6.11 MHz, while the standard deviation is 121.5 and 89 kHz for the V

_{w}/V

_{v}and V

_{w}/V

_{z}gain, respectively. The MC analysis confirms the low sensitivity of the VD-DIBA to transistor mismatch.

_{DD}= −V

_{SS}were [895 mV, 905 mV]. The results of this analysis, including the minimum, typical, and maximum values, are summarized in Table 2 and confirm the acceptable performance of the circuit under PVT variations.

## 4. The Proposed Floating Inductance Simulators Using VD-DIBAs

#### 4.1. The Proposed Floating Lossless Inductance Simulator

_{1}and v

_{2}, respectively. Moreover, the currents at the first and second port are denoted as i

_{1}and i

_{2}, respectively. The magnitudes of currents i

_{1}and i

_{2}are the output current of the first and second voltage to current converters, respectively. Ideally, the currents i

_{1}and i

_{2}must be equal. Therefore, the transconductance gains of both voltage to current converters are set to be equal to each other (k

_{1}= k

_{2}= k). The input impedance between the first and second ports in Figure 13 is given by

_{1}− v

_{2}. Equation (2) obviously shows that the input impedance of the block diagram presented in Figure 13 can be considered the impedance of a floating lossless inductance simulator, where its equivalent inductance is given by

_{m}

_{1}= g

_{m}

_{2}= g

_{m}, the input impedance between the first and second ports of Figure 14 is given by

_{m}.

#### 4.2. The Proposed Floating Series Inductance-Resistance Simulator

_{m}

_{1}= g

_{m}

_{2}= g

_{m}, the input impedance between the first and second port of Figure 15 is given by

_{m}

_{1}= g

_{m}

_{2}= g

_{m}, the input impedance between the first and second port of Figure 16 is given by

_{m}.

_{2}) is assigned as an output voltage node, then a low output impedance is achieved.

#### 4.3. The Proposed Floating Parallel Inductance-Resistance Simulator

_{1}= k

_{2}= k, the input impedance between the first and second port in Figure 17 is given by

_{m}

_{1}= g

_{m}

_{2}= g

_{m}, the input impedance between the first and second port of Figure 18 is given by

## 5. Simulation Results of Inductance Simulators

_{DD}= −V

_{SS}= 0.9 V, and the bias current was I

_{b}= 50 µA. The transistor aspect ratios of the VD-DIBA shown in Figure 4 are listed in Table 1. For the inductance simulators, the values of the passive components were selected as C = 1 nF and R = 10 kΩ, and the value of the resistor of the transconductors was R

_{set}

_{1}= R

_{set}

_{2}= 10 kΩ. Figure 19 shows the simulated impedance (both the magnitude and phase) of the floating lossless inductance simulator at the first port (v

_{1}) and second port (v

_{2}). The simulated inductance value was about 11.30 mH. The useful frequency range was around 3 decades. It was found that the parasitic resistances in VD-DIBA affect the workability of the active inductor and the performance of the proposed inductance simulator at a high frequency is affected by the parasitic capacitances. As described in (5), the inductance value of the lossless active inductor is adjusted by g

_{m}. This theoretical expectation was confirmed by the simulation result in Figure 20, where there are four values of R

_{set}(10, 20, 30, and 40 kΩ). The inductance values simulated from these R

_{set}values were 11.30, 21.51, 30.87, and 39.47 mH, respectively. As shown in the result, the inductance is proportional to the R

_{set}value. The simulated results in Figure 20 are consistent with the expectation in (5).

_{set}= 10 kΩ is shown in Figure 21. The simulated inductance and resistance values are about 12.39 mH and 9.22 kΩ, respectively. The impedance of the floating series L-R for different values of R

_{set}is shown in Figure 22, where R

_{set}had four values (10, 20, 30, and 40 kΩ). The inductance values simulated from these R

_{set}values were 12.39, 23.38, 30.92 and 35.29 mH, respectively. Additionally, the resistance values simulated from these R

_{set}values were 9.22, 16.88, 23.41, and 29.04 kΩ, respectively. The simulation performed on the floating parallel inductance-resistance simulator is shown in Figure 23. The simulated inductance and resistance values were about 11.28 mH and 9.43 kΩ, respectively. The impedance of the floating parallel L-R for different values of R

_{set}is shown in Figure 24, where R

_{set}was changed to four values (10, 20, 30, and 40 kΩ). The inductance values simulated from these R

_{set}values were 11.28, 21.48, 30.81, and 39.41 mH, respectively. Furthermore, the resistance values simulated from these R

_{set}values were 9.22, 17.36, 24.08, and 29.79 kΩ, respectively.

_{eq}

_{2}, while the series R

_{eq}

_{1}and L

_{eq}

_{1}circuit is implemented by the series inductance-resistance simulator shown in Figure 15. It should be noted that in the case of the input voltage signal applied at the first port (v

_{1}), only one VD-DIBA is required for the realization of the series L-R simulator. As mentioned in the Introduction section, the procedure used to synthesize the high order ladder filter is easy to understand and implement without using advanced or complicated mathematics by replacing the passive inductors with the proposed inductance simulators. The completed 4th order elliptic LP ladder filter using VD-DIBAs-based inductance simulators is shown in Figure 26. It can be seen that the input voltage node is a high impedance one.

_{1}= C

_{2}= C

_{3}= 1.04 nF and R

_{L}= 10 kΩ. The resistors and capacitors in the inductance simulators were C = 1.04 pF and R = 10 kΩ, respectively, while the value of R

_{set}was R

_{1set}= R

_{2set}= R

_{3set}= 9.07 kΩ. Figure 27 shows the frequency and responses of the 4th order elliptic LP ladder filter based on VD-DIBA and resistor-inductor-capacitor (RLC) circuit. The gain is −6.027 dB and the bandwidth (BW) is 13.31 kHz, while for the RLC, the gain is −6.02 dB and BW is 13.33 kHz. It is evident that the values are close to each other. Figure 28 shows the frequency responses of the LP ladder filter with different R

_{set}

_{1}and R = R

_{set}

_{1}= R

_{2set}= R

_{3set}= 7.07, 9.07, and 11.07 kΩ. The BW was 15.39, 13.31, and 11.8 kHz, respectively. The transient response of the 4th order LP ladder filter realized from the proposed inductance simulators is shown in Figure 29, where a sine wave signal with a peak-to-peak of 1 V at 1 kHz was applied to the input of the filter. The output signal has a total harmonic distortion (THD) of 1%. The THD versus the peak-to-peak value of the input signal is shown in Figure 30. The root mean square (RMS) value of the output noise of the filter is 60 µV, so the dynamic range is 80 dB for 2% THD.

## 6. Experimental Results of Inductance Simulators

_{m}= I

_{B}/2 V

_{T}, where the I

_{B}is the bias current and V

_{T}is the thermal voltage. To evaluate the impedance of the floating inductance simulators, the input current signal applied at the first (v

_{1}) and second (v

_{2}) ports was implemented by the voltage to current converter using AD844 and R

_{x}, as shown in Figure 32 (the small value resistor, R

_{s}, was connected to avoid oscillation in the tested circuits). The power supply voltage used was ±5 V, which was implemented by employing a GW Instek GPS-3303 power supply. C = 1 nF, R= 1 kΩ, and I

_{B}

_{1}= I

_{B}

_{2}= 180 μA, as measured by the Fluke 289 digital multimeter. From (5), the calculated inductance was 0.289 mH. The sinusoidal input signal and the measured output waveforms were registered with the Keysight DSOX1102G oscilloscope. Figure 33 shows the experimental impedance (both the magnitude and phase) of the floating lossless inductance simulator at the first port (v

_{1}) and second port (v

_{2}). The experimental inductance value was about 0.271 mH. The useful frequency range was more than two decades. It was found that the parasitic resistances in VD-DIBA affect the workability of the active inductor, as well as the performance of the proposed inductance simulator at a high frequency, which is affected by the parasitic capacitances. The transient responses of the input current (i

_{1}) and voltage v

_{1}are shown in Figure 34, where a sine wave signal with a peak-to-peak of 20 mVpp at 200 kHz was applied to the input (vs) of the V to I converter in Figure 32. This yielded the input current i1 of 20 µApp. The theoretical voltage drop at port v

_{1}should be 6.81 mVpp (v

_{1}= i

_{1}* 2πfL

_{eq}, where f = 200 kHz and L

_{eq}= 0.271 mH). The measured voltage drop at port v1 was 7.11 mVpp. It can be seen in Figure 34 that the phase of current was delayed compared to the phase of voltage by around 90 degrees, which proves that the proposed circuit works well as a passive inductor. The impedance at port v

_{1}of the inductance simulator for different values of I

_{B}is shown in Figure 35, where the values of I

_{B}were set at 78, 180, and 358 µA. The experimental inductance values obtained from these I

_{B}values were 0.644, 0.271, and 0.138 mH, respectively. As shown in the result, the inductance is electronically controlled by I

_{B}.

_{B}is shown in Figure 37, where I

_{B}values were changed to obtain the three values of 78, 180, and 358 µA. The experimental inductance values obtained from these I

_{B}values were 1.38, 0.346, and 0.15 mH, respectively, while the experimental resistance values obtained from these I

_{B}values were 0.623, 0.264, and 0.135 kΩ, respectively. The experimental result for the floating parallel inductance-resistance simulator connection is shown in Figure 38, where the inductance and resistance values were about 0.269 mH and 0.25 kΩ, respectively. The impedance of the floating parallel inductance-resistance connection for different values of IB values is shown in Figure 39, where I

_{B}values were set as 78, 180, and 358 µA. The corresponding inductance values were 0.639, 0.269, and 0.132 mH, respectively, while the resistance values were 0.603, 0.25, and 0.121 kΩ, respectively.

_{1}= C

_{2}= C

_{3}= 10 nF and R

_{L}= 0.25 kΩ. The resistors and capacitors in the inductance simulators were C = 1 nF and R = 1 kΩ, respectively, while the value of the bias current was I

_{B1}= I

_{B2}= I

_{B3}= 208 µA. This yielded L

_{eq1}= L

_{eq2}= 0.25 mH and R

_{eq1}= 0.25 kΩ. Figure 40 shows the experimental frequency responses of the 4th order elliptic LP ladder filter based on VD-DIBA compared with the theoretical response of the RLC prototype filter. The gain is −5.9 dB and bandwidth (BW) is 83.17 kHz, while for the RLC prototype, the gain is −6.02 dB and BW is 85.41 kHz. The transient responses of the LP ladder filter are shown in Figure 41, where sine wave signals with peak-to-peak of 20 mVpp at 10, 70, and 100 kHz were applied to the input of the filter. Figure 42 shows the experimental frequency and responses of the LP ladder filter with a different bias current and I

_{B}

_{1}= I

_{B}

_{2}= I

_{B}

_{3}= 52, 104, and 208 µA, respectively. The BW was 19.95, 57.54, and 83.17 kHz, respectively. It was found that the BW or the cut-off frequency is electronically controlled by the bias currents.

## 7. Comparison

## 8. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

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**Figure 1.**Design of the 4th ladder bandpass filter by replacing the inductance simulators instead of passive inductors [2].

**Figure 2.**(

**a**) The symbolic representation of the voltage differencing differential input buffered amplifier (VD-DIBA) and (

**b**) VD-DIBA equivalent circuit [18].

**Figure 5.**The multiple-input MOS transistor: (

**a**) Symbol; (

**b**) realization; and (

**c**) realization of R

_{MOS}[34].

**Figure 15.**Block diagram showing the synthesis of the floating series inductance-resistance simulator.

**Figure 17.**Block diagram demonstrating the synthesis of the floating parallel inductance-resistance simulator.

**Figure 34.**The current and voltage measured at port v

_{1}of the floating lossless inductance simulator.

**Figure 40.**The experimental frequency responses of the LP ladder filter based on VD-DIBA compared with the theoretical response of the RLC prototype filter.

Component | W/L [µm/µm] |
---|---|

M_{1}–M_{4} | 90/3 |

M_{5}–M_{9} | 2 × 90/3 |

M_{10}, M_{11}, M_{14}, M_{15}, M_{17} | 30/3 |

M_{12}, M_{13}, M_{16} | 2 × 30/3 |

M_{R} | 4/5 |

C_{c}_{1}, C_{c}_{2}, C_{1}, C_{2} = 2.6 pF | |

C_{Gi} = 0.5 pF | |

+V_{DD} = −V_{SS} = 0.9 V | |

I_{b} = 50 µA |

Min | tt | Max | |
---|---|---|---|

Gain V_{w}/V_{v} [mdB] | −12.68 | −7.72 | −5.42 |

Gain V_{w}/V_{z} [mdB] | −25.45 | 5.79 | 77.6 |

−3 dB V_{w}/V_{v} [MHz] | 5.33 | 6.36 | 7.48 |

−3 dB V_{w}/V_{z} [MHz] | 5.11 | 6.11 | 7.73 |

G_{m} [µS] for R_{set} = 15 kΩ | 71 | 71.2 | 71.4 |

**Table 3.**Comparison of the proposed inductance simulators and other inductance simulators using an active building block.

Ref | Type | No. of ABB | No. of R + C | Grounded Capacitor | Electronic Tune | Function | Design Procedure | No Need for ABB with Multiple Output Terminal | Free from Passive Element Matching Condition | Technology | Results | Supply Voltages and Power | Application in Filter Design and Performances |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|

[31] | Grounded | 1 VD-DIBA | 1 + 1 | Yes | Yes | Series LR Parallel LR | No | Yes | Yes | 0.18 μm TSMC CMOS and Commercial ICs | Simulation | ±0.9 V and N/A | 2nd order LPF and HPF |

[32] | Grounded | 1 VD-DIBA | 1 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | 0.35 μm MIETEC CMOS | Simulation | ±2 V and N/A | 2nd order BPF |

Floating | 2 VD-DIBA | 1 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | 0.35 μm MIETEC CMOS | Simulation | ±2 V and N/A | 2nd order BPF | |

[33] | Grounded | 2 VD-DIBA | 0 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | CMOS and Commercial ICs | Simulation | ±1 V and N/A | 2nd order BPF |

Floating | 3 VD-DIBA | 0 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | CMOS and Commercial ICs | Simulation | ±1 V and N/A | 2nd order BRF | |

[44] | Floating | 2 VDDDA | 1 + 1 | Yes | Yes * | Lossless L Series LR Parallel LR | No | Yes | Yes | Commercial ICs | Simulation and Experiment | ±5 V at 0.66 W | 3th order LPF and 4th order BPF |

[46] | Floating | 2 FTFNA | 1 + 2 | Yes | Yes | Lossless L | No | Yes | No | 0.18 μm TSMC CMOS | Simulation | ±1.65 V at 8.59 mW | 2nd order BPF and LPF |

[47] | Grounded | 1 FTFNA | 1 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | 0.18 μm TSMC CMOS and Commercial ICs | Simulation and Experiment | ±1.65 V at 1.28 mW | 5th HPF and 2nd universal filter |

Floating | 1 FTFNA | 1 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | 0.18 μm TSMC CMOS and Commercial ICs | Simulation and Experiment | ±1.65 V at 1.28 mW | 2nd BRF | |

[48] | Grounded | 1 VCII | 2 + 1 | Yes | No | Lossless L | No | Yes | Yes | 0.18 μm TSMC CMOS and Commercial ICs | Simulation and Experiment | ±0.9 V at 0.65 mW | 2nd HPF |

[49] | Floating | 1 DDCC | 2 + 1 | No | No | Negaitive lossless L Parallel LR Series LR | No | Yes | Yes | 0.13 μm CMOS and Commercial ICs | Simulation and Experiment | ±0.75 V at 2.06 mW and 1.96 mW | 2nd LPF, HPF, and 4th LPF |

[50] | Floating | 1 M-CDTA | 0 + 1 | Yes | Yes | Lossless L | No | No | Yes | 0.5 μm CMOS | Simulation | N/A | 2nd BPF and 4th LPF |

[51] | Floating | 3 VDBA | 0 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | 0.25 μm TSMC CMOS and Commercial ICs | Simulation and Experiment | ±0.75 V at 1.13 mW | 2nd BPF and LPF |

[52] | Grounded | 1 CCII & 2 IVB | 2 + 1 | No | No | Lossles L | No | Yes | Yes | 0.18 μm TSMC CMOS | Simulation | ±1.25 V and N/A | 2nd BPF with −40 dB of IM3 and 15.34 dBm of IIP3 |

[53] | Grounded | 2 CFOA | 3 + 1 | Yes | No | Lossless L | No | Yes | No | 0.13 μm IBM CMOS & Commercial ICs | Simulation and Experiment | ±0.75 V at 3.53 mW | 2nd BPF |

[54] | Floating | 2 VDBA | 1 + 1 | No | Yes | Series LR Parallel LR | No | Yes | Yes | 0.25 μm TSMC CMOS and Commercial ICs | Simulation and Experiment | ±0.75 V at 1.28 mW and 1.15 mW | 2nd LPF |

[55] | Grounded | 1 ZC-CFCCC | 0 + 1 | Yes | Yes | Lossless L | No | No | Yes | 0.18 μm TSMC CMOS | Simulation | ±2.5 V at 2.47 mW | 2nd BPF with 0.3–2.4% of THD at 10–150 mV of V_{in} |

Floating | 2 ZC-CFCCC | 0 + 1 | Yes | Yes | Lossless L | No | No | Yes | 0.18 μm TSMC CMOS | Simulation | ±2.5 V at 4.94 mW | 4th LPF with 0.2–7% of THD at 10–150 mV of V_{in} | |

[56] | Grounded | 2 CC-CFA | 0 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | BiCMOS | Simulation | ±1.5 V and N/A | 2nd universal filter |

Floating | 3 CC-CFA | 0 + 1 | Yes | Yes | Lossless L | No | Yes | Yes | BiCMOS | Simulation | ±1.5 V and N/A | 2nd BPF | |

[57] | Grounded | 1 CFOA | 3 + 1 | Yes | No | Lossless L | No | Yes | No | 0.13 μm IBM CMOS and Commercial ICs | Simulation and Experiment | ±0.75 V at 3.05 mW | 2nd universal filter |

[58] | Grounded | 1 LT1228 | 1 + 1 | No | Yes | Lossless L Parallel LR Series LR | No | Yes | Yes | Commercial ICs | Simulation and Experiment | ±5 V at 56.5 mW, 56.4 mW, and 56.8 mW | 2nd BPF |

[59] | Grouned | 1 MDVCC | 2 + 1 | Yes | No | Lossless L | No | Yes | No | 0.13 μm IBM CMOS and Commercial ICs | Simulation and Experiment | ±0.75 V at 1.62 mW | 2nd BPF |

[60] | Grounded | 1 CDBA | 2 + 1 | Yes | No | Parallel LR | No | Yes | Yes | Commercial ICs | Simulation | ±12 V and N/A | N/A |

This work | Floating | 2 VD-DIBA | 1 + 1 | Yes | Yes * | Lossless L Parallel LR Series LR | Yes | Yes | Yes | 0.18 μm TSMC CMOS and Commercial ICs | Simulation and Experiment | ±0.9 V at 1.98 mW | 4th order LPF with 80 dB for 2% THD of DR and 46 µVrms of output noise |

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**MDPI and ACS Style**

Jaikla, W.; Bunrueangsak, S.; Khateb, F.; Kulej, T.; Suwanjan, P.; Supavarasuwat, P.
Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs. *Electronics* **2021**, *10*, 684.
https://doi.org/10.3390/electronics10060684

**AMA Style**

Jaikla W, Bunrueangsak S, Khateb F, Kulej T, Suwanjan P, Supavarasuwat P.
Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs. *Electronics*. 2021; 10(6):684.
https://doi.org/10.3390/electronics10060684

**Chicago/Turabian Style**

Jaikla, Winai, Sirigul Bunrueangsak, Fabian Khateb, Tomasz Kulej, Peerawut Suwanjan, and Piya Supavarasuwat.
2021. "Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs" *Electronics* 10, no. 6: 684.
https://doi.org/10.3390/electronics10060684