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Open AccessArticle

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

1
Dipartimento di Ingegneria Elettrica ed Elettronica, Università degli Studi di Cagliari, Piazza d’Armi snc, 09123 Cagliari, Italy
2
Dipartimento di Chimica e Farmacia, Università degli Studi di Sassari, Via Vienna 2, 07100 Sassari, Italy
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(1), 73; https://doi.org/10.3390/electronics10010073
Received: 16 November 2020 / Revised: 26 December 2020 / Accepted: 30 December 2020 / Published: 3 January 2021
(This article belongs to the Section Circuit and Signal Processing)
With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived. View Full-Text
Keywords: high level synthesis; power management; clock gating; hardware acceleration; reconfigurable computing; design automation high level synthesis; power management; clock gating; hardware acceleration; reconfigurable computing; design automation
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MDPI and ACS Style

Ratto, F.; Fanni, T.; Raffo, L.; Sau, C. Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators. Electronics 2021, 10, 73. https://doi.org/10.3390/electronics10010073

AMA Style

Ratto F, Fanni T, Raffo L, Sau C. Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators. Electronics. 2021; 10(1):73. https://doi.org/10.3390/electronics10010073

Chicago/Turabian Style

Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo. 2021. "Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators" Electronics 10, no. 1: 73. https://doi.org/10.3390/electronics10010073

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