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Nanomaterials 2019, 9(2), 181; https://doi.org/10.3390/nano9020181

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Key Laboratory of Wide Band-Gap Semiconductor technology, School of Microelectronics, Xidian University, Xi’an 710071, China
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Received: 21 December 2018 / Revised: 12 January 2019 / Accepted: 28 January 2019 / Published: 1 February 2019
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Abstract

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations. View Full-Text
Keywords: TFET; BTBT; InAs/Si; heterojunction; staggered-bandgap; source-pocket; 2D Poisson equations; parabolic approximation; Kane’s model; current model TFET; BTBT; InAs/Si; heterojunction; staggered-bandgap; source-pocket; 2D Poisson equations; parabolic approximation; Kane’s model; current model
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Lu, H.; Lu, B.; Zhang, Y.; Zhang, Y.; Lv, Z. Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture. Nanomaterials 2019, 9, 181.

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