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Micromachines 2019, 10(2), 124; https://doi.org/10.3390/mi10020124

In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

1
Samsung Electronics Company, Ltd., Hwasung 18448, Korea
2
School of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, Korea
*
Author to whom correspondence should be addressed.
Received: 24 December 2018 / Revised: 3 February 2019 / Accepted: 5 February 2019 / Published: 14 February 2019
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Abstract

Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%. View Full-Text
Keywords: 3D-stacked; DRAM; in-DRAM cache; low-latency; low-power 3D-stacked; DRAM; in-DRAM cache; low-latency; low-power
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Shin, H.H.; Chung, E.-Y. In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs. Micromachines 2019, 10, 124.

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