Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations
Abstract
:1. Introduction
2. Neuromorphic Computing
3. CMOS Neuromorphic Systems
- Winner-Take-All (WTA) is a brain inspired mechanism implemented by inhibitory interactions between neurons in a population that compete to inhibit each other. The result is that the neuron in the population receiving the highest input remains active while silencing the output of the rest of the neurons. Hardware modules of spiking Winner-take-all networks have been reported [112].
- Hardware implementations of spiking neural networks for saliency maps detection have been proposed as emulators of brain attention mechanisms [116].
- The IBM TrueNorth chip is based upon distributed digital neural models aimed at real-time cognitive applications [120].
- The Heidelberg BrainScaleS system uses wafer-scale above threshold analogue neural circuits running 10,000 times faster than biological real time aimed at understanding biological systems, and in particular, long-term learning [124].
- The Manchester SpiNNaker is a real-time digital many-core system that implements neural and synapse models in software running on small embedded processors, again primarily aimed at modelling biological nervous systems [125].
- The Intel Loihi chip consists of a mesh of 128 neuromorphic cores with an integrated learning engine on-chip [126].
- The Darwin Neural Processing Unit is a hardware co-processor with digital logic specifically designed for resource-constrained embedded applications [127].
- A digital realization of a neuromorphic chip (ODIN) containing 256 neurons and 64 K 4-bit synapses exhibiting a spike-driven synaptic plasticity in FDSOI 28 nm technology has recently been developed in the University of Leuven [129].
4. Hybrid Memristor-CMOS Systems
- Memristors can be scaled down to feature sizes below 10 nm.
- They can retain memory states for years.
- They can switch with nanosecond timescales.
5. Learning with Memristors (STDP)
6. Future Perspective
Author Contributions
Funding
Conflicts of Interest
References
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Feature | ANN | SNN |
---|---|---|
Data processing | Frame-based | Spike-based |
Latency | High | Low |
Pseudo-simultaneity | ||
Time resolution | Low | High |
Preservation of spatio-temporal | ||
correlation | ||
Time processing | Sampled | Continuous |
Neuron model complexity | Low | High |
Recognition accuracy | Higher | Lower |
Hardware multiplexing | Possible | Not possible |
System scale-up | Ad hoc | Adding modules |
Recognition speed | Low | High |
Independent on input stimulus | Dependent on input statistics | |
Dependent on hardware resources | ||
Dependent on system complexity | Not dependent on system complexity | |
Power consumption | Determined by processor power | Determined by power-per-event |
and memory fetching | processing in modules | |
Independent on input stimulus | Dependent on stimulus statistics | |
Recurrent topologies | Need to iterate until converge | Instantaneous |
Platform | Human Brain | Neurogrid | BrainScaleS | Truenorth | SpiNNaker | Loihi | Darwin | ROLLS | DYNAPs | ODIN |
---|---|---|---|---|---|---|---|---|---|---|
Technology | Biology | Analog, sub-threshold | Analog, over threshold | Digital, fixed | Digital, programmable | Digital, programmable | Digital, programmable | Mixed-signal, sub-threshold | Mixed-signal, subthreshold | Digital, programamble |
Feature size | 10 m | 180 nm | 180 nm | 28 nm | 130 nm | 14 nm | 180 nm | 180 nm | 180 nm | 28 nm |
# transistors | 23 M | 15 M | 5.4 B | 100 M | 2.07 B | ≈M | 12.2 M | - | - | |
Chip size | 1.7 cm | 0.5 cm | 4.3 cm | 1 cm | 60 mm | 25 mm | 51.4 mm | 43.79 mm | 0.086 mm | |
# neurons (chip) | 65 k | 512 | 1 M | 16 k | 131 k | ≈M | 256 | 1 k | 256 | |
# synapses (chip) | 100 M | 100 k | 256 M | 16 M | 126 M | Programmable | 128 k | 64 k | 64 k | |
# chips per board | 16 | 352 | 16 | 48 | - | - | - | - | - | |
# neurons (board) | 1 M | 200 k | 16 M | 768 k | - | - | - | - | - | |
# synapses (board) | 4 B | 40 M | 4 B | 768 M | - | - | - | - | - | |
Energy per connection | 10 fJ | 100 pJ | 100 pJ | 25 pJ | 10 nJ | 81 pJ | 10 nJ | >77 fJ | 30 pJ | 12.7 pJ |
On-chip learning | Yes | No | Yes | No | Yes | Yes | Yes | Yes | No | Yes |
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Camuñas-Mesa, L.A.; Linares-Barranco, B.; Serrano-Gotarredona, T. Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations. Materials 2019, 12, 2745. https://doi.org/10.3390/ma12172745
Camuñas-Mesa LA, Linares-Barranco B, Serrano-Gotarredona T. Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations. Materials. 2019; 12(17):2745. https://doi.org/10.3390/ma12172745
Chicago/Turabian StyleCamuñas-Mesa, Luis A., Bernabé Linares-Barranco, and Teresa Serrano-Gotarredona. 2019. "Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations" Materials 12, no. 17: 2745. https://doi.org/10.3390/ma12172745