A Partial Power Processing SEPIC Converter for Photovoltaic Applications

Abstract

This paper presents the analysis, design, and experimental validation of a Partial Power Processing (PPP) Single-Ended Primary Inductor Converter (SEPIC) for photovoltaic (PV) applications. The proposed topology limits the fraction of processed power through the active switching stage, thereby reducing MOSFET RMS current and associated conduction losses and improving overall conversion efficiency. A complete analytical framework is developed, including steady-state modeling, state-space formulation, and small-signal analysis. The theoretical results are validated through MATLAB/Simulink simulations and laboratory-scale experimental tests under multiple loading conditions. Comparative analysis against a conventional Full Power Processing (FPP) SEPIC converter demonstrates that the proposed PPP configuration achieves efficiencies up to 95% in simulation and up to 93% experimentally, compared to 87% for the FPP counterpart under identical nominal conditions ($V_{\mathrm{in}}=18$ V, $f_{\mathrm{s}}=70$ kHz). Additionally, the PPP approach reduces the MOSFET RMS current by more than 50%, which directly translates into lower conduction losses and reduced device power dissipation. The results confirm that the proposed PPP-SEPIC converter constitutes a technically viable and energy-efficient solution for photovoltaic DC–DC power conversion systems.

1. Introduction

In recent years, global energy demand has increased, primarily driven by sustained population growth and the widespread electrification of modern devices and infrastructure. Simultaneously, worldwide energy consumption has been strongly associated with global warming due to emissions produced by conventional fossil-fuel-based generation systems. This environmental concern has intensified, as extreme temperature and precipitation records are increasingly reported on a yearly basis. Consequently, clean and sustainable energy sources have become a central focus of governmental policies and scientific research worldwide [1].

Among the various renewable energy sources currently deployed, hydroelectric, wind, and solar energy remain the most widely utilized technologies [2,3]. However, over the past decade, photovoltaic (PV) energy has exhibited the most rapid and sustained growth rate [4]. This expansion is largely attributed to the inherent abundance of solar resources and the continuous technological advancements in PV materials and manufacturing processes. Extensive research efforts have contributed to improving conversion efficiency while substantially reducing the cost of PV modules.

PV systems are typically interfaced with downstream power stages or the grid through multiple power conversion stages, including a DC–DC converter that regulates and adapts the voltage generated by the PV panels [5,6,7]. This stage is particularly critical because PV panels inherently produce relatively low output voltages, which must be efficiently boosted to meet grid or load requirements. Therefore, a wide range of converter topologies has been extensively developed and comparatively analyzed in the literature.

Power converters can be systematically classified according to the proportion of energy they process. Conventional Full Power Processing (FPP) converters handle the total power supplied by the source, whereas Partial Power Processing (PPP) converters process only a fraction of the transferred energy [8,9]. A general classification of these schemes is illustrated in Figure 1. Among the available PPP topologies, the PPP-SEPIC converter has attracted considerable attention due to its capability to efficiently step up voltage while reducing processed power and semiconductor stress [10,11,12].

This work introduces and evaluates a PPP-SEPIC converter specifically tailored for photovoltaic applications. Unlike its full-power counterpart, the proposed architecture confines the fraction of power processed by the active conversion stage, thereby reducing MOSFET RMS current and associated conduction losses while consistently improving overall conversion efficiency. The research focuses on the analytical design and performance evaluation of the converter, employing a partial power processing approach that inherently minimizes the amount of energy handled by the switching stage.

Although the PPP concept has been previously reported, its implementation using a SEPIC-based PPP structure for photovoltaic applications has not been thoroughly investigated under a complete analytical framework. The originality of this work therefore lies in the rigorous steady-state and small-signal modeling of the proposed topology, together with its experimental validation under a defined PV operating condition (17 V, approximately 100 W). It is important to clarify that the analytical model considers $V_d$ = 18 V as the nominal design value, while 17 V corresponds to the photovoltaic module operating point used in simulation and experimental validation. Furthermore, a systematic and quantitative comparison against a conventional FPP-SEPIC converter is provided, demonstrating the practical advantages of the PPP approach in terms of efficiency, component stress reduction, weight, size, and overall system cost [13].

2. Proposed PPP Architecture

Figure 2 illustrates the proposed PPP-SEPIC architecture. Capacitor $C_1$ operates as the coupling element, blocking the DC component between the input branch and the active conversion path while simultaneously enabling controlled energy transfer and the inherent buck–boost functionality. Capacitor $C_2$ is used to filter the output voltage ripple, thereby ensuring a stable and well-regulated output voltage $V_{\mathrm{o}}$.

The inductive elements provide controlled and continuous energy storage and delivery. Specifically, inductor $L_1$ smooths the current drawn from the source, thereby reducing input current ripple and improving source-side stability. Meanwhile, the magnetizing inductance $L_{\mathrm{m}}$ of the coupled inductor (transformer) governs the energy transfer to the output and inherently limits the fraction of power processed by the active switching stage, which constitutes the core principle of PPP.

The switch is driven by a PWM control signal. The corresponding duty cycle $d\left(t\right)$ for the control signal is defined as follows:

$$d\left(t\right)={\displaystyle \frac{1}{T_{\mathrm{s}}}}{\int }_t^{t+T_{\mathrm{s}}}q\left(\tau \right)d\tau ,$$

(1)

where $T_{\mathrm{s}}$ is the switching period, which is related to the switching frequency by $T_{\mathrm{s}}=1/f_{\mathrm{s}}$. The function $q\left(t\right)$ denotes the PWM switching function associated with the main switch, defined as $q\left(t\right)=1$ when the switch is ON and $q\left(t\right)=0$ when it is OFF.

2.1. Proposed Architecture Analysis

Since the proposed architecture includes only one control signal, two equivalent circuits can be obtained depending on the switch state when the converter operates in CCM. These equivalent circuits are shown in Figure 3. The converter operates in two intervals within each switching cycle:

Interval 1—Switch in conduction (ST1—ON):

When the switch is turned ON, the input inductor $L_1$ is directly energized by the input source, resulting in a linear increase of its current according to the applied voltage and inductance value. Simultaneously, the coupling capacitor $C_1$ transfers energy to the magnetizing inductance $L_{\mathrm{m}}$ of the coupled inductor, thereby establishing controlled energy storage within the magnetic structure. During this interval, the diode remains reverse-biased, effectively isolating the output stage from the input branch. Consequently, the load R is exclusively supplied by the output capacitor $C_2$, which gradually discharges to maintain the regulated output voltage. The energy stored in both $L_1$ and $L_{\mathrm{m}}$ increases approximately linearly, as determined by the instantaneous voltage conditions.

Interval 2—Switch in cutoff (ST2—OFF):

When the switch is turned OFF, the stored energy in $L_1$ and $L_{\mathrm{m}}$ is simultaneously released and transferred to the output stage through the forward-biased diode. During this interval, the magnetic coupling element effectively contributes to voltage adaptation according to the transformer turns ratio, thereby modulating the output voltage level. The output capacitor $C_2$ is recharged while supplying the load, ensuring voltage continuity and reduced ripple. Meanwhile, capacitor $C_1$ is naturally recharged, preparing the converter for the subsequent switching cycle. The combined mechanism of direct and magnetically coupled energy transfer limits the fraction of total power processed by the active switching device, which constitutes the fundamental principle of PPP. Figure 4 illustrates both switching states.

Unlike a conventional boost DC–DC converter, where the entire input power is processed by the switching stage (full power processing), the proposed PPP-SEPIC topology allows a portion of the input power to be directly transferred to the load, while only a controlled fraction is processed through the active branch. The coupled transformer plays a fundamental role in this mechanism by enabling power sharing between the direct and processed paths.

The transformer not only provides galvanic isolation but also introduces an additional design degree of freedom through its turns ratio $n={\displaystyle \frac{n_2}{n_1}}$. The turns ratio is selected according to the desired output voltage and the nominal operating duty cycle. By properly choosing n, the converter can operate within a reduced duty-cycle range (approximately 0.1–0.7 in this design), which corresponds to the region of highest efficiency and reduced RMS current stress.

Therefore, the proposed topology differs conceptually from a boost converter in that it does not process the entire input power through the switching stage; instead, it regulates only a fraction of it, thereby improving overall efficiency and reducing component stress.

Table 1. Architectural Comparison Between FPP-SEPIC and PPP-SEPIC Converters.

	FPP-SEPIC	PPP-SEPIC
Power processing	Full processing ($\gamma \approx 1$)	Partial processing ($\gamma <1$)
Topology	Conventional SEPIC	Proposed PPP-SEPIC
Transformer	No	Yes
Control method	PWM	PWM
Energy processed by switch	100% of input power	Fraction of input power
Voltage regulation principle	Entire power through active stage	Direct + processed power paths
Number of components	6	6

presents a conceptual and structural comparison between the FPP-SEPIC and PPP-SEPIC topologies. Both converters are evaluated under identical nominal design assumptions to ensure a fair and consistent structural comparison. Although the two topologies share similar structural characteristics, the PPP-SEPIC fundamentally differs in the manner in which power is distributed between the direct and actively processed paths.

Despite employing a similar number of passive and active components and exhibiting comparable theoretical voltage conversion ratios, the PPP-SEPIC topology fundamentally differs in the manner in which power is distributed between the direct and actively processed paths. This distinct energy distribution mechanism constitutes the primary source of its performance enhancement, which is analyzed and validated in Section 4.

2.2. Architecture for Comparison

In order to thoroughly evaluate the characteristics and practical advantages of the proposed configuration, two converter topologies are comparatively analyzed. Figure 5 illustrates a conventional FPP-SEPIC converter, in which the entire energy generated by the photovoltaic source is necessarily processed through the active switching stage [14,15]. This configuration therefore represents an appropriate baseline for structurally and functionally assessing the improvements introduced by the PPP-based approach.

Previous studies have consistently reported that PPP converters can achieve high conversion efficiencies ranging from 94% to 98%. These results have been critically analyzed and systematically incorporated into the design methodology of the proposed PPP-SEPIC converter [16]. In particular, the reported efficiency benchmarks were carefully considered during the selection of the turns ratio, duty-cycle operating range, and component sizing, thereby ensuring that the proposed topology operates within its optimal efficiency region.

3. Converter Mathematical Model

Using the equations of the proposed circuit and the equivalent circuits shown in Figure 3, the averaged equations can be derived to obtain the mathematical model of the converter [17]. The averaged dynamic model for the inductor currents and capacitor voltages is presented in Equations (2)–(5).

$$\begin{array}{cc}\hfill L_1{\displaystyle \frac{d{I}_{\mathrm{L}1}}{dt}}& =V_d\left(d\right)+\left(V_d-{\displaystyle \frac{V_{\mathrm{C}2}}{n}}-V_{\mathrm{C}1}\right)(1-d),\hfill \end{array}$$

(2)

$$\begin{array}{cc}\hfill L_{\mathrm{m}}{\displaystyle \frac{d{I}_{\mathrm{L}}}{dt}}& =-V_{\mathrm{C}1}\left(d\right)+{\displaystyle \frac{V_{\mathrm{C}2}}{n}}(1-d),\hfill \end{array}$$

(3)

$$\begin{array}{cc}\hfill C_1{\displaystyle \frac{d{V}_{\mathrm{C}1}}{dt}}& =I_{\mathrm{Lm}}\left(d\right)+I_{\mathrm{L}1}(1-d),\hfill \end{array}$$

(4)

$$\begin{array}{cc}\hfill C_2{\displaystyle \frac{d{V}_{\mathrm{C}2}}{dt}}& =-{\displaystyle \frac{V_{\mathrm{C}2}+V_d}{R}}\left(d\right)+\left({\displaystyle \frac{I_{\mathrm{L}1}}{n}}-{\displaystyle \frac{I_{\mathrm{Lm}}}{n}}-{\displaystyle \frac{V_{\mathrm{C}2}+V_d}{R}}\right)(1-d).\hfill \end{array}$$

(5)

$$V_{\mathrm{o}}=V_d+V_{\mathrm{C}2}.$$

(6)

The output current ($I_{\mathrm{o}}$) can be calculated based on the output voltage and the load resistance, using $I_{\mathrm{o}}=V_{\mathrm{o}}/R$. It is important to note that the output voltage is obtained by applying Kirchhoff’s Voltage Law (KVL) to the topology shown in Figure 2, as indicated in Equation (6) [18].

3.1. Steady State Analysis

The steady-state values for the inductor currents ($I_{\mathrm{Ls}}$) and capacitor voltages ($V_{\mathrm{Cs}}$) are obtained by setting the derivatives in Equations (2)–(5) to zero. Throughout the remainder of the document, uppercase letters are used to denote steady-state values. The system of equations can be more conveniently expressed in the canonical form of the state-space equations, as shown in (7) and (8), respectively. The state vector $x\left(t\right)$ is defined by the inductor currents and capacitor voltages: $x={\left[I_{\mathrm{L}1};I_{\mathrm{Lm}};V_{\mathrm{C}1};V_{\mathrm{C}2}\right]}^T$. It is worth noting that the input u corresponds to the input source voltage $V_d$, which is assumed to be constant, and the output y corresponds to the output voltage $V_{\mathrm{o}}$.

$$\dot{x}=\mathbf{A}x+\mathbf{B}u,$$

(7)

$$y=\mathbf{C}x+\mathbf{D}u.$$

(8)

Based on (2)–(5), the state–space model can be derived as follows:

$$\mathbf{A}=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{(1-D)}{L_1}}& -{\displaystyle \frac{(1-D)}{n{L}_1}}\\ 0& 0& -{\displaystyle \frac{D}{L_{\mathrm{m}}}}& {\displaystyle \frac{(1-D)}{n{L}_{\mathrm{m}}}}\\ {\displaystyle \frac{(1-D)}{C_1}}& {\displaystyle \frac{D}{C_1}}& 0& 0\\ {\displaystyle \frac{(1-D)}{n{C}_2}}& -{\displaystyle \frac{(1-D)}{n{C}_2}}& 0& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right];\mathbf{B}={\left[\begin{array}{cccc}{\displaystyle \frac{1}{L_1}}& 0& 0& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right]}^T$$

$$\mathbf{C}=\left[\begin{array}{cccc}0& 0& 0& 1\end{array}\right];\mathrm{and}\mathbf{D}=\left[\begin{array}{c}1\end{array}\right].$$

By performing the steady-state analysis and considering Equation (6), the output voltage is given by:

$$V_{\mathrm{o}}=V_d\left({\displaystyle \frac{1}{1-D}}\right).$$

(9)

This expression represents the ideal steady-state voltage conversion ratio of the proposed converter. It is important to clarify that the voltage gain expression in (9) corresponds to the proposed PPP-SEPIC topology. In contrast, the conventional FPP-SEPIC follows the classical SEPIC conversion ratio given by Equation (10):

$${\displaystyle \frac{V_{\mathrm{o}}}{V_d}}={\displaystyle \frac{D}{1-D}}.$$

(10)

The difference arises from the distinct power-processing mechanism adopted in each topology. In the FPP configuration, the entire input power is processed by the switching stage, leading to the classical SEPIC gain. Conversely, in the PPP topology, part of the power is transferred directly through the passive path while only a fraction is processed by the active stage, resulting in an effective gain equivalent to a boost-type relationship. Therefore, although both topologies share similar structural elements, their effective voltage conversion ratios differ due to the distinct distribution of processed power.

3.2. Small-Signal AC Model

The development of the small-signal AC model can be carried out following the traditional approach, which consists of expressing the state and input variables as the sum of their DC components and small AC perturbations. This approach allows for the analysis of the system’s behavior under small disturbances and can be expressed as shown in Equation (11).

$$\left\{\begin{array}{cc}{i}_{\mathrm{L}1}=I_{\mathrm{L}1}+{\tilde{i}}_{\mathrm{L}1},& i_{\mathrm{Lm}}=I_{\mathrm{Lm}}+{\tilde{i}}_{\mathrm{Lm}},\\ v_{\mathrm{C}1}=V_{\mathrm{C}1}+{\tilde{v}}_{\mathrm{C}1},& v_{\mathrm{C}2}=V_{\mathrm{C}2}+{\tilde{v}}_{\mathrm{C}2},\\ v_d=V_d+{\tilde{v}}_d,& d=D+{\tilde{d}}_{.}\end{array}\right\}$$

(11)

By substituting the expressions from Equation (11) for each of the variables, the set of Equations (2)–(5) is transformed into equations containing both DC and AC components, resulting in the following set of equations:

$$\begin{array}{cc}\hfill L_1{\displaystyle \frac{d{\tilde{i}}_{\mathrm{L}1}}{dt}}& ={\tilde{v}}_{\mathrm{d}}-\left(1-D\right){\tilde{v}}_{\mathrm{C}1}-{\displaystyle \frac{\left(1-D\right)}{n}}{\tilde{v}}_{\mathrm{C}2}+\left(V_{\mathrm{C}1}+{\displaystyle \frac{V_{\mathrm{C}2}}{n}}\right)\tilde{d},\hfill \end{array}$$

(12)

$$\begin{array}{cc}\hfill L_m{\displaystyle \frac{d{\tilde{i}}_{\mathrm{Lm}}}{dt}}& =-D{\tilde{v}}_{\mathrm{C}1}+{\displaystyle \frac{\left(1-D\right)}{n}}{\tilde{v}}_{\mathrm{C}2}-\left(V_{\mathrm{C}1}+{\displaystyle \frac{V_{\mathrm{C}2}}{n}}\right)\tilde{d},\hfill \end{array}$$

(13)

$$\begin{array}{cc}\hfill C_1{\displaystyle \frac{d{\tilde{v}}_{\mathrm{C}1}}{dt}}& =\left(1-D\right){\tilde{i}}_{\mathrm{L}1}+D{\tilde{i}}_{\mathrm{Lm}}+\left(I_{\mathrm{Lm}}-I_{\mathrm{L}1}\right)\tilde{d},\hfill \end{array}$$

(14)

$$\begin{array}{cc}\hfill C_2{\displaystyle \frac{d{\tilde{v}}_{\mathrm{C}2}}{dt}}& ={\displaystyle \frac{\left(1-D\right)}{n}}\left({\tilde{i}}_{\mathrm{L}1}-{\tilde{i}}_{\mathrm{Lm}}\right)-{\displaystyle \frac{{\tilde{v}}_{\mathrm{C}2}}{R}}-{\displaystyle \frac{{\tilde{v}}_d}{R}}-{\displaystyle \frac{\left(I_{\mathrm{L}1}-I_{\mathrm{Lm}}\right)}{n}}\tilde{d}.\hfill \end{array}$$

(15)

The set of equations from (12) to (15) constitutes a linear model that can also be expressed in the canonical state-space form, similarly to Equations (7) and (8). In this case, the state vector is defined as $x={\left[{\tilde{i}}_{\mathrm{L}1};{\tilde{i}}_{\mathrm{Lm}};{\tilde{v}}_{\mathrm{C}1};{\tilde{v}}_{\mathrm{C}2}\right]}^T$, the input vector as $\mathbf{u}=\left[{\tilde{v}}_{\mathrm{d}}\right]$, and:

$$\mathbf{A}=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{(1-D)}{L_1}}& -{\displaystyle \frac{(1-D)}{n{L}_1}}\\ 0& 0& -{\displaystyle \frac{D}{L_{\mathrm{m}}}}& {\displaystyle \frac{(1-D)}{n{L}_{\mathrm{m}}}}\\ {\displaystyle \frac{(1-D)}{C_1}}& {\displaystyle \frac{D}{C_1}}& 0& 0\\ {\displaystyle \frac{(1-D)}{n{C}_2}}& -{\displaystyle \frac{(1-D)}{n{C}_2}}& 0& -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right];$$

$$\mathbf{B}=\left[\begin{array}{c}{\displaystyle \frac{1}{L_1}}\\ 0\\ 0\\ -{\displaystyle \frac{1}{R{C}_2}}\end{array}\right];\mathrm{and}\mathbf{D}=\left[\begin{array}{c}1\end{array}\right].$$

4. Loss Modeling

The efficiency of the power converter ($\eta$) can be readily computed as:

$$\eta ={\displaystyle \frac{P_{\mathrm{o}}}{P_{\mathrm{o}}+P_{\mathrm{Loss}}}}$$

(16)

where $P_{\mathrm{o}}$ and $P_{\mathrm{Loss}}$ are the power consumed by the load resistor and $P_{\mathrm{Loss}}$ the losses due to the inductors ($P_{\mathrm{Ls}}$), the MOSFET ($P_{\mathrm{S}}$), and the diode ($P_{\mathrm{D}}$):

Therefore, they are calculated as:

$$\begin{array}{cc}\hfill P_{\mathrm{Loss}}& =P_{\mathrm{Ls}}+P_{\mathrm{S}}+P_{\mathrm{D}},\hfill \end{array}$$

(17)

$$\begin{array}{cc}\hfill P_{\mathrm{Ls}}& =r_{\mathrm{Lj}}·I_{\mathrm{Lj}\left(\mathrm{RMS}\right)}^2,\hfill \end{array}$$

(18)

$$\begin{array}{cc}\hfill P_{\mathrm{S}}& =r_{\mathrm{On}}·I_{\mathrm{S}\left(\mathrm{RMS}\right)}^2+(E_{\mathrm{Son}}+E_{\mathrm{Soff}})·F_{\mathrm{s}},\hfill \end{array}$$

(19)

$$\begin{array}{cc}\hfill P_{\mathrm{D}}& =I_{\mathrm{D}}·V_{\mathrm{D}}.\hfill \end{array}$$

(20)

the values for inductors are $\mathrm{j}=1,\mathrm{m}$.

4.1. Losses on Inductors

The losses on inductors $L_1$ and $L_{\mathrm{m}}$ can be calculated using the equivalent series resistance (ESR) and the RMS value of the current $I_{\mathrm{Lj}}\left(\mathrm{RMS}\right)$ through them. Since the mentioned inductors carry a triangular-shaped waveform current, the RMS can be obtained with:

$$I_{\mathrm{Lj}\left(\mathrm{RMS}\right)}=\sqrt{I_L^2+{\displaystyle \frac{\Delta i_L^2}{12}}}.$$

(21)

4.2. Losses on the MOSFET

The losses in the MOSFET S consist of conduction losses and switching losses. The conduction losses depend on the on-state resistance $r_{\mathrm{on}}$ and the RMS value of the current through the switch $I_{\mathrm{S}}\left(\mathrm{RMS}\right)$, whereas the switching losses depend on the turn-on and turn-off energy per switching event, $E_{\mathrm{Son}}$ and $E_{\mathrm{Soff}}$ and the switching frequency $f_{\mathrm{s}}$, as given in (19). The first term represents the ohmic losses, while the second term accounts for the energy dissipated during each switching transition. The conduction losses depend on the on-state resistance $r_{\mathrm{on}}$ and the RMS value of the current through the switch $I_{\mathrm{S}}\left(\mathrm{RMS}\right)$, whereas the switching losses depend on the turn-on and turn-off energy per switching event, $E_{\mathrm{Son}}$ and $E_{\mathrm{Soff}}$, respectively, together with the switching frequency $f_{\mathrm{s}}$, as seen in (22) and (22).

$$E_{\mathrm{Son}}=\frac{1}{2}{V}_{\mathrm{S}}{I}_{\mathrm{S}}{t}_{\mathrm{on}},$$

(22)

$$E_{\mathrm{Soff}}=\frac{1}{2}{V}_{\mathrm{S}}{I}_{\mathrm{S}}{t}_{\mathrm{off}}.$$

(23)

Similar to (21), the RSM is given by:

$$I_{\mathrm{S}\left(\mathrm{RMS}\right)}=\sqrt{I_{\mathrm{S}}^2+{\displaystyle \frac{\Delta i_{\mathrm{S}}^2}{12}}}.$$

(24)

where $I_{\mathrm{S}}$ is the average value of the current through the MOSFET, and the term $\Delta i_{\mathrm{S}}$ is the ripple during the on-stage. It is evident that $\Delta i_{\mathrm{S}}$ can be obtained during the on-stage: the MOSFET conducts the inductor current $i_{\mathrm{L}1}$ and $i_{\mathrm{Lm}}$, as (4) shows. Alternatively, $\Delta i_{\mathrm{S}}$ can be calculated with:

$$\begin{array}{cc}\hfill \Delta i_{\mathrm{S}}& =I_{\mathrm{S}\left(\mathrm{Max}\right)}-I_{\mathrm{S}\left(\min \right)},\hfill \end{array}$$

(25)

$$\begin{array}{cc}\hfill I_{\mathrm{S}\left(\mathrm{Max}\right)}& =(I_{\mathrm{L}}+I_{\mathrm{Lm}})+0.5·(\Delta i_{\mathrm{L}}+\Delta i_{\mathrm{Lm}}),\hfill \end{array}$$

(26)

$$\begin{array}{cc}\hfill I_{\mathrm{S}\left(\mathrm{Max}\right)}& =(I_{\mathrm{L}}+I_{\mathrm{Lm}})-0.5·(\Delta i_{\mathrm{L}}+\Delta i_{\mathrm{Lm}}).\hfill \end{array}$$

(27)

4.3. Losses on the Diode

The losses in the diode D are mainly conduction losses, since the device does not experience active switching transitions as the MOSFET does. These conduction losses depend on the average current flowing through the diode $I_{\mathrm{D}}$ and its forward voltage drop $V_{\mathrm{D}}$. Thus, the total losses on the diode can be expressed as:

$$P_{\mathrm{D}}=I_{\mathrm{D}}{V}_{\mathrm{D}}.$$

(28)

In this case, the average values for the current and voltage of the diode are:

$$\begin{array}{cc}\hfill I_{\mathrm{D}}& ={\displaystyle \frac{V_{\mathrm{o}}}{R}},\hfill \end{array}$$

(29)

$$\begin{array}{cc}\hfill V_{\mathrm{D}}& =-V_{\mathrm{C}2}.\hfill \end{array}$$

(30)

The negative sign in (30) arises from the chosen voltage reference for $V_{\mathrm{C}}2$, which is defined with opposite polarity to the conduction direction of the diode.

4.4. Losses on the Converter

The efficiency curves in Figure 6 illustrate the behavior of the converter for different transformer turns ratios n, while maintaining a fixed duty cycle of 35%. For each operating point, the total losses are quantified using (17). Because the turns ratio directly affects the current distribution within the coupled inductors and the power stage, both the RMS current and the corresponding ripple change as n varies. The highest efficiency is presented in the range of approximately 20–80 W.

The efficiency curves in Figure 7 illustrate the behavior of the converter for different values of the duty cycle, while keeping the transformer turns ratio fixed. For each operating point, the total losses are quantified using (17). As the duty cycle changes, the average and RMS currents through the inductors and semiconductor devices are modified, which in turn affects the conduction and switching losses. Higher duty cycles tend to increase the inductor current and reduce the voltage conversion stress.

At low output power, the differences among duty cycles are more pronounced due to the dominance of conduction losses. As the output power increases, efficiency decreases for all cases because inductor ESR losses and semiconductor switching losses grow with current.

5. Results and Discussion

Table 2. Comparison between the mathematical model and simulation results.

Resistance	${\mathit{V}}_{\mathbf{C}1}$	${\mathit{V}}_{\mathbf{C}2}$	${\mathit{I}}_{\mathbf{L}1}$	${\mathit{I}}_{\mathbf{Lm}}$
$5\mathrm{\Omega }$ (Model)	18 V	27 V	13.5 A	9 A
$5\mathrm{\Omega }$ (Simulation)	18 V	26.4 V	13.5 A	9 A
$10\mathrm{\Omega }$ (Model)	18 V	27 V	6.7 A	4.5 A
$10\mathrm{\Omega }$ (Simulation)	18 V	26.4 V	6.6 A	4.4 A
$15\mathrm{\Omega }$ (Model)	18 V	27 V	4.5 A	3 A
$15\mathrm{\Omega }$ (Simulation)	18 V	26.4 V	4.4 A	2.9 A
$20\mathrm{\Omega }$ (Model)	18 V	27 V	3.37 A	2.2 A
$20\mathrm{\Omega }$ (Simulation)	18 V	26.4 V	3.3 A	2.1 A

presents a detailed comparison between the results obtained from the averaged mathematical model and those derived from numerical simulation under different resistive load conditions. The validation is performed at nominal design parameters ($V_d=18$ V) using a purely resistive load to ensure controlled operating conditions.

For this analysis, the input source is intentionally considered ideal in the analytical model in order to rigorously verify the accuracy of the theoretical derivation. In contrast, parasitic elements are explicitly included in the simulation model to more realistically represent practical implementation effects. Despite these modeling differences, the results exhibit a high degree of correlation between both approaches, with only minor deviations observed in the predicted voltages and currents.

These findings confirm the validity of the proposed averaged model and demonstrate its capability to accurately capture the steady-state behavior of the converter under nominal operating conditions.

In the original efficiency evaluation, a resistive load model was employed to represent the steady-state operating condition of the DC output stage. While a purely resistive load is commonly used for steady-state efficiency characterization, an additional simulation including an inductive component (R = 5 $\mathrm{\Omega }$ in series with L = 2 mH) has now been incorporated to address the reviewer’s concern.

The updated results, presented in Figure 8, demonstrate that the inclusion of the inductive component does not significantly modify the steady-state efficiency behavior across the evaluated duty-cycle range. The observed deviation remains negligible, confirming that resistive-load-based efficiency analysis provides an accurate representation of steady-state performance for the proposed PPP-SEPIC converter. The maximum steady-state efficiency deviation between the resistive and RL cases remained below 1% within the nominal operating range.

As expected, inductive effects primarily influence transient response, while steady-state power conversion efficiency is predominantly governed by RMS currents and conduction/switching losses as derived in Section 4.

To further validate the proposed topology, a set of simulations were performed using MATLAB/Simulink R2018b. These simulations enable a direct and quantitative comparison between the FPP-SEPIC topology and the proposed PPP-SEPIC configuration. For consistency and fairness, both models were implemented using identical passive and active components, as well as the same photovoltaic panel operating under identical nominal conditions.

5.1. Switching Frequency Selection

The switching frequency of 70 kHz was selected as a practical design compromise between conversion efficiency and passive component size. Increasing the switching frequency reduces the required inductance and capacitance values, thereby enabling the use of smaller magnetic and filtering components. However, switching losses increase proportionally with frequency, since the energy dissipated during each transition accumulates with the switching rate. The switching loss can be reasonably approximated as:

$$P_{\mathrm{sw}}\approx {\displaystyle \frac{1}{2}}{V}_{\mathrm{DS}}{I}_{\mathrm{D}}(t_r+t_f)f_s$$

(31)

Consequently, higher switching frequencies increase switching losses and may therefore reduce the overall converter efficiency. At the 100 W power level considered in this work, switching frequencies in the range of 50–100 kHz are widely adopted in silicon-based DC–DC converters to achieve a balanced trade-off between magnetic component size and switching losses. Therefore, the selected value of 70 kHz represents a technically justified operating point.

5.2. Simulation Results and Performance Comparison

A silicon-based MOSFET device was consistently considered in both the simulation and the experimental validation stages. Conduction losses were estimated based on the parameter $R_{\mathrm{DS}\left(\mathrm{on}\right)}$, while switching losses were modeled as frequency-dependent according to the transition times and the corresponding operating conditions. Importantly, the same switching device model was employed for both PPP and FPP configurations to ensure a consistent comparison.

Table 3. Comprehensive comparison between FPP-SEPIC and PPP-SEPIC under identical PV operating conditions ($V_{\mathrm{pv}}\approx 17\mathrm{V}$, $P_{\mathrm{in}}\approx 100\mathrm{W}$, $f_{\mathrm{s}}=70\mathrm{kHz}$). Metrics measured over the last 200 switching cycles.

	FPP-SEPIC	PPP-SEPIC
Power processing	Full processing	Partial processing
Input voltage	17 V	17 V
Output voltage	21.7 V	22.7 V
Input power	100 W	100 W
Output power	87 W	95 W
Switching frequency	70 kHz	70 kHz
Ideal voltage gain	${\displaystyle \frac{D}{1-D}}$	${\displaystyle \frac{1}{1-D}}$
Duty cycle (D)	0.60	0.30
Efficiency ($\eta$)	87%	95%
$I_{\mathrm{SW},\mathrm{rms}}$ (A)	6.8149	3.0344
$I_{\mathrm{L}1,\mathrm{rms}}$ (A)	4.6015	4.9254
$I_{\mathrm{L}2,\mathrm{rms}}$ (A)	6.2141	1.4457
$I_{\mathrm{D},\mathrm{rms}}$ (A)	6.2141	4.9254
$\Delta V_{\mathrm{o},pp}$ (V)	0.0229	0.0211
THD$V_{\mathrm{o}}$ (%)	2.227	1.278
THD$I_{\mathrm{o}}$ (%)	2.227	1.278

presents a quantitative comparison between the proposed PPP-SEPIC and the conventional FPP-SEPIC topologies. Both converters were evaluated under identical photovoltaic operating conditions ($V_{\mathrm{pv}}\approx 17\mathrm{V}$, $P_{\mathrm{in}}\approx 100\mathrm{W}$, $f_{\mathrm{s}}=70\mathrm{kHz}$) to ensure a fair and controlled assessment.

Under these conditions, the PPP configuration achieves an efficiency of 95%, compared to 87% for the FPP topology. This corresponds to total conduction and switching losses of approximately 5 W and 13 W, respectively. Furthermore, the PPP approach reduces RMS current stress on the MOSFET (−55.5%) and on the second inductor (−76.7%), while maintaining a comparable output voltage ripple. Additionally, the PPP topology exhibits lower harmonic distortion, with THD($V_{\mathrm{o}}$) = 1.278% compared to 2.227% for the FPP configuration, corresponding to a 42.6% reduction. Since a purely resistive load was considered, THD($I_{\mathrm{o}}$) matches THD($V_{\mathrm{o}}$). This confirms that the PPP configuration not only reduces RMS current stress and power losses but also improves the spectral quality of the output voltage.

It is important to note that the voltage gain expressions correspond to ideal steady-state relationships. The simulated output voltages are slightly lower due to semiconductor voltage drops, winding resistances, and parasitic losses explicitly included in the model.

For the simulation study, the Global Solar Energy FG-2BTM-100 photovoltaic module was considered as the input source, providing a maximum output power of 100 W under nominal conditions. In the PPP-SEPIC configuration, maximum power transfer is achieved at a duty cycle of approximately 30%, whereas in the conventional FPP-SEPIC converter, the maximum power point occurs near a duty cycle of 60%.

The higher efficiency observed in the PPP-SEPIC topology can be primarily attributed to its operation at a significantly lower duty cycle [19]. Since the MOSFET conduction loss is proportional to the square of its RMS current, and the RMS current increases approximately with the square root of the duty ratio, reducing the duty cycle from about 0.60 to 0.30 nearly halves the conduction loss component, assuming comparable operating conditions.

Moreover, switching losses are inherently reduced in the PPP configuration because only a fraction of the total power flows through the active switching stage. This effectively lowers the current during turn-on and turn-off transitions, thereby decreasing the energy dissipated per switching event and improving overall efficiency. In the presented simulations, semiconductor losses were explicitly included in the device models. MOSFET conduction losses were calculated as $I_{\mathrm{RMS}}^2{R}_{\mathrm{DS}\left(\mathrm{on}\right)}$, while the diode model incorporated both forward voltage drop and internal series resistance. Switching losses were analytically estimated as frequency-dependent based on the energy dissipated per transition. The switching transition times were obtained from the manufacturer’s datasheet of the selected MOSFET device under nominal operating conditions. Therefore, the reported efficiency values account for both conduction and switching losses in the PPP and FPP configurations.

Full parameter values are comprehensively listed in Appendix A (

Table A1. Parameters.

Notation	Parameter	Value
$V_d$	Input voltage	18 V
$V_{\mathrm{o}}$	Output voltage	25 V
$f_{\mathrm{s}}$	Switching frequency	70 kHz
$P_{\mathrm{in}}$	Input power	100 W
$C_1=C_2$	Capacitors	100 $\mathsf{\mu }$F
$L_1$	Inductor 1	1.27 mH
$L_m$	Inductor 2	3.44 mH
$Q_1$	N-channel MOSFET (120 V, low $R_{\mathrm{DS}\left(\mathrm{on}\right)}$)	TK56A12N1
$D_1$	Ultrafast recovery diode (100 V, 20 A)	TS20U10CG

). The same set of electrical and magnetic parameters was consistently used for both topologies to ensure a fair and technically consistent efficiency comparison.

The simulation results presented in Figure 9 depict the input power (blue curve) and the power delivered to the load resistor (red curve) as a function of the duty cycle. The plot systematically illustrates the power behavior over the entire duty-cycle operating range. It can be observed that the maximum power transfer occurs at a duty cycle of approximately 30%, corresponding to the optimal operating condition of the PPP-SEPIC configuration.

Figure 10 shows the simulated efficiency of the proposed PPP-SEPIC converter as a function of the duty cycle. The efficiency curve was obtained from the ratio between the instantaneous output and input powers, averaged over several switching periods while sweeping the duty cycle from 0 to 1.

At low duty-cycle values, a transient response is initially observed due to the energy stored in the coupling capacitors and the temporary imbalance between the current paths. Once steady-state operation is established ($D>0.3$), the converter consistently maintains an efficiency close to 95%, thereby confirming the effective energy transfer through the partial power processing branch.

For higher duty-cycle values ($D>0.7$), the efficiency gradually decreases as conduction losses increase in the main switching device and associated passive components. This behavior is consistent with the quadratic dependence of conduction losses on RMS current, which rises with increasing duty ratio.

Overall, these results validate the expected operational principle of the PPP-SEPIC topology, in which only a controlled fraction of the total input power flows through the active processing branch. This selective power processing mechanism effectively reduces total power losses when compared to the conventional FPP-SEPIC configuration.

Figure 11 presents the corresponding simulation results for the conventional Full Power Processing (FPP) SEPIC topology. The figure illustrates the variation of input and output power over the entire duty-cycle range. It can be clearly observed that the maximum power transfer occurs at a duty cycle of approximately 60%, which corresponds to the nominal operating region of the FPP configuration.

Figure 12 illustrates the simulated efficiency of the FPP-SEPIC converter as a function of the duty cycle. A relatively high-efficiency plateau is observed for duty-cycle values approximately between 0.30 and 0.60, with the highest efficiency occurring slightly above the nominal maximum power transfer point (D = 0.60), where conduction and switching losses are reasonably balanced.

As the duty cycle increases beyond 0.7, an efficiency degradation occurs due to the rapid increase in inductor RMS currents, elevated switch conduction losses, and higher diode losses associated with the inherent voltage-gain characteristic of the SEPIC topology. In this region, the converter operates under extreme step-up conditions, which lie outside the recommended design and optimal operating range. It is important to note that the maximum efficiency point does not necessarily coincide with the maximum power transfer point shown in Figure 12, since efficiency depends on the ratio between delivered power and total losses.

Therefore, the observed efficiency reduction at high duty-cycle values does not represent normal operating behavior, but rather reflects the intrinsic physical limitations of the FPP-SEPIC topology under excessive gain requirements.

Overall, the results demonstrate that the conventional full-power SEPIC converter inherently experiences higher energy losses, since the entire transferred power must be processed through the active switching device and associated passive components. This complete power processing mechanism inevitably increases conduction and switching losses, particularly under high-duty-cycle operating conditions.

In contrast, the proposed PPP-SEPIC architecture processes only a controlled fraction of the total input power, thereby reducing the current stress in the switching stage and associated magnetic elements. As a result, the converter consistently achieves higher and more stable efficiency levels—typically exceeding 90% across a wide portion of the operating range.

This comparative analysis highlights the effectiveness of the Partial Power Processing approach in minimizing conversion losses and enhancing the overall energy performance of photovoltaic power conversion systems.

5.3. Thermal, Reliability, and Scalability Considerations

Although a dedicated thermal characterization, such as infrared thermography, was not explicitly conducted in this study, the thermal performance can be reasonably inferred from the reduced processed power reported in Table 3. Since the PPP stage processes only a controlled fraction of the total input power, both the RMS and average currents in the semiconductor devices are inherently reduced compared to a conventional FPP approach.

Given that conduction losses scale approximately with $I^{2}R$, a reduction in current stress directly implies lower power dissipation. Consequently, a lower junction temperature rise can be expected under comparable operating conditions. This reduced temperature rise is strongly associated with decreased thermal stress and may therefore contribute positively to long-term reliability.

Regarding scalability, the PPP approach is particularly attractive for photovoltaic applications in which the input and output voltages are relatively close, since the fraction of processed power remains inherently limited. This characteristic helps preserve the efficiency advantages as power levels increase. Future work will include comprehensive experimental thermal validation and long-term operation testing in order to quantitatively assess lifetime-related performance metrics.

5.4. Advantages, Limitations, and Future Work

The proposed PPP-SEPIC converter offers several relevant advantages: (i) a substantially reduced processed power fraction compared to conventional FPP structures, (ii) experimentally validated efficiency improvement and measurable power loss reduction, and (iii) potentially lower semiconductor stress due to reduced device RMS currents (Table 3).

The main limitations are primarily associated with: (i) the dependency on the photovoltaic operating point and the required voltage conversion ratio, (ii) design constraints in magnetic components, such as the transformer and inductors, and (iii) the need for carefully implemented control strategies in PPP-based structures.

Future work will systematically focus on integrating advanced MPPT control strategies, experimentally validating performance at higher power levels, conducting infrared thermal characterization to quantify junction temperature trends, and performing long-term operational testing in order to evaluate reliability under realistic photovoltaic operating conditions.

6. Experimental Results

In order to validate the theoretical proposal, a laboratory-scale prototype was built and is depicted in Figure 13.

In order to provide a broader experimental validation under different loading conditions, additional tests were performed at multiple operating points. For each test, the input and output voltages and currents were measured using calibrated instruments, and the efficiency was calculated as $\eta =P_{\mathrm{o}}/P_{\mathrm{in}}$, where $P_{\mathrm{in}}=V_{\mathrm{in}}{I}_{\mathrm{in}}$ and $P_{\mathrm{o}}=V_{\mathrm{o}}{I}_{\mathrm{o}}$. The results are summarized in

Table 4. Experimental results for the PPP-SEPIC prototype under different input voltage levels and load conditions.

Test	R ($\mathbf{\Omega }$)	${\mathit{V}}_{\mathbf{in}}$ (V)	${\mathit{I}}_{\mathbf{in}}$ (A)	${\mathit{P}}_{\mathbf{in}}$ (W)	${\mathit{V}}_{\mathbf{o}}$ (V)	${\mathit{P}}_{\mathbf{o}}$ (W)	$\mathit{\eta }$ (%)
1	100	15	0.40	6.00	23.91	5.71	95.2
2	100	17	0.45	7.65	27.10	7.34	96.0
3	100	19	0.51	9.69	30.31	9.19	94.8
4	100	21	0.56	11.76	33.48	11.21	95.3
5	100	23	0.62	14.26	36.66	13.44	94.3
6	100	25	0.69	17.25	39.77	15.81	91.6
7	50	17	0.85	14.50	26.00	13.52	93.0
8	30	17	1.35	22.95	24.80	19.91	87.0
9	30	19	1.50	28.50	27.00	23.49	82.0

.

The experimental results presented in Table 4 provide a comprehensive validation of the PPP-SEPIC prototype under different input voltage levels and load conditions.

For the 100 load (Tests 1–6), the converter maintains a high efficiency across the evaluated input voltage range (15–25 V). The maximum measured efficiency (96.0%) occurs at $V_{\mathrm{in}}$ = 17 V (Test 2), while efficiency gradually decreases to 91.6% at $V_{\mathrm{in}}$ = 25 V (Test 6). This slight reduction at higher input voltage levels is mainly attributed to increased conduction losses, magnetic core losses, and parasitic resistive effects, which become more significant as the processed power increases.

To further evaluate the converter under higher loading conditions, additional tests were performed with reduced load resistances. For R = 50 $\mathrm{\Omega }$ (Test 7), operating at $V_{\mathrm{in}}$ = 17 V and $P_{\mathrm{o}}$ = 13.5 W, the measured efficiency was 93.0%. When the load was further reduced to 30 $\mathrm{\Omega }$ (Tests 8 and 9), the output power increased to approximately 19.9 W and 23.5 W, and the efficiency decreased to 87.0% and 82.0%, respectively.

The observed efficiency drop at higher output power levels is primarily associated with increased RMS currents in the semiconductor devices and magnetic elements. Since conduction losses scale proportionally with I²R, the higher current stress under low-resistance loading conditions results in increased total power dissipation. Additionally, magnetic losses and non-ideal layout parasitics inherent to the laboratory-scale prototype contribute to the efficiency reduction at elevated power levels.

It is important to emphasize that even under the highest tested power condition (Test 9), the converter maintains stable operation in continuous conduction mode (CCM), as verified experimentally.

The experimental validation of the proposed PPP-SEPIC converter was performed using a laboratory-scale prototype, as illustrated in Figure 13. The prototype was implemented to experimentally verify the analytical predictions and simulation results under controlled conditions.

Representative steady-state waveforms corresponding to Test 7 ($V_{\mathrm{in}}$ = 17 V, R = 50 $\mathrm{\Omega }$, $P_{\mathrm{o}}$ = 13.5 W) are shown in Figure 14. Figure 14a presents the overall steady-state behavior (10 µs/div), confirming stable voltage regulation and controlled inductor current ripple. Figure 14b provides a zoomed view of the switching transition (500 ns/div), clearly illustrating the switching dynamics and current ripple behavior.

The zoomed waveform confirms the expected switching operation at approximately 70 kHz and demonstrates proper energy transfer between the direct and processed paths, validating the partial power processing principle under experimental conditions.

Overall, the experimental results validate the theoretical analysis and simulation results, confirming that the PPP-SEPIC topology achieves high efficiency under light and medium load conditions while maintaining stable operation under increased power levels.

7. Conclusions

This work has presented the complete analytical modeling, simulation, and experimental validation of a PPP-SEPIC converter for photovoltaic applications. The proposed topology was mathematically characterized using steady-state and small-signal models, providing a rigorous theoretical framework for performance evaluation.

Comparative results demonstrate that, under identical photovoltaic operating conditions, the PPP configuration significantly improves energy conversion efficiency compared to the conventional FPP-SEPIC topology. Simulation results indicate efficiencies up to 95%, while experimental validation confirms efficiencies reaching 93% under light and medium load conditions. The efficiency improvement is primarily attributed to the reduced duty-cycle operation and the partial processing of input power, which lowers RMS current stress and semiconductor losses.

Experimental tests conducted under different loading conditions further confirm stable steady-state operation and continuous conduction mode behavior. The agreement between analytical, simulation, and experimental results validates the correctness of the proposed modeling approach.

Overall, the PPP-SEPIC topology represents an effective strategy for enhancing efficiency and reducing device stress in photovoltaic DC–DC conversion systems. Future research will focus on thermal characterization, high-power scalability assessment, and advanced MPPT control integration to further evaluate long-term reliability and system-level performance.