The voltage amplitude and frequency of the charging strategy in this paper follow those from the theoretical model in [
11]. The waveform is shown in
Figure 1a. We have already verified and demonstrated that this composite sinusoidal waveform is effective in prolonging the 18650 lithium-ion battery life [
12]. The waveform has voltage level of 3.6 V. The upper cycle and lower cycle are 0.7 V and 0.2 V, respectively. The frequency is 1 kHz. As the cell voltage reaches the full voltage, the lower cycle of the waveform can discharge the battery. The circuit we developed can generate such a waveform.
Figure 1b shows the roadmap that the circuit comprises three parts. The first part is a pulse width modulation (PWM) for generating a digital signal of the composite sinusoidal waveform. The second part is to amplify the digital signal to the power level. The third part is a low-pass filter circuit that converts the digital signal into a voltage waveform for effective battery charging. In addition, we reserved a signal feedback function in the program [
17,
18], such that the circuit can provide the appropriate charging waveform in real time by incorporating databases and artificial intelligence (AI) decisions in the future. The microchip dsPIC30f4011 digital signal processor (DSP; Microchip Technology Inc., Chandler, AZ, USA) [
19] with high computing speed and low delay time was selected as the important component of composite waveform generation to allow the frequency of the output waveform to be above 1 kHz to avoid the impact of resolution on the waveform, and to reduce slowing down of Microcontroller Unit (MCU) processing by analog-to-digital reading. The charging circuit design adopts the buck circuit architecture, with TLP250 selected as the inner gate driver. In addition to driving MOSFET, it also isolates the signal from the power level. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) adopts the P-type IRF9540N and N-type IRF3705. Subsequently, restoration of the composite waveform is achieved by an LC low-pass filter.
2.1. Direct Digital Synthesis (DDS) and Buck Converter
In the first part of signal generation, the structure of DDS comprises the phase accumulator, waveform memory, analog-to-digital converter, and low-pass filter, as shown in
Figure 2a. The phase accumulator, which is the most important in the DDS module, comprises the N-bit adder and N-bit accumulator register. The principle of its operation is as follows. With an incoming reference frequency
, the accumulator accumulates the frequency control
FW with the output value of the register (
), the result of which is then input to the register. The accumulator register feeds the data generated in the previous reference clock into the accumulator by way of feedback. Under the action of the clock, the frequency control can be constantly accumulated. In the meantime, by using the data output from the phase accumulator as the address, the amplitude table corresponding to the said address is found in the waveform memory. The transformation from phase to amplitude is thus accomplished. The equation for computing the output frequency is as follows:
The equation for computing the resolution of output signal frequency (
) is as follows:
A stable average output voltage is generated as the buck converter adjusts the duty cycle and switches the ON/OFF status of the circuit, which passes through an LC filter, as shown in
Figure 2b. The working timing of the converter is shown in
Figure 2c. When the MOSFET is ON in the working time, the current is transmitted to the load end through the inductor, which also accumulates energy. Meanwhile, the diode state is OFF. When the MOSFET is OFF, the energy accumulated in the inductor is supplied to the load end as a current flow through the diode [
20,
21,
22,
23].
Based on the voltage and current stress analysis, the maximum current
through the inductor
L is that given by Equation (3), where
is the load resistance,
is filter inductance,
is the load current,
is the duty cycle, and
is the switching period.
The rated voltage
of the switch MOSFET and flyback diode
is given by Equation (4), where
is the rated voltage at the switch MOSFET and
is the rated voltage at the flyback diode.
The rated current
of the switch MOSFET and flyback diode
is given by
The filter inductance
is computed by Equation (6). When
,
L is at its maximum
Computing the filter capacitor, where
is the switch frequency, the charge of capacitor
C in one switching cycle is
The output ripple voltage
is evaluated by
The filter capacitance
C is
2.2. Waveform Generation
To generate a composite waveform that is effective for capacity recovery, dsPIC30f4011 chips are first used in conjunction with DDS. Interpolation is used to convert the composite waveform into program codes. The designed LC low-pass filter is used to verify the waveform. The cycle of correction, fine tuning, and verification is launched when there is discrepancy between the generated waveform and the target waveform. The composite waveform development process is completed only when the generated waveform agrees with the target waveform.
Primary Master Time Base Period Register (PTPER) is defined as the primary parameter for the development of composite waveform. Its purpose is to set the upper limit of the frequency and resolution of the composite waveform. The time-base module required to generate a PWM signal in dsPIC30f4011 chip can be categorized into four working modes: free running mode, single event mode, continuous up/down counting mode, and continuous up/down mode with interrupts for double-updates. In this study, all PWM outputs adopt the continuous up/down counting mode. To strike a balance between frequency and resolution, this study takes a prioritized resolution directive and sets the maximum output voltage (Vmax) of the chip at 5 V and the register precision (Vacc) at 100 mV per grid. Based on the calculation via the resolution equation, the resolution of the register at 100 mV per grid is obtained when PTPER is 25. In addition to meeting the requirements of the composite waveform, it also ensures high PWM output frequency, such that the composite waveform output can be above 1 kHz.
The conversion between the composite waveform generated and the registered value in the program code is achieved by computing the PWM duty cycle of 0–100% in the established composite waveform via Equation (11), then comparing with the values read from
PDCx register.
PDCx is the ratio of duty cycle of the PWM output. PTPER << 1 represents moving the binary value one bit to the left, corresponding to a multiplication by two in the decimal system.
Through the conversion of values in the register, the corresponding values read from the PDCx register can be known for every width of PWM duty cycle. The following paragraphs explain how the conversion is achieved from analog voltage signals to digital PWM duty cycle values. Adjustment is made to the voltage level, the first parameter of the voltage waveform. Then, the second and third parameters are adjusted, which are the upper/lower half-cycle amplitudes and waveform frequency, respectively. Finally, the three parameters are fine-tuned into a one-line program instruction to simplify program complexity and to improve readability. All the above output signals are the PWM value, which are difficult to read and to verify whether they are consistent with the target. Therefore, the low-pass filter is designed and implemented to verify whether the various parameter settings meet the target value.
To verify conformance of the PWM signal to the target voltage waveform, it is necessary to restore the PWM digital signal to a continuous analog waveform signal through the low-pass filter to improve the visibility [
24]. The lower filter circuit adopts an LC low-pass filter with wide applicability and good stability [
25,
26]. The frequency of the target composite waveform is the cut-off frequency of the low-pass filter that is set to about 1 kHz. The designing method is such that common L and C levels are substituted into the lower cut-off frequency to carry out theoretical calculations. The optimal values for filter L and C are found through repeatedly applied verifications. To verify the design of the PWM low-pass filter circuit, an exemplary sinusoidal PWM value is first selected as the basis for LC adjustment of the filter. It is found through verification that the best filter is one with an L of 12.5 mH and C of 1 μF. The cut-off frequency of the low-pass filter is reversely deduced via the equation to be 1.42 kHz, which is close to the original ideal value of 1 kHz.
Voltage values are converted to code parameters by taking advantage of the characteristic of linear interpolation, i.e., any two adjacent tabular points can be connected by a straight line. All the values of a therein can be correlated to a linear function
b(
x). Taking advantage of the feature that a straight line has a constant slope, the following relation can be expressed as Equation (12) [
27,
28]:
The target of this study is defined in such a manner that the upper and lower half-cycles are separate, thus, a1 and b1 in the equation can be assumed as 0. Consequently, a is assumed to be the maximum of sine(a), which is 1, and b is assumed to be a varied value of sine(a). Correspondingly, a2 in the equation is the maximum width of the PWM at 100% of the duty cycle. This value is fixed at 50 throughout the present study, half the value of the entire maximum amplitude. This value is also related to the PTPER value. The variable b2 is the PDC1 value to be obtained by this study, whose value varies with b.
The HIGH of the PWM signal output by MCU is the actual voltage of 5 V. Therefore, based on Equation (12), 5 can be substituted into a; b is the target amplitude voltage of 3.6 V; a2 is 50, the maximum value of the matrix; b2 is hence the value of the PDCx register to be obtained. It is assumed here that a1 and b1 are 0. By calculation, the target composite waveform voltage level of 3.6 V corresponds to a PDCx value where b2 equals 36. After passing through the filter, the output is 3.36 V, which deviates from the target value of 3.6 V. Repeated corrections by experiment yielded a PDCx value of 38, at which point the output voltage target can be achieved after passing through the filter.
Through the abovementioned interpolation method, the parameters of the sinusoidal wave matrix with the maximum amplitude can be obtained. The next step is to interpolate the value of PDCx register and the actual voltage output to find the required amplitude. The HIGH of the PWM signal output by MCU is the actual voltage of 5 V. Taking the upper half-cycle of 0.7 V as an example, through Equation (12), substituting 5 into a and the amplitude of the upper half-cycle 0.7 V into b, a2 is the maximum value of the matrix 50. The converted value to be obtained is b2, which equals 7. Taking the lower half-cycle of 0.2 V as an example, through Equation (12), substituting −5 into a and the amplitude of the lower half-cycle −0.2 V into b, a2 is then the maximum value of the matrix at −50. The converted value to be obtained is b2 equals −2.
After the abovementioned adjustments to the amplitude and the level, an important variable count has to be performed for the sequence of values to be concatenated into a continuous waveform output. In the program, after each output of the PWM waveform, 1 is added to the variable index to allow the MCU to read the next PWM value of the waveform matrix. As such, a continuous waveform output can be achieved. Therefore, after each PWM waveform output, when a value larger than 1 is added to the variable the number of waveforms in the same unit time will increase. However, this requires a balance between resolution and frequency. Increasing the variable indiscriminately after each PWM output will lead to the reduction of waveform resolution, which will eventually cause serious waveform distortion. Therefore, high analytical sampling is used in this study to mitigate the issue of resolution reduction when the frequency increases. Finally, the upper half-cycle value of
PDCx equal to 7 and the lower half-cycle of
PDCx equal to −2 are added to the computed voltage level
PDCx register value of 38, the result of which is added to the program codes. This produces a waveform matrix that agrees with the target composite charging waveform in this study, as shown in
Figure 1a.
2.3. Design of the Charging Circuit
The charging circuit is designed to adopt the form of a buck synchronous rectifier. A diode is connected after the switching element to allow the inductor to still be in a loop when the switching element is turned off to maintain a flowing current. This is to protect the switching element. Based on the principles of circuit operation, the circuit is set to switch on when the P-MOSFET is at LOW. The S pole of MOSFET is connected to the input power source. The D pole is connected to the power-storing inductor. When the LOW state is maintained at the G pole, MOS is open. When MOSFET is off, the energy in the inductor is released to the output end via the grounded diode. When the MCU output PWM is LOW, the top Positive Channel Metal Oxide Semiconductor (PMOS) is connected. In the meantime, the outer Vancouver Community College (VCC) supplies power to charge the inductor and capacitor. When MCU output PWM signal is HIGH, the top PMOS is disconnected. Then, the outer power is cut off. However, as a result of the afterflow from the inductor, PWM can filter out continuous composite waveforms, as shown in
Figure 3a.
The working sequence is shown in
Figure 3b. The charging loop filter is designed to adopt an LC π filter with low impedance input and output, as shown in
Figure 3c. First, capacitor C1 removes most of the AC components. Then, the L1 and C2 filter are passed through. L1 presents a very high resistance to the AC component. Thus, the AC voltage drop over L1 is large, and the AC component supplied to the load is small. As for the DC component, because L1 does not exhibit inductive resistance, it is equivalent to an open circuit. Simultaneously, the filter inductor adopts a thick wire diameter with very small DC resistance. Therefore, no drop occurs for the DC voltage, resulting in relatively high DC output voltage. These are the main advantages of adopting an inductor filter. After repeated experimental designing as described above, we obtained the values for C1 to be 0.4 μF, L1 to be 192 μH, and C2 to be 101.1 μH. As the desired waveform output is in contrast to the stable DC output, which is the target of a buck architect, and the fixed duty cycle of the PWM is replaced by a variable in real-time PWM duty cycle signal. As verified by circuit simulation software, the composite waveform can be successfully generated.
Figure 3d shows the conversion of signals between components and the final output. The PWM signal of MCU has a fixed output of ca. 0–5 V. To drive the PMOS IRF5305, a higher voltage is needed to keep the PMOS operating in the saturation and cut-off regions. Driving the MOSFET with the HIGH output of only 5 V from the MCU presents a problem that needs to be addressed. In addition, to protect the MCU from being burned, the signal and the power level should be isolated. TLP250 is adopted for the gate driver to increase the PWM signal to ca. 0–15 V through a 15 V input from an external power supply, thereby driving MOSFET to operate in the saturation and cut-off regions. The output end is a battery which attenuates the input charging voltage waveform. Therefore, the VCC of PMOS is set to be larger than the composite waveform voltage. We adopt a 12 V power supply that is widely used in the market. Finally, PWM is restored to the composite waveform by LC low-pass filter in the buck circuit.