Search Results (91)

In this paper, the fabrication and testing of an integrated passive device (IPD) structure for X-band FMCW radar based on the fan-out wafer-level packaging (FOWLP) process are discussed. First, a transition line structure is added to the IPD structure to increase the upper impedance limit of the substrate, so as to reduce the process implementation difficulty and development cost. Second, the vertical soldered SubMiniature Push-On Micro (SMPM) interfaces testing method is proposed, reducing the testing difficulty of the dual-port structure with the antenna. Finally, the process fabrication as well as testing of the IPD structure are completed. The dimensions of the fabricated structure are 16.983 × 24.099 × 0.56 ${\mathrm{mm}}^3$. Test results show that, with a center frequency of 8.5 GHz, the actual operational bandwidth of the structure reaches 7.66% (8.095–8.74 GHz), with a maximum isolation of 33.9 dB. The bandwidth with isolation greater than 20 dB is 1.76% (8.455–8.605 GHz). The maximum gain at the center frequency is 2.02 dBi. Additionally, experimental uncertainty analysis is performed on different IPD structures, and the measurement results are basically consistent. These results validate the feasibility of the FOWLP process in the miniaturization of X-band FMCW radar antenna and other passive devices. Full article

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs. Full article

This study presents an artificial intelligence (AI) prediction platform driven by deep learning technologies, designed specifically to address the challenges associated with predicting warpage behavior in fan-out wafer-level packaging (FOWLP). Traditional electronic engineers often face difficulties in implementing AI-driven models due to the specialized programming and algorithmic expertise required. To overcome this, the platform incorporates a graphical user interface (GUI) that simplifies the design, training, and operation of deep learning models. It enables users to configure and run AI predictions without needing extensive coding knowledge, thereby enhancing accessibility for non-expert users. The platform efficiently processes large datasets, automating feature extraction, data cleansing, and model training, ensuring accurate and reliable predictions. The effectiveness of the AI platform is demonstrated through case studies involving FOWLP architectures, highlighting its ability to provide quick and precise warpage predictions. Additionally, the platform is available in both uniform resource locator (URL)-based and standalone versions, offering flexibility in usage. This innovation significantly improves design efficiency, enabling engineers to optimize electronic packaging designs, reduce errors, and enhance the overall system performance. The study concludes by showcasing the structure and functionality of the GUI platform, positioning it as a valuable tool for fostering further advancements in electronic packaging. Full article

This paper presents a comprehensive review of advancements in wafer-level packaging (WLP) technology, with a particular focus on its application in surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters. As wireless communication systems continue to evolve, there is an increasing demand for higher performance and miniaturization, which has made acoustic wave devices—especially SAW and BAW filters—crucial components in the Radio Frequency (RF) front-end systems of mobile devices. This review explores key developments in WLP technology, emphasizing novel materials, innovative structures, and advanced modeling techniques that have enabled the miniaturization and enhanced functionality of these filters. Additionally, the paper discusses the role of WLP in addressing challenges related to size reduction and integration, facilitating the creation of multi-functional devices with low manufacturing costs and high precision. Finally, it highlights the opportunities and future directions of WLP technology in the context of next-generation wireless communication standards. Full article

Cavity silicon on insulator (Cavity-SOI) offers significant design flexibility for microelectromechanical systems (MEMS). Notably, the shape and depth of the cavity can be tailored to specific requirements, facilitating the realization of intricate multi-layer structural designs. The novelty of the proposed fabrication methodology is manifested in its employment of a micromachining process flow, which integrates dry etching, wafer level Au–Si eutectic bonding, and chemical mechanical polishing (CMP) to create Cavity-SOI. This innovative approach substantially mitigates the complexity of fabrication, and the implementation of wafer-level gold–silicon eutectic bonding and vacuum packaging can be achieved, representing a distinct advantage over conventional methods. To evaluate the technical viability, a MEMS resonant pressure sensor (RPS) was designed. Experimental findings demonstrate that during the formation of Cavity-SOI, dry etching can accurately fabricate cavities of predefined dimensions, wafer-level Au–Si eutectic bonding can achieve efficient sealing, and CMP can precisely regulate the depth of cavities, thus validating the feasibility of the Cavity-SOI formation process. Additionally, when implementing Cavity-SOI in the fabrication of MEMS RPS, it enables the spontaneous release of resonators, effectively circumventing the undercut and adhesion issues commonly encountered with hydrofluoric acid (HF) release. The sensors fabricated using Cavity-SOI exhibit a sensitivity of 100.695 Hz/kPa, a working temperature range spanning from −10–60 °C, a pressure range of 1–120 kPa, and a maximum error of less than 0.012% full scale (FS). The developed micromachining process for Cavity-SOI not only streamlines the fabrication process but also addresses several challenges inherent in traditional MEMS fabrication. The successful fabrication and performance validation of the MEMS RPS confirm the effectiveness and practicality of the proposed method. This breakthrough paves the way for the development of high-performance MEMS devices, opening up new possibilities for various applications in different industries. Full article

This study introduces a novel, non-rotationally symmetrical auxiliary electrode design aimed at mitigating localized hotspots and enhancing the deposition uniformity in wafer-level electroplating for advanced large-scale chip packaging. The formation of hotspots and deposition non-uniformity, particularly at the wafer edge and in regions with complex die layouts, presents significant challenges in electroplating processes. To address these issues, the proposed auxiliary electrode incorporates a dynamic angle control mechanism, which facilitates the precise, localized modulation of the current density. This innovative design improves the regulation of current distribution in hotspot-prone regions, without compromising the overall stability and uniformity of the wafer-level electroplating process. Extensive numerical simulations were conducted to assess the electrode’s effectiveness in redistributing current density, resulting in a marked reduction in current density at the wafer edge, thereby mitigating over-deposition and enhancing overall uniformity. The simulation results also demonstrated the electrode’s capability for dynamic current flow regulation, enabling localized adjustments only when necessary and minimizing disruptions to the electroplating process. Experimental validation further corroborated the simulation findings, with repeated trials confirming the electrode’s consistent performance in reducing localized over-deposition in hotspot regions while maintaining uniform plating in unaffected areas. These findings underscore the potential of the auxiliary electrode as a robust solution for addressing hotspot formation and deposition uniformity challenges in electroplating, providing a solid foundation for its industrial implementation in advanced chip packaging and related fields. Full article

This paper presents a silicon-based wafer-level vacuum packaging platform with a monolithically integrated micro-oven. This system provides vacuum and constant temperature operating conditions to improve the performance of resonant micro-electro-mechanical systems (MEMS) devices. Based on a three-layer wafer-level vacuum packaging process, the platform integrates a silicon thermistor, a thermal isolation structure, and a heater with the addition of a mask and an additional silicon wafer. This wafer-level vacuum-packaging platform achieved a vacuum level of approximately 6 mTorr. Due to the micro-oven, the temperature coefficient of the resonant frequency for the MEMS resonator was reduced by 48 times, and the temperature coefficient of the quality factor was reduced 19 times within the temperature range of −40 °C to 80 °C. The heater of the micro-oven consumed about 364 mW of power when the ambient temperature was −40 °C and the temperature controlled by the micro-oven was 100 °C. This method enables the wafer-level integration of the thermistor, thermal isolation structure, heater, and vacuum-packaged resonator, offering advantages such as low cost, efficient batch production, and high performance. Full article

In this paper, the performance, advantages and challenges of polymer microwave fibers (PMF) for sub-THz links are evaluated first. Then, a simple and elegant transceiver-integrated circuit (IC) and PMF wireless coupling scheme is presented. The proposed solution utilizes an advanced IC packaging technology to implement a Vivaldi antenna-in-package (AiP). The antenna is designed to provide lateral radiation and excellent directivity, so the proposed solution is very simple, compact, robust and cost-efficient: the IC readily connects to the PMF and the coupling is merely achieved by the packaged IC, without the need for any extra interface. The system operates at around 140 GHz, achieving a coupling loss of just 3.5 dB. Full article

In advanced microelectronic packaging, high thermo-mechanical loads arise on the solder interconnects. Accurate and efficient modeling of the mechanical behavior is crucial in the design of the package, and the simulation results can provide a basis for estimations of the reliability of the assembly. However, the accuracy of the simulation results depends on the accuracy of the modeled geometry and the modeling simplifications and assumptions employed to achieve computational cost-efficient calculations. In this work, finite element analysis (FEA) of a Fan Out—Wafer Level Packaging (FO-WLP) layout was carried out considering the following variations: modeling domain (2-D and pseudo-3-D) was defined for creating the efficient calculation framework, where soldering material (SAC 305 and SACQ), incorporation of intermetallic compound (IMC), bond pad edge geometry (sharp and blunt) were modeled for cycles of thermal load. Stress and strain analysis was carried out to evaluate the solder behavior for the parameter variations. Furthermore, fatigue indicators were evaluated. An efficient planar simulation framework with 2-D and pseudo-3-D meshed geometries provides a quick estimate for the lower and upper bound for the strain, stress and strain energy-related parameters, respectively. This calculation framework can be employed for extensive parameter studies solved rapidly at low computational costs. Full article

Silicon–glass anode bonding is the key technology in the process of wafer-level packaging for MEMS sensors. During the anodic bonding process, the device may experience adhesion failure due to the influence of electric field forces. A common solution is to add a metal shielding layer between the glass substrate and the device. In order to solve the problem of device failure caused by the electrostatic attraction phenomenon, this paper designed a double-ended solidly supported cantilever beam parallel plate capacitor structure, focusing on the study of the critical size of the window opening in the metal layer for the electric field shielding effect. The metal shield consists of 400 Å of Cr and 3400 Å of Au. Based on theoretical calculations, simulation analysis, and experimental testing, it was determined that the critical size for an individual opening in the metal layer is 180 μm × 180 μm, with the movable part positioned 5 μm from the bottom, which does not lead to failure caused by stiction due to electrostatic pull-in of the detection structure. It was proven that the metal shielding layer is effective in avoiding suction problems in secondary anode bonding. Full article

This paper describes an analysis of power supply rejection and noise improvement techniques for an envelope-tracking power amplifier. Although the envelope-tracking technique improves efficiency, its power supply rejection ratio is much lower than that of average power tracking or a fixed-supply power amplifier. In FDD systems with the envelope-tracking technique, the low power supply rejection ratio generates much output noise in the RX band and degrades the receiver’s sensitivity. An SM is designed by using a 130 nm CMOS process, and the chip die area is 2 × 2 mm² with a 25-pin wafer-level chip-scale package. The designed SM achieved peak efficiencies of 78–83% for LTE signals with a 5.8 dB PAPR and various channel bandwidths. For the low-output-noise-supply modulator, noise reduction techniques using resonant-frequency tuning and a notch filter are employed, and the measured results show maximum 1.8/5/5.3/3.8/3 dB noise reduction in LTE bands B17/B5/B2/B3/B7, respectively. Full article

The micro disk resonator gyroscope is a micro-mechanical device with potential for navigation-grade applications, where the performance is significantly influenced by the quality factor, which is determined by various energy dissipation mechanisms within the micro resonant structure. To enhance the quality factor, these gyroscopes are typically enclosed in high-vacuum packaging. This paper investigates a wafer-level high-vacuum-packaged (<0.1 Pa) cobweb-like disk resonator gyroscope, presenting a systematic and comprehensive theoretical analysis of the energy dissipation mechanisms, including air damping, thermoelastic damping, anchor loss, and other factors. Air damping is analyzed using both a continuous fluid model and an energy transfer model. The analysis results are validated through quality factor testing on batch samples and temperature characteristic testing on individual samples. The theoretical results obtained using the energy transfer model closely match the experimental measurements, with a maximum error in the temperature coefficient of less than 2%. The findings indicate that air damping and thermoelastic damping are the predominant energy dissipation mechanisms in the cobweb-like disk resonant gyroscope under high-vacuum conditions. Consequently, optimizing the resonator to minimize thermoelastic and air damping is crucial for designing high-performance gyroscopes. Full article

With the advancement of high-integration and high-density interconnection in chip manufacturing and packaging, Cu bumping technology in wafer- and panel- level packaging is developed to micrometer-sized structures and pitches to accommodate increased I/O numbers on high-end integrated circuits. Driven by this industrial demand, significant efforts have been dedicated to Cu electroplating techniques for improved pillar shape control and solder joint reliability, which substantially depend on additive formulations and electroplating parameters that regulate the growth morphology, crystal structure, and impurity incorporation in the process of electrodeposition. It is necessary to investigate the effect of an additive on Cu pillar electrodeposition, and to explore the Kirkendall voids formed during the reflowing process, which may result from the additive-induced impurity in the electrodeposited Cu pillars. In this work, a self-synthesized polyquaterntum (PQ) was made out with dual suppressor and leveler effects, and was combined with prototypical accelerator bis- (sodium sulfopropyl)-disulfide (SPS) for patterned Cu pillar electroplating. Then, Sn96.5/Ag3.0/Cu0.5 (SAC305) solder paste were screen printed on electroplated Cu pillars and undergo reflow soldering. Kirkendall voids formed at the joint interfaces were observed and quantified by SEM. Finally, XRD, and EBSD were employed to characterize the microstructure under varying conditions. The results indicate that PQ exhibits significant suppressive and levelled properties with the new structure of both leveler and suppressor. However, its effectiveness is dependent on liquid convection. PQ and SPS work synergistically, influencing the polarization effect in various convective environments. Consequently, uneven adsorption occurs on the surface of the Cu pillars, which results in more Kirkendall voids at the corners than at the center along the Cu pillar surface. Full article

This paper presents an integrated passive device (IPD) structure based on fan-out wafer-level packaging (FOWLP) for the front end of frequency-modulated continuous wave (FMCW) radar systems, focusing on enhancing the integration efficiency and performance of large passive components like antennas. Additionally, a new metric is introduced to assess this structure’s effect on the average noise figure in FMCW systems. Using this metric as a loss function, we apply the support vector machine (SVM) for electromagnetic simulation and the genetic algorithm (GA) for optimization. The sample fitting variance is 2.42 dB, reducing computation time from 12 min to under 1 millisecond, with the entire optimization completed in less than 100 s. The optimized IPD structure is 0.7 × 0.9 × 0.014 ${{\lambda }_0}^3$ in size and achieves over 35 dB isolation between the transmitter and receiver. Compared to the IPD model calculated by empirical formulas, the optimized device lowers the average noise figure by 15.2 dB and increases maximum gain by 4.19 dB. Full article

The semiconductor industry is a pivotal hub in the global information sector, in which superpowers compete for technological dominance. As a strategic, leading, and foundational sector, it is vital for advancing China’s manufacturing ambitions through new waves of transformation and upgrades. Therefore, of particular concern is the crisis surrounding China’s semiconductor supply chain insecurity and the intensifying U.S. sanctions on China’s high-tech companies. As such, in this study, we utilize data from China’s semiconductor enterprises, investments, and related statistics from 2002 to 2020; industrial agglomeration indicators; and a social network analysis to examine the spatiotemporal pattern, industrial agglomeration, and investment networks of six key value chain segments: wafer materials, packaging materials, semiconductor equipment, integrated circuit (IC) design, manufacturing, and testing/packaging. The research focuses on how these sectors can contribute to sustainable growth and economic responsibility within China’s semiconductor industry. Accordingly, the core questions explored were as follows: what are the provincial-level spatial production dynamics and evolutionary characteristics within China’s semiconductor industry, and how do the inter-provincial investment patterns manifest? The findings reveal the following: (1) The findings reveal a strong concentration of firms in the Eastern Coastal region, particularly in Jiangsu, Shanghai, Zhejiang, and Guangdong. Additionally, IC design exhibits the highest clustering, and other segments such as wafer materials, manufacturing, and packaging/testing are relatively concentrated, whereas equipment distribution is more dispersed. (2) The industry expanded steadily from 2002 to 2013, with a rapid expansion from 2014 to 2020, particularly in Guangdong. (3) Investment patterns are characterized by local and regional focus, strongly influenced by geographical proximity. This study aims to reveal the geographic concentration patterns of China’s semiconductor industry and to explore its investment networks. The findings are intended to provide theoretical support for optimizing sustainable industrial layouts, promoting sustainable industrial practices, and guiding policy formulation. Furthermore, in the broader context of de-globalization, this study offers insights and recommendations for strengthening industrial autonomy and sustainability in response to external challenges, thereby contributing to the sustainable development of a more robust domestic semiconductor supply chain. These insights are particularly significant in safeguarding China’s technological independence and future economic stability amid global tensions. Furthermore, by integrating sustainability into its semiconductor industry, China can create a more resilient, self-sufficient, and environmentally responsible industrial sector, capable of meeting both domestic and global demands. As China continues to expand its semiconductor industry, incorporating sustainable development principles will be essential for long-term success. The sustainable practices not only ensures compliance with environmental regulations but also enhances industrial competitiveness, promotes green techniques and contributes to broader societal goals. This aligns with China’s broader ambitions for sustainable development and positions the country as a key player in the global green technology revolution. Full article