Search Results (14)

This paper investigates the performance of vacuum gate dielectric doping-free carbon nanotube/nanoribbon field-effect transistors (VGD-DL CNT/GNRFETs) via computational analysis employing a quantum simulation approach. The methodology integrates the self-consistent solution of the Poisson solver with the mode space non-equilibrium Green’s function (NEGF) in the ballistic limit. Adopting the vacuum gate dielectric (VGD) paradigm ensures radiation-hardened functionality while avoiding radiation-induced trapped charge mechanisms, while the doping-free paradigm facilitates fabrication flexibility by avoiding the realization of a sharp doping gradient in the nanoscale regime. Electrostatic doping of the nanodevices is achieved via source and drain doping gates. The simulations encompass MOSFET and tunnel FET (TFET) modes. The numerical investigation comprehensively examines potential distribution, transfer characteristics, subthreshold swing, leakage current, on-state current, current ratio, and scaling capability. Results demonstrate the robustness of vacuum nanodevices for high-performance, radiation-hardened switching applications. Furthermore, a proposal for extrinsic enhancement via doping gate voltage adjustment to optimize band diagrams and improve switching performance at ultra-scaled regimes is successfully presented. These findings underscore the potential of vacuum gate dielectric carbon-based nanotransistors for ultrascaled, high-performance, energy-efficient, and radiation-immune nanoelectronics. Full article

A new structure for PNPN tunnel field-effect transistors (TFETs) has been designed and simulated in this work. The proposed structure incorporates the polarity bias concept and the gate work function engineering to improve the DC and analog/RF figures of merit. The proposed device consists of a control gate (CG) and a polarity gate (PG), where the PG uses a dual-material gate (DMG) structure and is biased at −0.7 V to induce a P⁺ region in the source. The PNPN structure introduces a local minimum on the conduction band edge curve at the tunneling junction, which dramatically reduces the tunneling width. Furthermore, we show that incorporating the DMG architecture further enhances the drive current and improves the subthreshold slope (SS) characteristics by introducing an additional electric field peak. The numerical simulation reveals that the electrically doped PNPN TFET using DMG improves the DC and analog/RF performances in comparison to a conventional single-material gate (SMG) device. Full article

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell. Full article

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the first time. The TCAD simulator is used to examine the performance of a dielectrically modulated label-free biosensor. The voltage and current sensitivity of the device and the effects of the cavity size, bioanalyte electric charge, fill factor, and location on the performance of the biosensor are also investigated. The relative current sensitivity of the biosensor is found to be about 10¹³. Besides showing an enhanced sensitivity compared with other FET- and TFET-based biosensors, the device proves itself convenient for low-power applications, thus opening up numerous directions for future research and applications. Full article

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications. Full article

Miniaturization and portable devices have reshaped the electronic device landscape, emphasizing the importance of high performance while maintaining energy efficiency to ensure long battery life. FinFET and Tunnel-FET technologies have emerged as attractive alternatives to overcome the limitations of supply voltage scaling for ultra-low power applications. This work compares the performance of 10 nm FinFET- and TFET-based digital circuits from basic logic gates up to an 8k gates low-power microprocessor. When compared with their FinFET-based counterparts, the TFET-based logic gates have lower leakage power when operated below 300 mV, show higher input capacitance, and exhibit a reduced propagation delay under different fan-in and fan-out conditions. Our comparative study was extended to the synthesis of an MSP-430 microprocessor through standard cell libraries built particularly for this work. It is demonstrated that the TFET-based synthesized circuits operating at ultra-low voltages achieve a higher performance in terms of speed at the cost of increased power consumption. When the speed requirements are relaxed, the TFET-based designs are the most energy-efficient alternative. It is concluded that the TFET is an optimal solution for ultra-low voltage design. Full article

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology. Full article

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 $\mathrm{V}$), while showing energy savings of 50% and faster write switching of 60%. Full article

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices. Full article

In this paper, we present an in-built N⁺ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at −0.7 V to induce a P⁺ region at the source side, leaving an N⁺ pocket between the source and the channel. This technique yields an N⁺ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N⁺ pocket yields a higher I_ON and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (E_C) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N⁺ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications. Full article

A long-standing goal of nanoelectronics is the development of integrated systems to be used in medicine as sensor, therapeutic, or theranostic devices. In this review, we examine the phenomena of transport and the interaction between electro-active charges and the material at the nanoscale. We then demonstrate how these mechanisms can be exploited to design and fabricate devices for applications in biomedicine and bioengineering. Specifically, we present and discuss electrochemical devices based on the interaction between ions and conductive polymers, such as organic electrochemical transistors (OFETs), electrolyte gated field-effect transistors (FETs), fin field-effect transistor (FinFETs), tunnelling field-effect transistors (TFETs), electrochemical lab-on-chips (LOCs). For these systems, we comment on their use in medicine. Full article

The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle was injected into a field effect transistor (FET), which resulted in a drain current fluctuation and caused the integrated circuit to malfunction as the result of a soft-error-rate (SER) issue. It was subsequently observed that radiation effects on NS-TFET were completely different from a conventional drift-diffusion (DD)-based FET. Unlike a conventional DD-based FET, when an alpha particle enters the source and channel areas in the current scenario, a larger drain current fluctuation occurs due to a tunneling mechanism between the source and the channel, and this has a significant effect on the drain current. In addition, as the temperature increases, the radiation effect increases as a result of a decrease in silicon bandgap energy and a resultant increase in band-to-band generation. Finally, the radiation effect was analyzed according to the energy of the alpha particle. These results can provide a guideline by which to design a robust integrated circuit for radiation that is totally different from the conventional DD-FET approach. Full article

Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (I_AMB). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (I_ON), I_AMB, and gate-to-drain capacitance (C_GD). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot. Full article

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device I_on, I_off, C_g, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device I_on and I_off. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better I_on and C_g,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse I_off variability of TFET devices. Full article