Search Results (157)

This work introduces an innovative approach for estimating the Single-Event Upset (SEU) cross-sections in Static Random-Access Memory (SRAM) devices, addressing challenges related to limited technological information and the complexity of Technology Computer-Aided Design (TCAD) simulations. The proposed methodology is designed to be accessible even to users without in-depth TCAD expertise, enabling a streamlined yet accurate SEU cross-section estimation. Using simplified mixed-modeling (TCAD-based 2D modeling with circuit-level SPICE simulations), this approach significantly reduces computational efforts while maintaining good correlation with experimental data. Furthermore, this study identifies key parameters that influence TCAD modeling accuracy and proposes strategies for approximating unknown parameters, enhancing the reliability of SEU cross-section predictions. Full article

This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm²/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm²/mg at 300 K, dropping to 6 MeV cm²/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10⁻⁴ A/μm at 300 K to 4.65 × 10⁻⁵ A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K. Full article

The U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor (UMOS or trench FET) is one of the most widely used semiconductor power devices worldwide, increasingly replacing the traditional vertical double-diffused MOSFET (DMOSFET) in various applications due to its superior electrical performance. However, a detailed experimental comparison of ion-induced Single-Event Burnout (SEB) in similarly rated silicon (Si) UMOS and DMOS devices remains lacking. This study presents a comprehensive experimental comparison of ion-induced charge collection mechanisms and SEB susceptibility in similarly rated Si UMOS and DMOS devices. Charge collection mechanisms due to alpha particles from ²⁴¹Am radiation source are analyzed, and SEB cross sections induced by heavy ions from particle accelerators are directly compared. The implications of the unique gate structure of Si UMOSFETs on their reliability in harsh radiation environments are discussed based on technology computer-aided design (TCAD) simulations. Full article

Benefiting from the progress of the germanium (Ge) epitaxy process on silicon (Si) substrates, waveguide-integrated Ge-on-Si photodetectors (PDs) have demonstrated decent performances in short-wave infrared (SWIR) detection. By lowering the operating temperature, theses PDs can meet the stringent signal-to-noise requirements for high-sensitivity detection. We systematically investigated the dark current characteristics and optical response in the 1500–1600 nm wavelength range of the waveguide-integrated Ge-on-Si PDs operated at low temperatures (200 K to 300 K). Under a −3 V bias, the PD exhibits a room-temperature dark current of 4.62 nA and a responsivity of 0.87 A/W at 1550 nm. When the temperature was reduced to 200 K, the dark current decreased to 93.69 pA, and the responsivity dropped to 0.34 A/W. Using finite-difference time-domain (FDTD) and technology computer-aided design (TCAD) simulations, we extracted the absorption coefficients of epitaxial Ge on Si at low temperatures. At room temperature, the absorption coefficient at the wavelength of 1550 nm was approximately 1100 cm⁻¹, while at 200 K, the absorption coefficient decreased to 248 cm⁻¹. The outcomes of this work pave the way for the high-performance low-temperature Si photonic systems in the future. Full article

The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO₂/SiO_xN_y/SiO₂ (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability. Full article

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 10³. Full article

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (R_DS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in R_DS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in R_DS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs. Full article

Amorphous oxide semiconductor transistors with a high current density output are highly desirable for large-area electronics. In this study, wrapping amorphous indium-gallium-zinc-oxide (a-IGZO) transistors are proposed to enhance the current density output relative to a-IGZO source-gated transistors (SGTs). Device performances are analyzed using technology computer-aided design (TCAD) simulations. The TCAD simulation results reveal that, with an optimized device structure, the current density of the wrapping a-IGZO transistor can reach 7.34 μA/μm, representing an approximate two-fold enhancement compared to that of the a-IGZO SGT. Furthermore, the optimized wrapping a-IGZO transistor exhibits clear flat saturation and pinch-off behavior. The proposed wrapping a-IGZO transistors show significant potential for applications in large-area electronics. Full article

In the present study, a novel normally-off vertical GaN MOSFET with an enhanced AlGaN/GaN channel on the sidewall has been proposed using the technology computer-aided design (TCAD) simulation. By using the selective area growth process, the trench structure and the enhanced sidewall channel are formed simultaneously, which is beneficial to enhance the conduction capability compared with the conventional trenched MOSFET. It demonstrates that a proper hole concentration and thickness of the p-GaN layer are key parameters to balance the threshold voltage, on-state resistance, and off-state breakdown voltage, resulting in the highest Baliga’s figure of merit value. Furthermore, a p-GaN shield layer is also adopted as a junction termination extension to modulate the electric field around the trench bottom. By optimizing the device parameters, a normally-off GaN MOSFET with good performance is designed. Full article

This study proposes an AlGaN/GaN current aperture vertical electron transistor (CAVET) featuring a double superjunction (SJ) to enhance breakdown voltage (BV) and investigates its electrical characteristics via technology computer-aided design (TCAD) Silvaco Atlas simulation. An additional p-pillar was formed beneath the gate current blocking layer to create a lateral depletion region that provided a high off-state breakdown voltage. To address the tradeoff between the drain current and off-state breakdown voltage, the key design parameters were carefully optimized. The proposed device exhibited a higher off-state breakdown voltage (2933 V) than the device with a single SJ (2786 V), although the specific on-resistance of the proposed method (1.29 mΩ·cm⁻²) was slightly higher than that of the single SJ device (1.17 mΩ·cm⁻²). In addition, the reverse transfer capacitance was improved by 15.6% in the proposed device. Full article

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity. Full article

Neural network (NN)-based compact modeling methodologies are gaining attention due to the challenges of device complexity, narrow model coverage, and SPICE simulation speed in advanced semiconductor technology nodes. As device complexity increases, the number of process and structural variables also increases, which significantly increases the amount of technology computer-aided design (TCAD) simulation data required for NN-based compact modeling. This study proposes a multi-fidelity model and active learning approach to predict global and local variations of nanosheet FETs (NSFETs) with less than 1.5% error, significantly reducing the number of required TCAD simulations by more than half compared with conventional modeling techniques. In addition, the simplified NN model with a smaller training dataset significantly reduces the SPICE simulation time. Full article

A novel planar silicon carbide (SiC) MOSFET integrated with both MOS-channel diode (MCD) and junction barrier Schottky diode (JBS) on the same chip (MCD-JBSFET) is proposed and investigated through Technology Computer-Aided Design (TCAD) simulations in this paper. The proposed device features the lowest turn-on voltage and the best current conduction capability under the reverse-biased conditions, allowing it to achieve the same reverse conduction capability with fewer MCDs compared to conventional MOSFET with MCD structures (MCDFET). This reduction in the number of MCDs enables more channels to operate under forward-biased conditions, thereby improving power density. Compared to a conventional MOSFET integrated with JBS structure (JBSFET), the reverse current in the MCD-JBSFET flows through both the MCD and JBS, which suppresses the peak lattice temperature at Schottky contact and enhances the high-temperature robustness, especially under surge current conditions. In addition, the split-gate structure in the proposed structure optimizes the reverse capacitance and the figure of merit R_on,sp × Q_g by factors of 0.65 and 2.15, respectively. Finally, the switching losses are reduced by 40.2%, indicating the suitability of MCD-JBSFET for high-frequency and high-current applications. Full article

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CISs), known for their high integration, low cost, and superior performance, have found widespread applications in satellite and space exploration. However, the readout circuits of pixel arrays are vulnerable to functional failures in complex or intense radiation environments, particularly due to transient γ radiation. Using Technology Computer-Aided Design (TCAD) device simulations and Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulations, combined with a double-exponential current source fault injection method, this study investigates the transient dose rate effect (TDRE) on a typical readout circuit of CISs. It presents the variations in the photoelectric signal under different dose rates and at different occurrence moments of the TDRE. The results show that, under low dose rates, the CIS readout circuit can still perform data acquisition and digital processing, with the photoelectric signal exhibiting some sensitivity to the occurrence moment. At high dose rates, however, the photoelectric signal not only remains sensitive to the occurrence moment but also shows significant discreteness. Further analysis of the CIS readout circuit sequence suggests that the occurrence moment is a critical factor affecting the circuit’s performance and should not be overlooked. These findings provide valuable insights and references for further research on the TDRE in circuits. Full article

This paper presents a method for modeling ReRAM in TCAD and validating its accuracy for neuromorphic systems. The data obtained from TCAD are used to analyze the accuracy of the neuromorphic system. The switching behaviors of ReRAM are implemented using the kinetic Monte Carlo (KMC) approach. Realistic ReRAM characteristics are obtained through the use of the trap-assisted tunneling (TAT) model and thermal equations. HfO₂-Al₂O₃-based ReRAM offers improved switching behaviors compared to HfO₂-based ReRAM. The variation in conductance depends on the structure of the ReRAM. The conductance extracted from TCAD is validated in the neuromorphic system using the MNIST (Modified National Institute of Standards and Technology) dataset. Full article