MDPI - Publisher of Open Access Journals

23 pages, 4836 KiB

Open AccessEditor’s ChoiceArticle

Parylene C as a Multipurpose Material for Electronics and Microfluidics

by Beatriz J. Coelho, Joana V. Pinto, Jorge Martins, Ana Rovisco, Pedro Barquinha, Elvira Fortunato, Pedro V. Baptista, Rodrigo Martins and Rui Igreja

Polymers 2023, 15(10), 2277; https://doi.org/10.3390/polym15102277 - 12 May 2023

Cited by 21 | Viewed by 9644

Abstract

Poly(p-xylylene) derivatives, widely known as Parylenes, have been considerably adopted by the scientific community for several applications, ranging from simple passive coatings to active device components. Here, we explore the thermal, structural, and electrical properties of Parylene C, and further present a variety [...] Read more.

Poly(p-xylylene) derivatives, widely known as Parylenes, have been considerably adopted by the scientific community for several applications, ranging from simple passive coatings to active device components. Here, we explore the thermal, structural, and electrical properties of Parylene C, and further present a variety of electronic devices featuring this polymer: transistors, capacitors, and digital microfluidic (DMF) devices. We evaluate transistors produced with Parylene C as a dielectric, substrate, and encapsulation layer, either semitransparent or fully transparent. Such transistors exhibit steep transfer curves and subthreshold slopes of 0.26 V/dec, negligible gate leak currents, and fair mobilities. Furthermore, we characterize MIM (metal–insulator–metal) structures with Parylene C as a dielectric and demonstrate the functionality of the polymer deposited in single and double layers under temperature and AC signal stimuli, mimicking the DMF stimuli. Applying temperature generally leads to a decrease in the capacitance of the dielectric layer, whereas applying an AC signal leads to an increase in said capacitance for double-layered Parylene C only. By applying the two stimuli, the capacitance seems to suffer from a balanced influence of both the separated stimuli. Lastly, we demonstrate that DMF devices with double-layered Parylene C allow for faster droplet motion and enable long nucleic acid amplification reactions. Full article

► Show Figures

Graphical abstract

7 pages, 2564 KiB

Open AccessCommunication

Simulation of a Steep-Slope p- and n-Type HfS₂/MoTe₂ Field-Effect Transistor with the Hybrid Transport Mechanism

by Juan Lyu and Jian Gong

Nanomaterials 2023, 13(4), 649; https://doi.org/10.3390/nano13040649 - 7 Feb 2023

Cited by 1 | Viewed by 2057

Abstract

The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs). In addition to the selection of source materials [...] Read more.

The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs). In addition to the selection of source materials with linearly decreasing density-of-states-energy relations (D(E)s), in this study, we further verified, by means of a computer simulation, that a 2D semiconductor-semiconductor combination could also be used as an efficient CS. As a test case, a HfS₂/MoTe₂ FET was studied. It was found that MoTe₂ can be spontaneously p-type-doped by interfacing with n-doped HfS₂, resulting in a truncated decaying hot-carrier density with an increasing p-type channel barrier. Compared to the conventional MoTe₂ FET, the subthreshold swing (SS) of the HfS₂/MoTe₂ FET can be significantly reduced to below 60 mV/decade, and the on-state current can be greatly enhanced by more than two orders of magnitude. It was found that there exists a hybrid transport mechanism involving the cold injection and the tunneling effect in such a p- and n-type HfS₂/MoTe₂ FET, which provides a new design insight into future low-power and high-performance 2D electronics from a physical point of view. Full article

(This article belongs to the Special Issue First-Principles Investigations of Low-Dimensional Nanomaterials)

► Show Figures

Figure 1

9 pages, 2190 KiB

Open AccessArticle

Steep-Slope and Hysteresis-Free MoS₂ Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric

by Xinge Tao, Lu Liu and Jingping Xu

Nanomaterials 2022, 12(24), 4352; https://doi.org/10.3390/nano12244352 - 7 Dec 2022

Cited by 1 | Viewed by 2141

Abstract

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not [...] Read more.

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS₂ NCFET is fabricated using a single Hf_0.5−xZr_0.5−xAl_2xO_y (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the Hf_0.5Zr_0.5O₂ (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 10⁶. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/Al₂O₃ stack gates. Full article

► Show Figures

Figure 1

10 pages, 3371 KiB

Open AccessEditor’s ChoiceArticle

Low-Power OR Logic Ferroelectric In-Situ Transistor Based on a CuInP₂S₆/MoS₂ Van Der Waals Heterojunction

by Kun Yang, Shulong Wang, Tao Han and Hongxia Liu

Nanomaterials 2021, 11(8), 1971; https://doi.org/10.3390/nano11081971 - 31 Jul 2021

Cited by 8 | Viewed by 4608

Abstract

Due to the limitations of thermodynamics, the Boltzmann distribution of electrons hinders the further reduction of the power consumption of field-effect transistors. However, with the emergence of ferroelectric materials, this problem is expected to be solved. Herein, we demonstrate an OR logic ferroelectric [...] Read more.

Due to the limitations of thermodynamics, the Boltzmann distribution of electrons hinders the further reduction of the power consumption of field-effect transistors. However, with the emergence of ferroelectric materials, this problem is expected to be solved. Herein, we demonstrate an OR logic ferroelectric in-situ transistor based on a CIPS/MoS₂ Van der Waals heterojunction. Utilizing the electric field amplification of ferroelectric materials, the CIPS/MoS₂ vdW ferroelectric transistor offers an average subthreshold swing (SS) of 52 mV/dec over three orders of magnitude, and a minimum SS of 40 mV/dec, which breaks the Boltzmann limit at room temperature. The dual-gated ferroelectric in-situ transistor exhibits excellent OR logic operation with a supply voltage of less than 1 V. The results indicate that the CIPS/MoS₂ vdW ferroelectric transistor has great potential in ultra-low-power applications due to its in-situ construction, steep-slope subthreshold swing and low supply voltage. Full article

(This article belongs to the Special Issue 2D Semiconducting Materials for Device Applications)

► Show Figures

Figure 1

9 pages, 2352 KiB

Open AccessArticle

Effects of Interface Trap on Transient Negative Capacitance Effect: Phase Field Model

by Taegeon Kim and Changhwan Shin

Electronics 2020, 9(12), 2141; https://doi.org/10.3390/electronics9122141 - 14 Dec 2020

Cited by 8 | Viewed by 3784

Abstract

Ferroelectric materials have received significant attention as next-generation materials for gates in transistors because of their negative differential capacitance. Emerging transistors, such as the negative capacitance field effect transistor (NCFET) and ferroelectric field-effect transistor (FeFET), are based on the use of ferroelectric materials. [...] Read more.

Ferroelectric materials have received significant attention as next-generation materials for gates in transistors because of their negative differential capacitance. Emerging transistors, such as the negative capacitance field effect transistor (NCFET) and ferroelectric field-effect transistor (FeFET), are based on the use of ferroelectric materials. In this work, using a multidomain 3D phase field model (based on the time-dependent Ginzburg–Landau equation), we investigate the impact of the interface-trapped charge (Q_it) on the transient negative capacitance in a ferroelectric capacitor (i.e., metal/Zr-HfO₂/heavily doped Si) in series with a resistor. The simulation results show that the interface trap reinforces the effect of transient negative capacitance. Full article

(This article belongs to the Special Issue Steep-Switching Devices)

► Show Figures

Figure 1

7 pages, 1053 KiB

Open AccessProceeding Paper

Molybdenum Disulfide Field Effect Transistors under Electron Beam Irradiation and External Electric Fields

by Aniello Pelella, Alessandro Grillo, Enver Faella, Filippo Giubileo, Francesca Urban and Antonio Di Bartolomeo

Mater. Proc. 2021, 4(1), 25; https://doi.org/10.3390/IOCN2020-07807 - 10 Nov 2020

Viewed by 1386

Abstract

In this work, monolayer molybdenum disulfide (MoS₂) nanosheets, obtained via chemical vapor deposition onto SiO₂/Si substrates, are exploited to fabricate field-effect transistors with n-type conduction, high on/off ratio, steep subthreshold slope and good mobility. We study their electric characteristics [...] Read more.

In this work, monolayer molybdenum disulfide (MoS₂) nanosheets, obtained via chemical vapor deposition onto SiO₂/Si substrates, are exploited to fabricate field-effect transistors with n-type conduction, high on/off ratio, steep subthreshold slope and good mobility. We study their electric characteristics from 10⁻⁶ Torr to atmospheric air pressure. We show that the threshold voltage of the transistor increases with the growing pressure. Moreover, Schottky metal contacts in monolayer molybdenum disulfide (MoS₂) field-effect transistors (FETs) are investigated under electron beam irradiation conditions. It is shown that the exposure of Ti/Au source/drain electrodes to an electron beam reduces the contact resistance and improves the transistor performance. It is shown that e-beam irradiation lowers the Schottky barrier at the contacts due to thermally induced atom diffusion and interfacial reactions. The study demonstrates that electron beam irradiation can be effectively used for contact improvement though local annealing. It is also demonstrated that the application of an external field by a metallic nanotip induces a field emission current, which can be modulated by the voltage applied to the Si substrate back-gate. Such a finding, that we attribute to gate-bias lowering of the MoS₂ electron affinity, enables a new field-effect transistor based on field emission. Full article

(This article belongs to the Proceedings of The 2nd International Online-Conference on Nanomaterials)

► Show Figures

Figure 1

8 pages, 2685 KiB

Open AccessArticle

High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

by Te Jui Yen, Albert Chin and Vladimir Gritsenko

Nanomaterials 2020, 10(11), 2145; https://doi.org/10.3390/nano10112145 - 28 Oct 2020

Cited by 16 | Viewed by 5260

Abstract

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO₂ TFTs, with a high field-effect mobility (μ_FE) [...] Read more.

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO₂ TFTs, with a high field-effect mobility (μ_FE) of 136 cm²/Vs, a large on-current/off-current (I_ON/I_OFF) of 1.5 × 10⁸, and steep subthreshold slopes of 108 mV/dec. Here, μ_FE represents the maximum among the top-gate TFTs made on an amorphous SiO₂ substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO₂ channel layer of 4.5 nm and an HfO₂ gate dielectric with a 3 nm SiO₂ interfacial layer between the SnO₂ and HfO₂. The inserted SiO₂ layer is crucial for decreasing the charged defect scattering in the HfO₂ and HfO₂/SnO₂ interfaces to increase the mobility. Such high μ_FE, large I_ON, and low I_OFF top-gate SnO₂ devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs. Full article

(This article belongs to the Special Issue Nanoscience and Nanotechnology for Electronics)

► Show Figures

Figure 1

18 pages, 8212 KiB

Open AccessArticle

Analytical Study of Front-End Circuits Coupled to Silicon Photomultipliers for Timing Performance Estimation under the Influence of Parasitic Components

by Pietro Antonio Paolo Calò, Savino Petrignani, Michele Di Gioia and Cristoforo Marzocca

Sensors 2020, 20(16), 4428; https://doi.org/10.3390/s20164428 - 8 Aug 2020

Cited by 3 | Viewed by 3738

Abstract

Full exploitation of the intrinsic fast timing capabilities of analog silicon photomultipliers (SiPMs) requires suitable front-end electronics. Even a parasitic inductance of a few nH, associated to the interconnections between the SiPM and the preamplifier, can significantly degrade the steepness of the detector [...] Read more.

Full exploitation of the intrinsic fast timing capabilities of analog silicon photomultipliers (SiPMs) requires suitable front-end electronics. Even a parasitic inductance of a few nH, associated to the interconnections between the SiPM and the preamplifier, can significantly degrade the steepness of the detector response, thus compromising the timing accuracy. In this work, we propose a simple analytic expression for the single-photon response of a SiPM coupled to the front-end electronics, as a function of the main parameters of the detector and the preamplifier, taking into account the parasitic inductance. The model is useful to evaluate the influence of each parameter of the system on the slope of its response and to guide the designer in the definition of the architecture and the specifications for the front-end electronics. The results provided by the model have been successfully compared with experimental measurements from a front-end circuit with variable configuration based on a bipolar junction transistor (BJT), coupled to a 3 × 3 mm² SiPM stimulated by a fast-pulsed laser source. Full article

(This article belongs to the Special Issue Electronics for Sensors)

► Show Figures

Figure 1

11 pages, 2983 KiB

Open AccessArticle

Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope

by Faraz Najam and Yun Seop Yu

Electronics 2018, 7(11), 275; https://doi.org/10.3390/electronics7110275 - 24 Oct 2018

Cited by 8 | Viewed by 3994

Abstract

The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades [...] Read more.

The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance. Full article

(This article belongs to the Special Issue Nanoelectronic Materials, Devices and Modeling)

► Show Figures

Figure 1

7 pages, 2004 KiB

Open AccessArticle

Steep Switching of In_0.18Al_0.82N/AlN/GaN MIS-HEMT (Metal Insulator Semiconductor High Electron Mobility Transistors) on Si for Sensor Applications

by Pin-Guang Chen, Kuan-Ting Chen, Ming Tang, Zheng-Ying Wang, Yu-Chen Chou and Min-Hung Lee

Sensors 2018, 18(9), 2795; https://doi.org/10.3390/s18092795 - 24 Aug 2018

Cited by 5 | Viewed by 4500

Abstract

InAlN/Al/GaN high electron mobility transistors (HEMTs) directly on Si with dynamic threshold voltage for steep subthreshold slope (<60 mV/dec) are demonstrated in this study, and attributed to displacement charge transition effects. The material analysis with High-Resolution X-ray Diffraction (HR-XRD) and the relaxation by [...] Read more.

InAlN/Al/GaN high electron mobility transistors (HEMTs) directly on Si with dynamic threshold voltage for steep subthreshold slope (<60 mV/dec) are demonstrated in this study, and attributed to displacement charge transition effects. The material analysis with High-Resolution X-ray Diffraction (HR-XRD) and the relaxation by reciprocal space mapping (RSM) are performed to confirm indium barrier composition and epitaxy quality. The proposed InAlN barrier HEMTs exhibits high ON/OFF ratio with seven magnitudes and a steep threshold swing (SS) is also obtained with SS = 99 mV/dec for forward sweep and SS = 28 mV/dec for reverse sweep. For GaN-based HEMT directly on Si, this study displays outstanding performance with high ON/OFF ratio and SS < 60 mV/dec behaviors. Full article

(This article belongs to the Special Issue Selected Papers from the 7th IEEE International Symposium on Next-Generation Electronics (ISNE 2018))

► Show Figures

Figure 1

Search Results (10)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

Saved Queries

Search Filter Reset All

Years

Feature Papers

Subjects

Journals

Article Types

Countries / Regions

Search Results (10)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI