Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope

The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance.

It was found using device simulations that the 2D corner effect [6] present in LTFETs degrades its subthreshold performance.In order to remove SS degradation due to the kink effect induced by the source corner, the fully depleted rounded corner with a gradual doping profile was used [6].The LTFET still achieves a sub-thermal SS, but as shown in this work there is room for significant improvement in the subthreshold performance of LTFETs.To achieve this improvement, a new device based on the original LTFET is introduced.The new device uses a dual-gate (DG) structure and is termed the DG-LTFET.The two gates (gate1 and gate2) have different workfunctions and different heights.The DG-LTFET was thoroughly evaluated for different device parameters, including the source region height, gate1 and gate2 heights, gate1 and gate2 workfunctions, channel thickness, and drain doping levels.Optimum dimensions and drain doping level were determined for the DG-LTFET.Section 2 briefly discusses the corner-effect problem of the LTFET.Section 3 introduces the DG-LTFET and compares its results with the LTFET.Section 4 presents the conclusion.

The LTFET: The Corner Effect
Figure 1 shows a schematic for LTFET.The p + (10 20 cm −3 ) doped source region overlaps the gate with the n − (10 12 cm −3 ) channel sandwiched in between them.This sandwiched channel region is termed as R nonoffset .There is also a part of the channel termed R offset in which there is an offset present between the source and the gate, as indicted in Figure 1.The following parameters were used for all devices considered in this work unless otherwise specified: source height (H s ) = 40 nm, oxide thickness (t ox ) = 2 nm, length of R nonoffset (T j ) = 5 nm, channel length (L ch ) = 50 nm, height of R offset (H offset ) = 10 nm, height of R nonoffset (H nonoffset ) = H s , gate height (H g1 ) = H s + (H offset − t ox ) = 48 nm, dielectric permittivity ε ox = 25, metal gate workfunction W rk_LTFET = 4.72 eV, and drain doping (N d ) = 10 20 cm −3 .
Electronics 2018, 7, x FOR PEER REVIEW 2 of 11 introduces the DG-LTFET and compares its results with the LTFET.Section 4 presents the conclusion.

The LTFET: The Corner Effect
Figure 1 shows a schematic for LTFET.The p + (10 20 cm −3 ) doped source region overlaps the gate with the n − (10 12 cm −3 ) channel sandwiched in between them.This sandwiched channel region is termed as Rnonoffset.There is also a part of the channel termed Roffset in which there is an offset present between the source and the gate, as indicted in Figure 1.The following parameters were used for all devices considered in this work unless otherwise specified: source height (Hs) = 40 nm, oxide thickness (tox) = 2 nm, length of Rnonoffset (Tj) = 5 nm, channel length (Lch) = 50 nm, height of Roffset (Hoffset) = 10 nm, height of Rnonoffset (Hnonoffset) = Hs, gate height (Hg1) = Hs + (Hoffset − tox) = 48 nm, dielectric permittivity εox = 25, metal gate workfunction Wrk_LTFET = 4.72 eV, and drain doping (Nd) = 10 20 cm −3 .Sentaurus technology-computer-aided-design tool (TCAD) was used as the simulator [7].The following models were used in the simulation: the dynamic nonlocal band-to-band-tunneling (BTBT) model, Fermi statistics, and the constant mobility model.The dynamic nonlocal BTBT model calculates BTBT in both lateral and 1D directions.Crystal orientation is assumed to be <100> in all devices.A constant electron effective tunneling mass of 0.19 mo was used in all simulations [8].All simulations were performed at a drain source bias Vds = 0.1 V unless otherwise specified.
For analysis to follow, drain-source current (Ids) versus gate-source bias (Vgs) characteristics of the LTFET are shown in Figure 2a.There is a direct overlap between gate and source in Rnonoffset, and the electric field in Rnonoffset is in the 1D direction.In Roffset, however, the electric field from the gate converges around the sharp source corner marked by an X in Figure 1.This increases the potential in Roffset as compared to Rnonoffset for any given bias (until potential saturates due to electron inversion).Figure 2b shows the surface potential at Vgs = 0 V.It can be seen that, because the electric field converges around the sharp source corner [6], the potential in Roffset has increased.Since the potential is higher in Roffset as compared to Rnonoffset, the threshold voltage for BTBT in Roffset (Vth_Roffset) is lower than the threshold voltage for BTBT in Rnonoffset (Vth_Rnonoffset).
Figures 3a,b show the tunneling rate (Gtun) contour plot and Gtun, respectively, at Vgs = 0.21 V which is the bias needed to generate Ids = 10 −13 A (from Figure 2a).It is obvious from Figure 3 that the BTBT only takes place in Roffset, whereas Rnonoffset is completely switched off. Figure 4a shows Gtun at several Vgs values.From Figure 4a, Vth_Roffset and Vth_Rnonoffset can be found to be around Vgs = 0.17 V and 0.24 V, respectively.Figure 4b shows the Gtun contour plot at Vgs = Vth_Rnonoffset = 0.24 V. Figure 4a shows that Gtun in Rnonoffset just after it turns on, is always higher and has a much larger BTBT area (in Sentaurus technology-computer-aided-design tool (TCAD) was used as the simulator [7].The following models were used in the simulation: the dynamic nonlocal band-to-band-tunneling (BTBT) model, Fermi statistics, and the constant mobility model.The dynamic nonlocal BTBT model calculates BTBT in both lateral and 1D directions.Crystal orientation is assumed to be <100> in all devices.A constant electron effective tunneling mass of 0.19 m o was used in all simulations [8].All simulations were performed at a drain source bias V ds = 0.1 V unless otherwise specified.
For analysis to follow, drain-source current (I ds ) versus gate-source bias (V gs ) characteristics of the LTFET are shown in Figure 2a.There is a direct overlap between gate and source in R nonoffset , and the electric field in R nonoffset is in the 1D direction.In R offset , however, the electric field from the gate converges around the sharp source corner marked by an X in Figure 1.This increases the potential in R offset as compared to R nonoffset for any given bias (until potential saturates due to electron inversion).
Figure 2b shows the surface potential at V gs = 0 V.It can be seen that, because the electric field converges around the sharp source corner [6], the potential in R offset has increased.Since the potential is higher in R offset as compared to R nonoffset , the threshold voltage for BTBT in R offset (V th_Roffset ) is lower than the threshold voltage for BTBT in R nonoffset (V th_Rnonoffset ).
Figure 3a,b show the tunneling rate (G tun ) contour plot and G tun , respectively, at V gs = 0.21 V which is the bias needed to generate I ds = 10 −13 A (from Figure 2a).It is obvious from Figure 3 that the BTBT only takes place in R offset , whereas R nonoffset is completely switched off. Figure 4a shows G tun at several V gs values.From Figure 4a, V th_Roffset and V th_Rnonoffset can be found to be around V gs = 0.17 V and 0.24 V, respectively.Figure 4b shows the G tun contour plot at V gs = V th_Rnonoffset = 0.24 V. Figure 4a shows that G tun in R nonoffset just after it turns on, is always higher and has a much larger BTBT area (in the y direction) as compared to R offset .Thus, whenever R nonoffset turns on, it dominates over R offset .The reason why G tun is higher in R nonoffset is simply because the BTBT paths in R offset are laterally oriented or 2D from source to the surface in R offset , whereas the BTBT paths in R nonoffset are 1D.The 2D BTBT paths being naturally longer than the 1D paths result in a lower G tun in R offset .
0.00 0.01 0.02 0.03 0.04 0.05 0.28 0.32 0.36  From Figure 4a, it can be observed that, for a large part of the subthreshold region (Vgs < 0.24 V), only Roffset with the longer 2D BTBT paths and lower Gtun is contributing to the BTBT current and the more efficient Rnonoffset makes no contribution to the current.In other words, the LTFET underperforms in the subthreshold region.If Rnonoffset could be forced to turn on at a lower bias than Roffset, which is the condition Vth_Rnonoffset < Vth_Roffset, Rnonoffset will turn on in the subthreshold region, and with the condition Gtun in Rnonoffset > Gtun in Roffset, demonstrated in Figure 4a, a significant improvement in SS could be expected.
In other words, the Rnonoffset could be regarded as a parasitic region with a parasitic, fringing capacitance originating from the bottom of the gate to the sharp source corner.Since the potential is different in this area (Figure 2b), the capacitance associated with this region is different from the Rnonoffset region.If Vth_Rnonoffset < Vth_Roffset could be achieved, as is demonstrated below, the effect of this parasitic capacitance could be practically eliminated, and this is the purpose of the device proposed below.Since drain is not in close proximity to Roffset/Rnonoffset, where the BTBT current is generated, gate-drain capacitance fringing capacitance is not expected to influence the potential and BTBT significantly at high frequency.
0.00 0.01 0.02 0.03 0.04 0.05 0.28 0.32 0.36 From Figure 4a, it can be observed that, for a large part of the subthreshold region (Vgs < 0.24 V), only Roffset with the longer 2D BTBT paths and lower Gtun is contributing to the BTBT current and the more efficient Rnonoffset makes no contribution to the current.In other words, the LTFET underperforms in the subthreshold region.If Rnonoffset could be forced to turn on at a lower bias than Roffset, which is the condition Vth_Rnonoffset < Vth_Roffset, Rnonoffset will turn on in the subthreshold region, and with the condition Gtun in Rnonoffset > Gtun in Roffset, demonstrated in Figure 4a, a significant improvement in SS could be expected.
In other words, the Rnonoffset could be regarded as a parasitic region with a parasitic, fringing capacitance originating from the bottom of the gate to the sharp source corner.Since the potential is different in this area (Figure 2b), the capacitance associated with this region is different from the Rnonoffset region.If Vth_Rnonoffset < Vth_Roffset could be achieved, as is demonstrated below, the effect of this parasitic capacitance could be practically eliminated, and this is the purpose of the device proposed below.Since drain is not in close proximity to Roffset/Rnonoffset, where the BTBT current is generated, gate-drain capacitance fringing capacitance is not expected to influence the potential and BTBT significantly at high frequency.From Figure 4a, it can be observed that, for a large part of the subthreshold region (V gs < 0.24 V), only R offset with the longer 2D BTBT paths and lower G tun is contributing to the BTBT current and the more efficient R nonoffset makes no contribution to the current.In other words, the LTFET underperforms in the subthreshold region.If R nonoffset could be forced to turn on at a lower bias than R offset , which is the condition V th_Rnonoffset < V th_Roffset , R nonoffset will turn on in the subthreshold region, and with the condition G tun in R nonoffset > G tun in R offset , demonstrated in Figure 4a, a significant improvement in SS could be expected.
In other words, the R nonoffset could be regarded as a parasitic region with a parasitic, fringing capacitance originating from the bottom of the gate to the sharp source corner.Since the potential is different in this area (Figure 2b), the capacitance associated with this region is different from the R nonoffset region.If V th_Rnonoffset < V th_Roffset could be achieved, as is demonstrated below, the effect of this parasitic capacitance could be practically eliminated, and this is the purpose of the device proposed below.Since drain is not in close proximity to R offset /R nonoffset , where the BTBT current is generated, gate-drain capacitance fringing capacitance is not expected to influence the potential and BTBT significantly at high frequency.V gs =0.17 V

The DG-LTFET: Basic Device Physics
In order to achieve the condition Vth_Rnonoffset < Vth_Roffset, the DG-LTFET is presented in Figure 5a.DG-LTFET uses dual material gates denoted by gate1 and gate2, each with a different workfunction (Wrk_gate1/2) and height (Hg1/2).Hg1 = Hnonoffset = Hs = 40 nm, Hoffset = 10 nm, Hg2 = Hnonoffset − Hg1 + (Hoffset − tox) = 8 nm, and Tj = 5 nm.Wrk_gate1 is always lower than Wrk_gate2.Wrk_gate2 is fixed at Wrk_LTFET = 4.72 eV for all DG-LTFET considered in this work.The DG-LTFET process-flow is indicated in Figure 5a.The process-flow is based on the LTFET process-flow [3].The DG-LTFET process-flow follows the LTFET process-flow until the chemical vapor deposition (CVD) of gate2 (similar to the gate deposition in the LTFET).After this, two additional steps are required.The device is masked to protect the gate oxide and channel areas, and gate2 is selectively etched according to the desired height.Gate1 is then deposited in the recess created by gate2-etching by a low-temperature atomic layer deposition process.Similar dual-material gate structures have been extensively reported in the literature including [9][10][11].

The DG-LTFET: Basic Device Physics
In order to achieve the condition V th_Rnonoffset < V th_Roffset , the DG-LTFET is presented in Figure 5a.DG-LTFET uses dual material gates denoted by gate1 and gate2, each with a different workfunction (W rk_gate1/2 ) and height (H g1/2 ).H g1 = H nonoffset = H s = 40 nm, H offset = 10 nm, H g2 = H nonoffset − H g1 + (H offset − t ox ) = 8 nm, and T j = 5 nm.W rk_gate1 is always lower than W rk_gate2 .W rk_gate2 is fixed at W rk_LTFET = 4.72 eV for all DG-LTFET considered in this work.The DG-LTFET process-flow is indicated in Figure 5a.The process-flow is based on the LTFET process-flow [3].The DG-LTFET process-flow follows the LTFET process-flow until the chemical vapor deposition (CVD) of gate2 (similar to the gate deposition in the LTFET).After this, two additional steps are required.The device is masked to protect the gate oxide and channel areas, and gate2 is selectively etched according to the desired height.Gate1 is then deposited in the recess created by gate2-etching by a low-temperature atomic layer deposition process.Similar dual-material gate structures have been extensively reported in the literature including [9][10][11].V gs =0.17 V

The DG-LTFET: Basic Device Physics
In order to achieve the condition Vth_Rnonoffset < Vth_Roffset, the DG-LTFET is presented in Figure 5a.DG-LTFET uses dual material gates denoted by gate1 and gate2, each with a different workfunction (Wrk_gate1/2) and height (Hg1/2).Hg1 = Hnonoffset = Hs = 40 nm, Hoffset = 10 nm, Hg2 = Hnonoffset − Hg1 + (Hoffset − tox) = 8 nm, and Tj = 5 nm.Wrk_gate1 is always lower than Wrk_gate2.Wrk_gate2 is fixed at Wrk_LTFET = 4.72 eV for all DG-LTFET considered in this work.The DG-LTFET process-flow is indicated in Figure 5a.The process-flow is based on the LTFET process-flow [3].The DG-LTFET process-flow follows the LTFET process-flow until the chemical vapor deposition (CVD) of gate2 (similar to the gate deposition in the LTFET).After this, two additional steps are required.The device is masked to protect the gate oxide and channel areas, and gate2 is selectively etched according to the desired height.Gate1 is then deposited in the recess created by gate2-etching by a low-temperature atomic layer deposition process.Similar dual-material gate structures have been extensively reported in the literature including [9][10][11].Lower W rk_gate1 results in an increased flatband voltage [12] (V fb ) in R nonoffset as compared to R offset .Figure 5b shows V fb of DG-LTFET (red symbols) with W rk_gate1 = 4.5 eV and W rk_gate2 = W rk_LTFET .Also shown for the reference is V fb of the LTFET (blue symbols).Expectedly, the DG-LTFET potential increases in R nonoffset .The potential does not change abruptly from gate1 to gate2 because of the presence of 2D effects around the source corner.Electric field from the bottom of gate2 converges around the source corner.Around the middle of R offset , equilibrium is established between the two gates and DG-LTFET potential overlaps LTFET potential since W rk_gate2 = W rk_LTFET .With W rk_gate1 < W rk_gate2 , the increased potential in R nonoffset reduces V th_Rnonoffset .If W rk_gate1/2 are appropriately tuned with W rk_gate1 < W rk_gate2 , the condition V th_Rnonoffset < V th_Roffset = 0.17 V can be achieved.Because W rk_gate2 = W rk_LTFET = 4.72 eV, V th_Roffset (in the DG-LTFET) is equal to V th_Roffset (in the LTFET).
Figure 6a-c show I ds -V gs characteristics at different W rk_gate1 , SS, and I ON /I OFF of the DG-LTFET with constant W rk_gate2 = W rk_LTFET = 4.72 eV for all DG-LTFET, respectively.Also shown for the reference is the I ds -V gs characteristics of the LTFET (black squares).I ON is extracted at V gs = 0.7 V, and I OFF is defined as I ds = 10 −17 A. With W rk_gate1 = 4.675 eV (red circles), the V th_Rnonoffset is reduced to 0.189 V. Compared with the LTFET, R nonoffset now turns on earlier in the subthreshold region, along with R offset .Since the BTBT is more efficient in R nonoffset (Figure 4a) as compared to R offset , I ds increases more rapidly within the subthreshold region.
Hence, just at the transition point, where R nonoffset turns on (V gs ~0.189), a kink appears in the I ds -V gs curve.With W rk_gate1 = 4.65 eV (green triangles), V th_Rnonoffset is reduced to V gs = 0.167 V and the condition V th_Rnonoffset < V th_Roffset is achieved, and DG-LTFET exhibits a remarkable SS with values less than 10 mV/dec as seen in Figure 6b.With W rk_gate1 = 4.625 eV (blue stars), V th_Rnonoffset reduces further to 0.1448 V, which is < V th_Roffset .If V th_Rnonoffset < V th_Roffset is established, then any increase in V th_Roffset − V th_Rnonoffset simply shifts the I ds -V gs to the left without any change in SS as shown by the blue stars (W rk_gate1 = 4.625 eV) and orange diamonds (W rk_gate1 = 4.5 eV) in Figure 6a,b, respectively.An improvement of ~16% is observed in the I ON /I OFF of the DG-LTFET (with W rk_gate1 = 4.625 eV) over the LTFET.
Figure 7a shows the G tun contour plot of DG-LTFET at a V gs (= 0.172 V) bias needed to achieve an equivalent I ds of 10 −13 A in DG-LTFET with W rk_gate1 = 4.65 eV. Figure 7b shows the contour plot extracted from Figure 7a.For reference, Figure 7b also shows that G tun needed to generate an equivalent amount of I ds in the LTFET (at a V gs bias of 0.21 V, Figure 3b).As can be seen in Figure 7b, the LTFET needs contribution only from R offset , but generating the same amount of I ds DG-LTFET depends heavily on R nonoffset with some contribution from R offset .Because G tun in R nonoffset is more efficient (Figure 4a), as the V gs bias increases, G tun increases exponentially in a much larger area in R nonoffset , which results in the DG-LTFET exhibiting a much steeper subthreshold swing, while the LTFET continues to depend only on the inefficient BTBT in R offset until around V th_Rnonoffset = 0.24 V.

Device Optimization
To optimize device performance, the impact of variations in key parameters including Hg1/2, Hs/Tj, and Nd was investigated.

Device Optimization
To optimize device performance, the impact of variations in key parameters including H g1/2 , H s /T j , and N d was investigated.To investigate the impact of H g1/2 values, I ds -V gs characteristics for the DG-LTFET at different H g1 and H g2 = H nonoffset − H g1 + (H offset − t ox ) with fixed W rk_gate1 = 4.5 eV and W rk_gate2 = W rk_LTFET , H s = H nonoffset = 40 nm, H offset = 10 nm, and T j = 5 nm is presented in Figure 8.It can be seen that I ds is independent of H g1/2 .

Device Optimization
To optimize device performance, the impact of variations in key parameters including Hg1/2, Hs/Tj, and Nd was investigated.
H g1 = 35 nm, H g2 = 13 nm H g1 = 37 nm, H g2 = 11 nm Next, to investigate the effect of T j on device performance, I ds -V gs characteristics, SS, and I ON /I OFF of DG-LTFET are presented for different T j with fixed W rk_gate1 = 4.5 eV and W rk_gate2 = W rk_LTFET , H g1 = H nonoffset = 40 nm, H offset = 10 nm, and H g2 = H nonoffset − H g1 + (H offset − t ox ) = 8 nm in Figure 9a-c, respectively.It was found that the increasing T j results in a degradation of the I ON /I OFF ratio.It is simply because of the increase in BTBT path length with the increase in T j .The T j of 5 nm was found to be optimum in this work as any further reduction will bring significant quantum confinement effect into play, which is well known to degrade device performance [4,5,[13][14][15].Hnonoffset = 40 nm, Hoffset = 10 nm. and Hg2 = Hnonoffset − Hg1 + (Hoffset − tox) = 8 nm in Figure 9a-c, respectively.It was found that the increasing Tj results in a degradation of the ION/IOFF ratio.It is simply because of the increase in BTBT path length with the increase in Tj.The Tj of 5 nm was found to be optimum in this work as any further reduction will bring significant quantum confinement effect into play, which is well known to degrade device performance [4,5,[13][14][15].Next, the impact of varying H s was investigated.I ds -V gs characteristics of the DG-LTFET for several H s with fixed W rk_gate1 = 4.5 eV and W rk_gate2 = W rk_LTFET , H g1 = H s = H nonoffset , H g2 = H nonoffset − H g1 + (H offset − t ox ) = 8 nm, and T j = 5 nm is presented in Figure 10.By maintaining H g1 = H s , H offset = 10 nm, and H g2 = 8 nm, the electric field vector distribution within the DG-LTFET remains the same as H s is varied, and the BTBT area simply scales with H s .An increase (decrease) in the BTBT area with H s simply results in an increased (decreased) I ON /I OFF ratio as shown in Figure 10b with no change in SS, as evident from Figure 10a.
Finally, the ambipolar current of the DG-LTFET is discussed.Ambipolar I ds of TFET depends on the drain-channel junction.In the DG-LTFET, the drain-channel junction is controlled by gate2 with W rk_gate2 = W rk_LTFET .With the same workfunction, the electrostatics of the drain-channel junction in the DG-LTFET is exactly the same as that in the LTFET.Figure 11a shows ambipolar I ds of the DG-LTFET compared with the LTFET.Any change in W rk_gate1 in the DG-LTFET does not affect the drain-channel junction.The same argument applies for any other design parameter variation in DG-LTFET including H s , H g1/2 , and T j ; that is, as long as the electrostatics of the drain-channel junction remains unaffected, the DG-LTFET will exhibit an equivalent ambipolar I ds as the LTFET.Further, the impact of N d on ambipolar I ds was considered.Different N d values were considered for a DG-LTFET with W rk_gate1 = 4.5 eV and W rk_gate2 = W rk_LTFET , H g1 = H nonoffset = 40 nm, H g2 = H offset − t ox = 8 nm, and T j = 5 nm, and the results are shown in Figure 11b.A drain doping level of 10 18 cm −3 was found to suppress ambipolar I ds appreciably without affecting the I ON .
Next, the impact of varying Hs was investigated.Ids-Vgs characteristics of the DG-LTFET for several Hs with fixed Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET, Hg1 = Hs = Hnonoffset, Hg2 = Hnonoffset − Hg1 + (Hoffset − tox) = 8 nm, and Tj = 5 nm is presented in Figure 10.By maintaining Hg1 = Hs, Hoffset = 10 nm, and Hg2 = 8 nm, the electric field vector distribution within the DG-LTFET remains the same as Hs is varied, and the BTBT area simply scales with Hs.An increase (decrease) in the BTBT area with Hs simply results in an increased (decreased) ION/IOFF ratio as shown in Figure 10b with no change in SS, as evident from Figure 10a.
Finally, the ambipolar current of the DG-LTFET is discussed.Ambipolar Ids of TFET depends on the drain-channel junction.In the DG-LTFET, the drain-channel junction is controlled by gate2 with Wrk_gate2 = Wrk_LTFET.With the same workfunction, the electrostatics of the drain-channel junction in the DG-LTFET is exactly the same as that in the LTFET.Figure 11a shows ambipolar Ids of the DG-LTFET compared with the LTFET.Any change in Wrk_gate1 in the DG-LTFET does not affect the drain-channel junction.The same argument applies for any other design parameter variation in DG-LTFET including Hs, Hg1/2, and Tj; that is, as long as the electrostatics of the drain-channel junction remains unaffected, the DG-LTFET will exhibit an equivalent ambipolar Ids as the LTFET.Further, the impact of Nd on ambipolar Ids was considered.Different Nd values were considered for a DG-LTFET with Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET, Hg1 = Hnonoffset = 40 nm, Hg2 = Hoffset − tox = 8 nm, and Tj = 5 nm, and the results are shown in Figure 11b.A drain doping level of 10 18 cm −3 was found to suppress ambipolar Ids appreciably without affecting the ION.

Conclusions
The device physics of the LTFET was investigated.It was found that a large part of the subthreshold region is dominated by the parasitic, lateral, 2D BTBT from the source to R offset with a lower G tun .The more efficient 1D BTBT from the source to R nonoffset , with a higher G tun takes place at a higher bias in the subthreshold region.In other words, the condition, that is, V th_Rnonoffset > V th_Roffset , exists in the LTFET.With R nonoffset not conducting the device does not utilize its channel fully during the subthreshold region.A new type of device based on the LTFET was introduced in this work.The device uses a dual gate structure with W rk_gate1 < W rk_gate2 .This increases the potential in R nonoffset and lowers V th_Rnonoffset .The DG-LTFET reverses the threshold condition of the LTFET, that is, it lowers V th_Rnonoffset and makes it <V th_Roffset .R nonoffset with higher G tun turns on earlier than R offset in the subthreshold region in the DG-LTFET and the device exhibits an SS of less than 10 mV/dec.It was found that W rk_gate1 in the DG-LTFET needs to be sufficiently less than W rk_gate2 to achieve the sub 10 mv/dec SS.It was found that I ds and SS are independent of H g1/2 .The DG-LTFET was further evaluated for different device dimensions including T j and H s while maintaining the electric field vector distribution equivalent.I ds decreases with an increase in T j and scales with H s .The N d value of 10 18 cm −3 was found to appreciably reduce ambipolar I ds .With the results presented in this work, the DG-LTFET could be considered as a viable potential replacement to conventional MOSFET and 3D integrations [16].

Figure 2 .
Figure 2. (a) Ids-Vgs transfer characteristics of the LTFET.Vth_Rnonoffset = 0.24 V and Vth_Roffset = 0.17 V. (b) Potential along the cutline shown in the inset at Vgs = 0 V. Potential is higher in Roffset.

Figure 2 .
Figure 2. (a) I ds -V gs transfer characteristics of the LTFET.V th_Rnonoffset = 0.24 V and V th_Roffset = 0.17 V. (b) Potential along the cutline shown in the inset at V gs = 0 V. Potential is higher in R offset .

Figure 3 .
Figure 3. (a) G tun contour plot at V gs = 0.21 V, which is the bias needed to generate I ds = 10 −13 A and (b) G tun extracted from (a).

Figure 4 .
Figure 4. (a) G tun at different V gs .(a) V th_Rnonoffset = 0.24 V and V th_Roffset = 0.17 V. (b) G tun contour plot at V gs = V th_Rnonoverlap = 0.24 V.In (b), yellow arrow indicates the height of R nonoffset .

Figure 5 .
Figure 5. (a) Schematic of DG-LTFET with process-flow indicated alongside and (b) V fb of DG-LTFET (red symbols) compared with that of the LTFET (blue symbols).In the DG-LTFET, W rk_gate1 = 4.5 eV and W rk_gate2 = W rk_LTFET = 4.72 eV were used.

c)Figure 6 .
Figure 6.(a) I ds -V gs characteristics of DG-LTFET with different W rk_gate1 s and fixed W rk_gate2 = W rk_LTFET .Also shown are I ds -V gs characteristics of the LTFET (black squares).(b) SS extracted from I ds -V gs characteristics in Figure 8a.(c) I ON /I OFF ratio extracted from I ds -V gs characteristics in Figure 8a.Red circles: W rk_gate1 = 4.675 eV; green triangles: W rk_gate1 = 4.65 eV; blue stars: W rk_gate1 = 4.625 eV; orange diamonds: W rk_gate1 = 4.5 eV.

Figure 7 .
Figure 7. (a) G tun contour plot of DG-LTFET at V gs = 0.172 V, which is needed to generate I ds = 10 −13 A and (b) G tun extracted from (a) (red symbols).Also shown for reference is G tun (blue symbols) of the LTFET at a V gs bias needed to generate I ds = 10 −13 A. In (a), yellow arrow indicates the height of R nonoffset .

10 SSFigure 9 .
Figure 9. (a) I ds -V gs characteristics of the DG-LTFET with different T j and fixed W rk_gate1 = 4.5 eV, W rk_gate2 = W rk_LTFET , and H g1 = H s = H nonoffset = 40 nm, H g2 = H offset (10 nm) − t ox = 8 nm.(b) The SS of I ds -V gs shown in Figure 8a.(c) I ON /I OFF ratio of I ds -V gs characteristics shown in Figure 8a.Red squares, green circles, and blue triangles: T j = 5, 6 and 7 nm, respectively.
Roffset.Thus, whenever Rnonoffset turns on, it dominates over Roffset.The reason why Gtun is higher in Rnonoffset is simply because the BTBT paths in Roffset are laterally oriented or 2D from source to the surface in Roffset, whereas the BTBT paths in Rnonoffset are 1D.The 2D BTBT paths being naturally longer than the 1D paths result in a lower Gtun in Roffset.