Search Results (317)

This paper presents the first hybrid supply modulator (HSM) designed for envelope tracking power amplifiers (ET-PAs) in base station applications. The focus is on a rail-to-rail Class-AB linear amplifier (LA) optimized for high-voltage and wide-bandwidth operation. The LA is designed using 130 nm BCD technology, utilizing Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors for high-voltage operation and incorporating shielding MOSFETs to protect the low-voltage devices. The circuit utilizes dual power supply domains (5 V and 30 V) to improve power efficiency. The proposed LA achieves a bandwidth of 100 MHz and a slew rate of +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, with a quiescent power consumption of 0.89 W. Transient simulations using a 50 MHz bandwidth 5G NR envelope input demonstrate that the proposed HSM achieves a power efficiency of 83%. Consequently, the proposed HSM supports high-output (100 W) wideband 5G NR transmission with enhanced efficiency. Full article

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness. Full article

Terahertz (THz) frequencies, spanning from 0.1 to 1 THz, are poised to play a pivotal role in the development of future 6G wireless communication systems. These systems aim to utilize photonic technologies to enable ultra-high data rates—on the order of terabits per second—while maintaining low latency and high efficiency. In this work, we present a novel photonic method for generating sub-THz vector signals within the THz band, employing a semiconductor optical amplifier (SOA) and phase modulator (PM) to create an optical frequency comb, combined with in-phase and quadrature (IQ) modulation techniques. We demonstrate, both through simulation and experimental setup, the generation and successful transmission of a 0.1 THz vector. The process involves driving the PM with a 12.5 GHz radio frequency signal to produce the optical comb; then, heterodyne beating in a uni-traveling carrier photodiode (UTC-PD) generates the 0.1 THz radio frequency signal. This signal is transmitted over distances of up to 30 km using single-mode fiber. The resulting 0.1 THz electrical vector signal, modulated with quadrature phase shift keying (QPSK), achieves a bit error ratio (BER) below the hard-decision forward error correction (HD-FEC) threshold of ${3.8 \times 10}^{-3}$. To the best of our knowledge, this is the first experimental demonstration of a 0.1 THz photonic vector THz wave based on an SOA and a simple PM-driven optical frequency comb. Full article

Encryption and decryption are essential components in signal processing and optical communication systems, providing data confidentiality, integrity, and secure high-speed transmission. We present a novel design and simulation of an all-optical encryption and decryption system operating at 120 Gb/s using carrier reservoir semiconductor optical amplifiers (CR-SOAs) embedded in Mach–Zehnder interferometers (MZIs). The architecture relies on two consecutive exclusive-OR (XOR) logic gates, implemented through phase-sensitive interference in the CR-SOA-MZI structure. The first XOR gate performs encryption by combining the input data signal with a secure optical key, while the second gate decrypts the encoded signal using the same key. The fast gain recovery and efficient carrier dynamics of CR-SOAs enable a high-speed, low-latency operation suitable for modern photonic networks. The system is modeled and simulated using Mathematica Wolfram, and the output quality factors of the encrypted and decrypted signals are found to be 28.57 and 14.48, respectively, confirming excellent signal integrity and logic performance. The influence of key operating parameters, including the impact of amplified spontaneous emission noise, on system behavior is also examined. This work highlights the potential of CR-SOA-MZI-based designs for scalable, ultrafast, and energy-efficient all-optical security applications. Full article

In recent years, advancements in semiconductor technologies have significantly transformed Radio Frequency Power Amplifiers (RFPAs), enhancing their efficiency, size, and performance. Despite these advancements, the design of RFPAs remains intrinsically linked to the specific applications for which they are intended. What proves effective in one context, such as communication technologies, may not be equally suitable in others, such as scientific instruments. This discrepancy highlights the lack of a systematic approach to RFPA design that can be applied across different applications. This paper delves into the fundamental concepts of RFPA design, adopting a comprehensive perspective. It further introduces an alternative categorization of RFPAs, thereby providing a generalized design approach. Full article

In this paper, a high-voltage chopper and ping-pong auto-zeroing operational amplifier was designed for industrial and automotive applications. Based on chopper stabilization, the proposed circuit introduces a novel chopper switch control signal that varies with the input common-mode voltage. This scheme effectively suppresses the reference offset caused by the chopper switches and prevents transistor breakdown under high-voltage conditions. Additionally, the ping-pong auto-zero structure was optimized by employing a six-channel parallel first-stage amplifier, which further reduced the charge injection and ripple introduced by the chopper switches. The amplifier was implemented using an SMIC (Semiconductor Manufacturing International Corporation) 180 nm 1P5M BCD (Bipolar-CMOS-DMOS) process with a chip area of 4.211 mm². The post-layout simulation results show that, under a 55 V supply, the amplifier achieves an input-referred noise Power Spectral Density (PSD) of 6.2 $\mathrm{nV}/\sqrt{\mathrm{Hz}}$ and an input offset voltage of 32 $\mu \mathrm{V}$, while the output voltage swings from 0.2 V to 53.4 V with a unity gain bandwidth of 3.2 MHz, which meets the requirements for high-voltage, high-resolution signal processing. Full article

In this paper, we present a directly modulated laser (DML) using a partially corrugated grating (PCG) and integrated with a semiconductor optical amplifier (SOA). The influence of the quasi-high-pass filter properties of the SOA on the bandwidth was explored, resulting in high optical power output at lower current levels, with a bandwidth surpassing 25 GHz and an output power above 25 mW. The PCG design boosts the lasing mode’s resistance to random phase fluctuations at the rear facet, hence boosting the mode stability of the laser with a side-mode suppression ratio (SMSR) of over 44 dB. Furthermore, we performed back-to-back (BTB) 26.5625 Gbps NRZ data transmission experiments at room temperature (25 °C) with a modulation current of 60 mA. The results reveal that the transmitter and dispersion eye closure (TDEC) of the fabricated DML is lower than that of a conventional laser when the SOA area current reaches a specific threshold, demonstrating the enhanced signal transmission capabilities of our design. This laser structure offers a fresh strategy for the development of high-power, high-speed DMLs. Full article

All-optical encoders and comparators are essential components for high-speed optical computing, enabling ultra-fast data processing with minimal latency and low power consumption. This paper presents a numerical analysis of an all-optical encoder and comparator architecture operating at 120 Gb/s, based on carrier reservoir semiconductor optical amplifier-assisted Mach–Zehnder interferometers (CR-SOA-MZIs). Building upon our previous work on all-optical arithmetic circuits, this study extends the application of CR-SOA-MZI structures to implement five key logic operations between two input signals (A and B): $\overline{\mathrm{A}}\mathrm{B}$, $\mathrm{A}\overline{\mathrm{B}}$, AB (AND), $\overline{\mathrm{A}}\hspace{0.17em}\overline{\mathrm{B}}$ (NOR), and AB + $\overline{\mathrm{A}}\hspace{0.17em}\overline{\mathrm{B}}$ (XNOR). The performance of these logic gates is evaluated using the quality factor (QF), yielding values of 17.56, 17.04, 19.05, 10.95, and 8.33, respectively. We investigate the impact of critical design parameters on the accuracy and stability of the logic outputs, confirming the feasibility of high-speed operation with robust signal integrity. These results support the viability of CR-SOA-MZI-based configurations for future all-optical logic circuits, offering promising potential for advanced optical computing and next-generation photonic information processing systems. Full article

GaN High-Electron-Mobility Transistors have gained some foothold in the power-electronics industry. This is due to wide frequency bandwidth and power handling. Gallium Nitride offers a wide bandgap and higher critical field strength compared to most wide-bandgap semiconductors, resulting in better radiation resistance. Theoretically, it supports higher speeds as the device dimensions could be reduced without suffering voltage breakdown. The simulation and experimental results illustrate the superior performance of the Gallium Nitride High-Electron-Mobility Transistors in an amplifying circuit. Using a spice model for commercially available Gallium Nitride High-Electron-Mobility Transistors, non-distorted output to an input signal of 200 ps was displayed. Real-world measurements underscore the fast response of the Gallium Nitride High-Electron-Mobility Transistors with its measured slew rate at approximately 3000 V/μs, a result only 17% lower than the result obtained from the simulation. This fast response, coupled with the amplifier radiation resistance, shows promise for designing improved detection and imaging circuits with long Mean Time Between Failure required, for example, by next-generation industrial-process gamma transmission-computed tomography. Full article

This paper presents a multiple-input single-output (MISO) shadow filter implemented using multiple-input differential difference transconductance amplifiers (MI-DDTAs). The MI-DDTA’s multiple inputs are realized through the multiple-input bulk-driven MOS transistor (MI-BD MOST) technique. Leveraging the multiple-input capability of the DDTA, various filter responses—low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), band-stop filter (BSF), and all-pass filter (APF)—can be efficiently achieved by appropriately configuring the input signals. The natural frequency and quality factor of the shadow filter can be independently tuned using external amplifiers. Unlike conventional shadow filters, where adjusting the quality factor or natural frequency impacts the passband gain, this design ensures a constant unity passband gain. The MI-DDTA operates at a supply voltage of 0.5 V and consumes 385.8 nW of power for setting current I_set = 14 nA. The proposed MI-DDTA and shadow filter are designed and validated through simulations in the Cadence design environment, using a 0.18 µm CMOS process provided by TSMC (Taiwan Semiconductor Manufacturing Company Limited). Full article

Lithography is crucial to semiconductor manufacturing, enabling the production of smaller, more powerful electronic devices. This review explores the evolution, principles, and advancements of key lithography techniques, including extreme ultraviolet (EUV) lithography, electron beam lithography (EBL), X-ray lithography (XRL), ion beam lithography (IBL), and nanoimprint lithography (NIL). Each method is analyzed based on its working principles, resolution, resist materials, and applications. EUV lithography, with sub-10 nm resolution, is vital for extending Moore’s Law, leveraging high-NA optics and chemically amplified resists. EBL and IBL enable high-precision maskless patterning for prototyping but suffer from low throughput. XRL, using synchrotron radiation, achieves deep, high-resolution features, while NIL provides a cost-effective, high-throughput method for replicating nanostructures. Alignment marks play a key role in precise layer-to-layer registration, with innovations enhancing accuracy in advanced systems. The mask fabrication process is also examined, highlighting materials like molybdenum silicide for EUV and defect mitigation strategies such as automated inspection and repair. Despite challenges in resolution, defect control, and material innovation, lithography remains indispensable in semiconductor scaling, supporting applications in integrated circuits, photonics, and MEMS/NEMS devices. Various molecular strategies, mechanisms, and molecular dynamic simulations to overcome the fundamental lithographic limits are also highlighted in detail. This review offers insights into lithography’s present and future, aiding researchers in nanoscale manufacturing advancements. Full article

With advances in space, nuclear, and defense industries, the susceptibility of semiconductor integrated circuits (ICs) to radiation has increased. Radiation-induced degradation and malfunctioning of IC performance can lead to system failure, leading to significant damage. To address this limitation, this study employed mixed-stage modeling and simulation (M&S) techniques to evaluate the reliability of complementary metal-oxide semiconductor application-specific ICs (ASICs) in radiation environments. Radiation-hardened IC chips were designed and fabricated using layout modification techniques based on M&S. The ASIC, which includes the D-latch and Operational Amplifier (Op-Amp) circuits, was validated for resistance up to a total ionizing dose of 20 kGy(Si). The proposed radiation-hardened ICs demonstrated stable performance even in radiation-exposed environments, ensuring reliable operation under such conditions. The findings provide insights into overcoming radiation-induced degradation and malfunction in semiconductor integrated circuits, which is particularly relevant for advancing space, nuclear, and defense industries. Full article

This paper reviews various design approaches for sensing schemes that utilize silicon nanowire (SiNW) ion-sensitive field-effect transistors (ISFETs) for pH-sensing applications. SiNW ISFETs offer advantageous characteristics, including a high surface-to-volume ratio, fast response time, and suitability for integration with complementary metal oxide semiconductor (CMOS) technology. This review focuses on SiNW ISFET-based biosensors in three key aspects: (1) major fabrication processes and device structures; (2) theoretical analysis of key performance parameters in readout circuits such as sensitivity, linearity, noise immunity, and output range in different system configurations; and (3) an overview of existing readout circuits with quantitative evaluations of N-type and P-type current-mirror-based circuits, highlighting their strengths and limitations. Finally, this paper proposes a modified N-type readout scheme integrating an operational amplifier with a negative feedback network to overcome the low sensitivity of conventional N-type circuits. This design enhances gain control, linearity, and noise immunity while maintaining stability. These advancements are expected to contribute to the advancement of the current state-of-the-art SiNW ISFET-based readout circuits. Full article

This paper presents a low-voltage, low-power current differencing transconductance amplifier (CDTA) utilizing the bulk-driven MOS transistor technique in the subthreshold region for reduced voltage and power consumption. The proposed CDTA includes a z-copy terminal, which enhances its functionality in current-mode circuit applications. Designed in the Cadence Virtuoso environment using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC), the amplifier operates with a supply voltage of 0.45 V and consumes 328 nW of power, with a bias current set to 10 nA. The current bandwidth and offset of the CDTA are 35 kHz and 0.3 nA, respectively. To demonstrate its performance, the CDTA is applied in a current-mode universal filter, which can realize low-pass, band-pass, high-pass, band-stop, and all-pass responses within a single topology. This design eliminates issues related to inverting input signals, input signal matching, or the need for multiple input signals. Additionally, the natural frequency of these filtering functions can be electronically controlled. The low-pass filter achieves a dynamic range of 61 dB, with a total harmonic distortion of 0.8%. Full article

The advent of CMOS power amplifiers has enabled compact and cost-effective solutions for RF applications. Among the available options, switching amplifiers are the most competitive due to their superior efficiency. In this paper, we present the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations that is compliant with the Bluetooth Low Energy (BLE) standard. The amplifier is based on a cascode configuration with charging acceleration capacitance and a combination of standard and high-voltage (HV) MOSFETs, ensuring optimal performance while maintaining device reliability. To identify the best configuration for the proposed circuit, we first provide an overview of basic class-E amplifier operations and critically review optimization techniques proposed in the scientific literature. This review is complemented by a numerical analysis of the potential advantages of using a combined standard-HV MOSFET structure. Post-layout simulations with parasitic parameter extraction demonstrated that the amplifier achieves 40.85% Power Added Efficiency and 20.52 dBm output power. Full article