Search Results (29)

In this study, we propose a bidirectional chemical sensor platform based on a reconfigurable ion-sensitive field-effect transistor (R-ISFET) architecture. The device incorporates Ni-silicide Schottky barrier source/drain (S/D) contacts, enabling ambipolar conduction and bidirectional turn-on behavior for both p-type and n-type configurations. Channel polarity is dynamically controlled via the program gate (PG), while the control gate (CG) suppresses leakage current, enhancing operational stability and energy efficiency. A dual-control-gate (DCG) structure enhances capacitive coupling, enabling sensitivity beyond the Nernst limit without external amplification. The extended-gate (EG) architecture physically separates the transistor and sensing regions, improving durability and long-term reliability. Electrical characteristics were evaluated through transfer and output curves, and carrier transport mechanisms were analyzed using band diagrams. Sensor performance—including sensitivity, hysteresis, and drift—was assessed under various pH conditions and external noise up to 5 V_pp (i.e., peak-to-peak voltage). The n-type configuration exhibited high mobility and fast response, while the p-type configuration demonstrated excellent noise immunity and low drift. Both modes showed consistent sensitivity trends, confirming the feasibility of complementary sensing. These results indicate that the proposed R-ISFET sensor enables selective mode switching for high sensitivity and robust operation, offering strong potential for next-generation biosensing and chemical detection. Full article

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics. Full article

Schottky barrier thin-film transistors (SBTFTs) are promising for low-power electronics due to advantages such as low saturation voltage and high stability. In this study, we developed a high-performance bilayer IGZO SBTFT by combining a 4.7 nm atomic layer deposition (ALD) IGZO layer with an 11.8 nm sputtering IGZO layer, using platinum (Pt) and molybdenum (Mo) electrodes. The device exhibits dual-mode operation. In Schottky barrier TFT (SB-TFT) mode (Pt as source), the bilayer structure reduces defect density, achieving a very low saturation voltage (~0.4 V), high field-effect mobility (up to 20 cm²/V·s), and enhanced stability under stress conditions, including positive/negative bias and negative illumination. In quasi-Ohmic TFT (QO-TFT) mode (Pt as drain), the device retains conventional saturation behavior in output characteristics while delivering similar mobility and robust stability. This work provides a novel bilayer SBTFT design with dual functionality, enabling a higher current drive, improved stability, and flexibility for energy-efficient applications. Full article

In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf_xTi_1−xO₂ in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM_H) and Noise Margin Low (NM_L), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities. Full article

As semiconductor technology and process nodes advance, three-dimensional devices like FinFET and NSFET are increasingly becoming the primary choice, replacing planar MOSFETs. However, the complex manufacturing processes and high process sensitivity of three-dimensional devices at advanced process nodes inevitably cause significant deviations from the ideal structure during actual fabrication, leading to notable changes in their electrical characteristics. This paper investigates the impact of source/drain region height fluctuations caused by etching and epitaxial growth variations on the electrical characteristics of FinFET and NSFET devices, as well as their related circuits. The electrical characteristics when height variations occur in single and multiple electrodes indicate that, although NSFET and FinFET generally exhibit similar properties such as a decrease in the ON-state current when the source/drain height is reduced, the independent nature of the nanosheets in NSFET and the unidirectional conduction of Schottky contact resistance cause significant differences in their electrical characteristics. Additionally, the related circuit-level simulations show that height fluctuations in the source/drain regions of devices can significantly impact circuit characteristics, including voltage and delay, and in severe cases, they may even lead to circuit failure. Full article

A silicon carbide (SiC) SGT MOSFET featuring a “一”-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Q_rr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage. Full article

Ultraviolet (UV) photodetectors are key devices required in the industrial, military, space, environmental, and biological fields. The Schottky barrier (SB)-MOSFET, with its high hole and electron barrier, and given its extremely low dark current, has broad development prospects in the optoelectronics field. We analyze the effects of trap states on the output characteristics of an inversion mode n-channel GaN SB-MOSFET using TCAD simulations. At the oxide/GaN interface below the gate, it was demonstrated that shallow donor-like traps were responsible for degrading the subthreshold swing (SS) and off-state current density (I_off), while deep donor-like traps below the Fermi energy level were insignificant. In addition, shallow acceptor-like traps shifted the threshold voltage (V_t) positively and deteriorated the SS and on-state current density (I_on), while deep acceptor-like traps acted on a fixed charge. The output characteristics of the GaN SB-MOSFET were related to the resistive GaN path and the tunneling rate due to the traps at the metal (source, drain)/GaN interface. For the UV responses, the main mechanism for the negative V_t shift and the increases in the I_on and spectral responsivity was related to the photo-gating effect caused by light-generated holes trapped in the shallow trap states. These results will provide insights for UV detection technology and for a high-performance monolithic integration of the GaN SB-MOSFET. Full article

This paper presents a novel approach to the efficient extraction of parasitic resistances in high electron mobility transistors (HEMTs). The study reveals that the gate resistance value can be accurately determined under specific forward gate bias conditions (V_g = 1.0 V), although the gate resistance value becomes unreliable beyond this threshold (V_g > 1.0 V) due to potential damage to the Schottky contact. Furthermore, by examining the characteristics of the device under a cold-FET bias condition (V_ds = 0 V), a linear correlation between the gate and drain current is identified, enabling an estimation of the interdependence between the drain and source resistance using the proposed method. The estimation of parasitic pad capacitance (C_pg and C_pd) from Dambrine’s model is refined by incorporating the depletion layer capacitance on the gate side during the pinch-off condition. To validate the accuracy of the extracted parasitic capacitance and resistance values obtained from the new method, small-signal modeling is performed on a diverse range of measured devices. Full article

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (V_TH) depended on the range of the gate stress voltage (V_G.stress) at room temperature. However, the positive shift of V_TH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of V_TH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (I_GD and I_GS) before and after the stress test. The difference between the gate–source current and the gate–drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected. Full article

Achieving low conduction loss and good channel mobility is crucial for SiC MOSFETs. However, basic planar SiC MOSFETs provide challenges due to their high density of interface traps and significant gate-to-drain capacitance. In order to enhance the reverse recovery property of the device, a Schottky barrier diode (SBD) was added to the source contact area, the top of the current spreading region, of a trench-etched double-diffused SiC MOS (TED MOS). Two types of SBD structures were optimized to improve the electrical properties using 3D simulation software, “TCAD Silvaco”. During reverse recovery simulation, the carriers of the device were withdrawn from the SBD, indicating that the new design was effective. It also showed that the recovery properties of the new design depended on temperature, carrier lifetime, and the work functions of metals. All the new designs were evaluated in various circumstances to determine the trend. Ultimately, in high-speed switching circuits, the SiC TED MOS with SBD structure efficiently boosted switching speed, while reducing switching loss. Full article

A novel Schottky barrier MOSFET with quad gate and with source engineering has been proposed in this work. A high-κ dielectric is used at the source side of the channel, while SiO₂ is used at the drain side of the channel. To improve the carrier mobility, a SiGe pocket region is created at the source side of the channel. Physical and electrical characteristics of the proposed device are compared with conventional double gate Schottky barrier MOSFET. It has been observed that the proposed device exhibits better performance, with a higher I_ON/I_OFF ratio and lower subthreshold slope. The high-κ dielectric, along with the SiGe pocket region, improves tunneling probability, while aluminum, along with SiO₂ at the drain side, broadens the drain/channel Schottky barrier and reduces the hole tunneling probability, resulting in a reduced OFF-state current. Further, the proposed device is used as a biosensor to detect both the charged and neutral biomolecules. Biosensors are made by creating a nanocavity in the dielectric region near the source end of the channel to capture biomolecules. Biomolecules such as streptavidin, biotin, APTES, cellulose and DNA have unique dielectric constants, which modulates the electrical parameters of the device. Different electrical parameters, viz., the electric field, surface potential and drain current, are analyzed for each biomolecule. It has been observed that drain current increases with the dielectric constant of the biomolecules. Furthermore, the sensitivity and selectivity of the proposed biosensors is better than that of conventional biosensors made using double gate Schottky barrier MOSFETs. Sensitivity is almost twice that of a conventional sensor, while selectivity is six to twelve times higher than a conventional one. Full article

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH₃COO⁻ and OH⁻) and cations (H⁺) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems. Full article

The flyback converter with its active cell balancing topology for charging lithium-based batteries in Electrical Vehicles (EV) have been adopted recently into the industry. Electrical Vehicle battery charging requires high current operation in continuous current mode and hence, the power loss on the Schottky diode rectifier on the secondary side determines the power conversion efficiency. The depletion mode (D-mode) GaN HEMT synchronous rectifier proposed in this paper has been used to replace the Schottky diode on the secondary side of the flyback converter in order to improve the power conversion efficiency. This synchronous rectifier regulates the forward voltage drop of an external switch to about 100 mV per ampere of current flow with no concern to threshold voltage. The first challenge of converting the D-mode GaN HEMT as a synchronous rectifier is that the normally-on device must be off when the primary side inductor of the flyback converter is initially charging the magnetic energy. That is, the rectifier must behave as the normally-off device during its initialization stage. The second challenge is that the D-mode GaN HEMT must switch off as soon as the secondary current becomes zero. The third challenge is posing a fast recovery feature to reduce the drain-source voltage rise on the primary side switch, which suffices to be the main reason as to why the D-mode GaN HEMT is used instead of MOS devices. The proposed depletion mode GaN HEMT synchronous rectifier is verified to be able to overcome all challenges and in result becomes a candidate for the synchronous rectifier. Full article

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (I_ON) of 76.07 μA/μm and ON-state to OFF-state current ratio (I_ON/I_OFF) of 7 × 10⁵, and those for NMOS are 48.57 μA/μm and 1 × 10⁶. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NM_H) of 0.17 V and for low (NM_L) of 0.43 V, with power consumption less than 0.9 μW at V_DD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated. Full article

This study proposes a bidirectional chemical sensor platform using ambipolar double-gate ion-sensitive field-effect transistors (ISFET) with microwave-assisted Ni-silicide Schottky-barrier (SB) source and drain (S/D) on a fully depleted silicon-on-insulator (FDSOI) substrate. The microwave-assisted Ni-silicide SB S/D offer bidirectional turn-on characteristics for both p- and n-type channel operations. The p- and n-type operations are characterized by high noise resistance as well as improved mobility and excellent drift performance, respectively. These features enable sensing regardless of the gate voltage polarity, thus contributing to the use of detection channels based on various target substances, such as cells, antigen-antibodies, DNA, and RNA. Additionally, the capacitive coupling effect existing between the top and bottom gates help achieve self-amplified pH sensitivity exceeding the Nernst limit of 59.14 mV/pH without any additional amplification circuitry. The ambipolar FET sensor performance was evaluated for bidirectional electrical characteristics, pH detection in the single-gate and double-gate modes, and reliability in continuous and repetitive operations. Considering the excellent characteristics confirmed through evaluation, the proposed ambipolar chemical sensor platform is expected to be applicable to various fields including biosensors. And through linkage with subsequent studies, various medical applications and precision detector operations for specific markers will be possible. Full article