Binary-Synaptic Plasticity in Ambipolar Ni-Silicide Schottky Barrier Poly-Si Thin Film Transistors Using Chitosan Electric Double Layer

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH3COO− and OH−) and cations (H+) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems.


Introduction
In recent times, artificial intelligence (AI) technology is being used in everyday life in various fields, such as autonomous cars, intelligent robots, and wearable smart devices [1][2][3]. Processing massive data from numerous variables is essential for AI technology. Although extensive data have been processed on the existing von Neumann-structured CPU chips, the serial method cause a bottleneck between the process and memory. Various attempts have been made to minimize this inefficiency of AI process-specialized circuits using graphics processing units, field-programmable gate arrays, and application-specific integrated circuits [4][5][6]. However, the von Neumann process structure has evident limitations. To overcome these limitations, neuromorphic semiconductors mimicking efficient information processing of the human brain are in the spotlight. The human brain processes extensive information more efficiently and quickly than any other system. Its super-parallel structure of approximately 100 billion neurons and 100 trillion synapses connects them in all directions. When we see, hear, feel, or think about something, neurons exchange information with other neurons by forming electrical spikes. Because of the parallel structure, the human brain processes information with an energy consumption of 20 W and has no bottleneck inefficiency [7,8]. In the early research, a two-terminal memristor attracted attention as a synaptic device with a structure and mechanism similar to these biological synapses. However, typical two-terminal memristors based on conducting filaments or phase change materials have the disadvantage of requiring high write/read currents due to the high conductance, resulting in excessive power loss as the array scale increases [9].

Device Fabrication
We fabricated the top-gate structure ambipolar chitosan synaptic transistor on a glass substrate with a 160-nm-thick ELA crystallized poly-Si film. For the channel layer (post-synapse), we defined the active channel area with width/length = 20/10 µm by photolithography; we wet etched it using silicon etchant. For NiSi S/D junctions, we deposited an 80-nm-thick Ni film with an E-beam evaporator. For the formation of NiSi, we performed the 2.45 GHz frequency of microwave annealing (MWA) process at 600 W (corresponding to approximately 400 • C thermal temperature [28,29]) in N 2 ambient air for 2 min. We removed unreacted Ni using a mixture of H 2 SO 4 :H 2 O 2 = 1:1. We formed the chitosan electrolyte EDL (neurotransmitter) using the following procedure. We prepared the chitosan electrolyte solution using a 2 wt% chitosan powder (deacetylation degree > 75%) dissolved in 2 wt% acetic acids; we spin-coated the chitosan EDL layer, dried it in ambient air for 24 h, and oven-baked it at 130 • C for 10 min. The thickness of the chitosan EDL was 130 nm (±5 nm deviation). Subsequently, we deposited a high-k Ta 2 O 5 dielectric layer with 80 nm thickness using RF magnetron sputtering as a chemical/mechanical reinforcing barrier layer of the organic chitosan electrolyte film. For the top-gate electrode (pre-synapse), we deposited a 150-nm-thick Al film using an e-beam evaporator and then formed it using a lift-off method. Finally, we opened the S/D contact hole for electrical measurement using a reactive ion etching process. Figure 1a shows a 300-times-magnified microscopic image of the ambipolar chitosan synaptic transistor with NiSi S/D, and Figure 1b shows the synaptic transistors array on an ELA glass substrate. Due to the Ta 2 O 5 barrier layer on the chitosan electrolyte, the ambipolar chitosan synaptic transistor could be patterned by photolithography.
130 nm (±5 nm deviation). Subsequently, we deposited a high-k Ta2O5 dielectric layer 80 nm thickness using RF magnetron sputtering as a chemical/mechanical reinforcing rier layer of the organic chitosan electrolyte film. For the top-gate electrode (pre-synap we deposited a 150-nm-thick Al film using an e-beam evaporator and then formed it u a lift-off method. Finally, we opened the S/D contact hole for electrical measurement u a reactive ion etching process. Figure 1a shows a 300-times-magnified microscopic im of the ambipolar chitosan synaptic transistor with NiSi S/D, and Figure 1b shows the aptic transistors array on an ELA glass substrate. Due to the Ta2O5 barrier layer on chitosan electrolyte, the ambipolar chitosan synaptic transistor could be patterned by p tolithography.

Characterization and Measurements
We analyzed the optical microscopic image of the fabricated ambipolar chitosan aptic transistor using an SV−55 Microscope System (SOMETECH, Seoul, Korea). We m ured the Fourier transform infrared (FT-IR) spectroscopy analysis of chitosan electro EDL film using IFS 66v/S and HYPERION 3000 ALPHA FT-IR microscope (Bruker Op Billerica, MA, USA). We measured the transfer, output characteristics, and synaptic havior using an Agilent 4156B Precision Semiconductor Parameter Analyzer (Hew Packard Co., Palo Alto, Santa Clara, CA, USA). To apply a pre-synapse spike, we app electrical pulses using Agilent 8110A Pulse Generator (Hewlett-Packard Co., Palo A USA). We evaluated the crystal structure of the microwave annealed NiSi film throug ray diffraction analysis using a SmartLab X-ray diffractometer (Rigaku Co., Tokyo, Jap

Device Structure of Ambipolar Chitosan Synaptic Transistor
Recent studies on synaptic transistors using chitosan electrolytes as EDL have stricted the options in the device fabrication process due to limitations of the mech cal/chemical weakness of the organic chitosan layer. Representatively, the patterning cess using a shadow mask that does not require additional etching and cleaning has b forced after the formation of the chitosan electrolyte layer [30][31][32][33][34]. However, through latest research, we secured the possibility of applying the lithography patterning pro

Characterization and Measurements
We analyzed the optical microscopic image of the fabricated ambipolar chitosan synaptic transistor using an SV−55 Microscope System (SOMETECH, Seoul, Korea). We measured the Fourier transform infrared (FT-IR) spectroscopy analysis of chitosan electrolyte EDL film using IFS 66v/S and HYPERION 3000 ALPHA FT-IR microscope (Bruker Optics, Billerica, MA, USA). We measured the transfer, output characteristics, and synaptic behavior using an Agilent 4156B Precision Semiconductor Parameter Analyzer (Hewlett-Packard Co., Palo Alto, Santa Clara, CA, USA). To apply a pre-synapse spike, we applied electrical pulses using Agilent 8110A Pulse Generator (Hewlett-Packard Co., Palo Alto, Santa Clara, CA, USA). We evaluated the crystal structure of the microwave annealed NiSi film through X-ray diffraction analysis using a SmartLab X-ray diffractometer (Rigaku Co., Tokyo, Japan).

Device Structure of Ambipolar Chitosan Synaptic Transistor
Recent studies on synaptic transistors using chitosan electrolytes as EDL have restricted the options in the device fabrication process due to limitations of the mechanical/chemical weakness of the organic chitosan layer. Representatively, the patterning process using a shadow mask that does not require additional etching and cleaning has been forced after the formation of the chitosan electrolyte layer [30][31][32][33][34]. However, through our latest research, we secured the possibility of applying the lithography patterning process by laminating the high-k Ta 2 O 5 as a barrier layer [18,19]. Subsequently, as the fabrication process limit expanded, we applied ambipolar-type undoped poly-Si as a channel layer and MWA-silicided Ni S/D to develop an advanced-structure chitosan synaptic transistor with a photolithography process optimized for high integration. The Si-based ambipolar synaptic transistor in our study can provide CMOS process compatibility and high stability compared to other channel materials such as oxide semiconductor or graphene. The schematic structure of the fabricated top-gate type chitosan synaptic transistor is shown in Figure 1c,d.

Characterization of Chitosan Electrolyte EDL and NiSi S/D
We applied the chitosan electrolyte EDL as a neurotransmitter in the biologic synapse to implement synaptic behavior. For fabricating a photolithography-processed chitosan synaptic transistor, an appropriate chitosan oven baking must be applied to prevent the swelling/outgassing of the chitosan electrolyte film due to chemical/thermal damage during the photolithography process [18]. Figure 2a shows the FT-IR spectra of the chitosan electrolyte film according to the oven baking condition. The typical chitosan FT-IR peak shape remains stable until the 130 • C oven baking. Figure 2b shows the detailed FT-IR spectra at 130 • C for accurate band characterization of 130 • C oven-baked chitosan films. The band around 3412 cm −1 is attributed to the O-H peak. The C-H stretching peak is around 2902 cm −1 . In addition, the band at 1672 cm −1 is ascribed to the N-H bending of -NH 2 . The bands at 1398 cm −1 are ascribed to the C-N (amide) peak. The C-O peak appears at 1066 cm −1 . These bands are primarily reported in synaptic transistor studies using chitosan electrolytes as EDL [35,36]. Therefore, we prevented chemical/thermal damage during the photolithography process through 130 • C oven baking in which the band of chitosan electrolyte film remained stable. by laminating the high-k Ta2O5 as a barrier layer [18,19]. Subsequently, as the fabricat process limit expanded, we applied ambipolar-type undoped poly-Si as a channel la and MWA-silicided Ni S/D to develop an advanced-structure chitosan synaptic transis with a photolithography process optimized for high integration. The Si-based ambipo synaptic transistor in our study can provide CMOS process compatibility and high sta ity compared to other channel materials such as oxide semiconductor or graphene. T schematic structure of the fabricated top-gate type chitosan synaptic transistor is sho in Figure 1c,d.

Characterization of Chitosan Electrolyte EDL and NiSi S/D
We applied the chitosan electrolyte EDL as a neurotransmitter in the biologic syna to implement synaptic behavior. For fabricating a photolithography-processed chito synaptic transistor, an appropriate chitosan oven baking must be applied to prevent swelling/outgassing of the chitosan electrolyte film due to chemical/thermal damage d ing the photolithography process [18]. Figure 2a shows the FT-IR spectra of the chito electrolyte film according to the oven baking condition. The typical chitosan FT-IR p shape remains stable until the 130 °C oven baking. Figure 2b shows the detailed FT spectra at 130 °C for accurate band characterization of 130 °C oven-baked chitosan fil The band around 3412 cm −1 is attributed to the O-H peak. The C-H stretching peak around 2902 cm −1 . In addition, the band at 1672 cm −1 is ascribed to the N-H bending NH2. The bands at 1398 cm −1 are ascribed to the C-N (amide) peak. The C-O peak appe at 1066 cm −1 . These bands are primarily reported in synaptic transistor studies using c tosan electrolytes as EDL [35,36]. Therefore, we prevented chemical/thermal damage d ing the photolithography process through 130 °C oven baking in which the band of c tosan electrolyte film remained stable. We applied NiSi as an S/D electrode on the undoped poly-Si channel to provide terface stability and low contact resistance compared to metal-Si junctions by formin Schottky barrier. As a self-aligned silicide annealing process of NiSi, we performe short-time efficient MWA-a unique volumetric direct heating method promising achieve advanced Si CMOS process [37]. Figure 3a,b shows the XRD pattern of N formed by 600 W of MWA treatment and the Schottky contact diagram between NiSi a Si interface, respectively. The XRD peaks appearing in the diffraction pattern were ferred to as the peak data of the International Committee for Diffraction Data pow diffraction file for accurate identification [38]. Certain (200), (210), (211), (220), (310), a (301) peaks indicating the preferentially oriented peaks of NiSi were identified. The N provides strong immunity to the short channel effect and bridging failure, which can fatal for scaled neural-ICs resulting from a short-circuit area between the gate and S [39,40]. We applied NiSi as an S/D electrode on the undoped poly-Si channel to provide interface stability and low contact resistance compared to metal-Si junctions by forming a Schottky barrier. As a self-aligned silicide annealing process of NiSi, we performed a short-time efficient MWA-a unique volumetric direct heating method promising to achieve advanced Si CMOS process [37]. Figure 3a,b shows the XRD pattern of NiSi formed by 600 W of MWA treatment and the Schottky contact diagram between NiSi and Si interface, respectively. The XRD peaks appearing in the diffraction pattern were referred to as the peak data of the International Committee for Diffraction Data powder diffraction file for accurate identification [38]. Certain (200), (210), (211), (220), (310), and (301) peaks indicating the preferentially oriented peaks of NiSi were identified. The NiSi provides strong immunity to the short channel effect and bridging failure, which can be fatal for scaled neural-ICs resulting from a short-circuit area between the gate and S/D [39,40]. Nanomaterials 2022, 12, 3063 5 of 12  Figure 4a shows the double-sweep transfer characteristic (ID-VG) curves of the ambipolar chitosan synaptic transistor at a constant drain voltage (VD) of 1 V. The gate voltage sweep was swept forward from −20 V to 20 V and then swept backward from 20 V to −20 V. Due to the undoped ambipolar type poly-Si channel, p-and n-type operate well by hole and electron accumulation, respectively. Meanwhile, the normally off behavior is attributed to carrier depletion caused by the NiSi Schottky barriers [41]. Figure 4c,d show this current flow mechanism. When the negative gate bias is applied simultaneously with drain bias, the holes are injected into the poly-Si channel according to the mechanism of tunneling or thermionic emission. Likewise, in the case of positive bias applied to the gate, the electrons are injected into the channel. Meanwhile, a wide hysteresis window appears between forward and reverse sweeps under double-sweep transfer conditions. It is due to the slow polarization reaction of mobile ions in the chitosan electrolyte EDL. Figure 4b shows the symmetric output characteristics (ID-VD) curves measured in the p-and n-regions. Ambipolar-type channel transistors typically exhibit leakage currents on output curves due to opposite carriers (electrons in p-region, holes in n-region) at high VD [42][43][44]. However, in the low VD required for synaptic operation (less than 5 V), such leakage current does not significantly affect and saturate stably.   Figure 4a shows the double-sweep transfer characteristic (I D -V G ) curves of the ambipolar chitosan synaptic transistor at a constant drain voltage (V D ) of 1 V. The gate voltage sweep was swept forward from −20 V to 20 V and then swept backward from 20 V to −20 V. Due to the undoped ambipolar type poly-Si channel, p-and n-type operate well by hole and electron accumulation, respectively. Meanwhile, the normally off behavior is attributed to carrier depletion caused by the NiSi Schottky barriers [41]. Figure 4c,d show this current flow mechanism. When the negative gate bias is applied simultaneously with drain bias, the holes are injected into the poly-Si channel according to the mechanism of tunneling or thermionic emission. Likewise, in the case of positive bias applied to the gate, the electrons are injected into the channel. Meanwhile, a wide hysteresis window appears between forward and reverse sweeps under double-sweep transfer conditions. It is due to the slow polarization reaction of mobile ions in the chitosan electrolyte EDL. Figure 4b shows the symmetric output characteristics (I D -V D ) curves measured in the pand n-regions. Ambipolar-type channel transistors typically exhibit leakage currents on output curves due to opposite carriers (electrons in p-region, holes in n-region) at high V D [42][43][44]. However, in the low V D required for synaptic operation (less than 5 V), such leakage current does not significantly affect and saturate stably.   Figure 4a shows the double-sweep transfer characteristic (ID-VG) curves of the ambipolar chitosan synaptic transistor at a constant drain voltage (VD) of 1 V. The gate voltage sweep was swept forward from −20 V to 20 V and then swept backward from 20 V to −20 V. Due to the undoped ambipolar type poly-Si channel, p-and n-type operate well by hole and electron accumulation, respectively. Meanwhile, the normally off behavior is attributed to carrier depletion caused by the NiSi Schottky barriers [41]. Figure 4c,d show this current flow mechanism. When the negative gate bias is applied simultaneously with drain bias, the holes are injected into the poly-Si channel according to the mechanism of tunneling or thermionic emission. Likewise, in the case of positive bias applied to the gate, the electrons are injected into the channel. Meanwhile, a wide hysteresis window appears between forward and reverse sweeps under double-sweep transfer conditions. It is due to the slow polarization reaction of mobile ions in the chitosan electrolyte EDL. Figure 4b shows the symmetric output characteristics (ID-VD) curves measured in the p-and n-regions. Ambipolar-type channel transistors typically exhibit leakage currents on output curves due to opposite carriers (electrons in p-region, holes in n-region) at high VD [42][43][44]. However, in the low VD required for synaptic operation (less than 5 V), such leakage current does not significantly affect and saturate stably.    [30,45]. When a bias is applied to the top gate, these mobile ions cause a slow polarization reaction in the chitosan electrolyte EDL. Under the negative bias condition, anions accumulate at the interface of the ambipolar-type poly-Si channel. Under the positive bias condition, cations accumulate at the channel interface. Figure 5c,d show a double-sweep transfer curve measured separately for p-and n-regions, respectively. In the p-region, holes in the ambipolar poly-Si channel act as major carriers. In the n-region, electrons act as major carriers. First, the p-region double-sweep transfer curve in Figure 5c was measured by decreasing the minimum gate voltage (V G-Min ) sweep range from −6 V to −12 V (in −0.5 V steps). The clockwise hysteresis in the curves occurred due to negative bias applied to the gate during the double sweep, which is observed in a p-type operating EDL synaptic transistor [46,47]. Figure 5e shows the hysteresis window and the threshold voltage (V th ) variation according to the V G-Min on the p-region. As the V G-Min decreases, the V th remains fixed, and the hysteresis window linearly increases and then saturates. This is because more anions (CH 3 COO − or OH − ) accumulate at the channel interface by the strong negative bias and require a strong positive bias to diffuse back. Then, after enough anions are accumulated, the hysteresis window remains saturated. Second, the opposite polarity of the n-region double-sweep transfer curve in Figure 5d was measured by increasing the maximum gate voltage (V G-Max ) sweep range from −5 V to 10 V (in 0.5 V steps). Contrary to the p-region, anti-clockwise hysteresis occurred at the n-region due to positive bias applied to the gate during the double sweep, which is observed in an n-type operating EDL synaptic transistor [48,49]. Figure 5f shows the hysteresis window and the V th variation according to the V G-Max on the n-region. Considering the case of the p-region, the increasing tendency of the hysteresis window in the n-region is due to the accumulation of cations (H + ). Consequently, we examined the fundamental operation of the ambipolar chitosan synaptic transistor due to the slow mobile ion polarization in the chitosan.

Synapse Mimicking Properties of the Ambipolar Chitosan Synaptic Transistor
The synaptic behavior of synaptic transistor operation is essential to mimic the biologic synapse functionality and mechanism. In biology, neurons and synapses behave like the two fundamental computational engines in the human brain. The signal spikes generated by pre-synaptic neurons are transmitted to post-synaptic neurons through neurotransmitters [50]. In the fabricated ambipolar chitosan synaptic transistor, the electrical spikes applied at the Al top-gate (pre-synapse) migrate the mobile ions (neurotransmitter) in the Ta 2 O 5 /chitosan EDL composite insulator layer (synaptic cleft) to the ambipolar-type poly-Si channel (post-synapse). Consequently, electrical spikes cause excitatory current in the post-synapse channel, which is called excitatory postsynaptic current (EPSC). EPSC is a fundamental representation of synaptic strength [51]. Figure 6a shows the simplified schematic of the EPSC measurement. Figure 6b shows the EPSC retention characteristics for a single pre-synapse spike in the n-and p-regions. For nregion measurement, a pre-synapse spike with an amplitude of 1 V and duration of 50 ms was applied under a constant V D of 1 V. For p-region measurement, a pre-synapse spike with an amplitude of −1 V and duration of 50 ms was applied under a constant V D of −1 V. After the pre-synapse spike, the EPSC rises to a peak and then slowly decreases by the slow polarization reaction of the mobile ions in the chitosan EDL. This tendency is well-implemented in both n-and p-regions. These temporal profiles of the EPSC are similar to biological excitatory synapses. Just a few seconds of the EPSC retention time scale implies short-term synaptic plasticity, which allows the basis of learning and memory of the nervous information process system [20]. Figure 6c,d show the resting EPSC after stimulation by an amplitude-variated pre-synapse spike in the p-and n-regions, respectively. After 5 s of spike stimulation, the resting EPSC absolute value slightly increased from −2.0 nA to −4.1 nA as the pre-synapse spike amplitude increased from −1 V to −6 V in the p-region. In the n-region, as the pre-synapse spike amplitude increased from 1 to 6 V, the resting EPSC absolute value slightly increased from 4.6 nA to 7 nA. Through the resting EPSC tendency, we found that increasing the amplitude of the pre-synapse spike can affect the temporal property of the synaptic plasticity in both p-and n-regions.
opposite polarity of the n-region double-sweep transfer curve in Figure 5d was by increasing the maximum gate voltage (VG-Max) sweep range from −5 V to 10 V steps). Contrary to the p-region, anti-clockwise hysteresis occurred at the n-regi positive bias applied to the gate during the double sweep, which is observed in operating EDL synaptic transistor [48,49]. Figure 5f shows the hysteresis windo Vth variation according to the VG-Max on the n-region. Considering the case of the the increasing tendency of the hysteresis window in the n-region is due to the a tion of cations (H + ). Consequently, we examined the fundamental operation of polar chitosan synaptic transistor due to the slow mobile ion polarization in the  As a form of short-term synaptic plasticity, the paired-pulse facilitation (PPF) characteristic represents the dynamic enhancement of neurotransmitters in biological neural synapses, involved in several neural tasks such as simple learning and encoding temporal information [52]. PPF is the degree of facilitation between the first and second pre-synapse spikes. In the fabricated ambipolar chitosan synaptic transistor, it is possible to know the degree to which mobile ions moved to the channel interface by the first pre-synapse spike, further facilitated by the second spike before diffusing back. Figure 7a,b show the PPF index in the p-and n-regions, respectively. The PPF index can be obtained as a ratio of the EPSC value (A1) triggered by the first spike and the EPSC value (A2) triggered by the second spike. For extracting the PPF, two consecutive spikes with a duration of 50 ms (p-region amplitude = −1 V, n-region amplitude = 1 V) were applied by adjusting the interval time (∆t inter ) between spikes. The shorter the interval between the two spikes, the more the occurrence of EPSC facilitation. At 50 ms intervals, the PPF index increased to 175% in the p-region and 171% in the n-region. The decay of the PPF index with the spike interval was fitted by a double exponential decay function, the extracted relaxation time constants are τ 1 = 12 ms, τ 2 = 300 ms in the p-region, and τ 1 = 16 ms, τ 2 = 243 ms in the n-region, respectively. In the biological synapses, τ 1 is about tens of milliseconds (rapid phase) and τ 2 is about hundreds of milliseconds (slow phase), which is similar to the extracted values in this study [53,54].  Synaptic plasticity can be gradually enhanced by multiple pre-synaptic spikes. We accomplished actual information processing between synapses through multiple pre-synaptic spikes. Figure 8a,b show EPSC responses to multiple pre-synapse spikes in the pand n-regions, respectively. In the single pre-synapse spike condition (duration = 50 ms, p-region amplitude = −1 V, and n-region amplitude = 1 V) applied thus far, spikes were continuously applied from 10 to 50 times with a spike interval time of 100 ms. The more the multiple pre-synapse spikes are applied, the more the facilitation of peak EPSC and increase in the resting EPSC. Figure 8c,d show spike cycle dependence of the EPSC change ratio in the p-and n-regions. EPSC change ratio means ((I − I0)/I0) × 100%, where I0 and I are the channel current before and after the gate spike stimulation, respectively [9]. The EPSC change ratio after 10 s increases significantly with the increase in the cycles of pulse, indicating a trend from short-term to long-term synaptic plasticity. Thus, we successfully confirmed the synaptic plasticity in both p-and n-regions by accumulating the mobile  Synaptic plasticity can be gradually enhanced by multiple pre-synaptic spikes. We accomplished actual information processing between synapses through multiple pre-synaptic spikes. Figure 8a,b show EPSC responses to multiple pre-synapse spikes in the pand n-regions, respectively. In the single pre-synapse spike condition (duration = 50 ms, p-region amplitude = −1 V, and n-region amplitude = 1 V) applied thus far, spikes were continuously applied from 10 to 50 times with a spike interval time of 100 ms. The more the multiple pre-synapse spikes are applied, the more the facilitation of peak EPSC and increase in the resting EPSC. Figure 8c,d show spike cycle dependence of the EPSC change ratio in the p-and n-regions. EPSC change ratio means ((I − I0)/I0) × 100%, where I0 and I are the channel current before and after the gate spike stimulation, respectively [9]. The EPSC change ratio after 10 s increases significantly with the increase in the cycles of pulse, indicating a trend from short-term to long-term synaptic plasticity. Thus, we successfully confirmed the synaptic plasticity in both p-and n-regions by accumulating the mobile Synaptic plasticity can be gradually enhanced by multiple pre-synaptic spikes. We accomplished actual information processing between synapses through multiple pre-synaptic spikes. Figure 8a,b show EPSC responses to multiple pre-synapse spikes in the p-and n-regions, respectively. In the single pre-synapse spike condition (duration = 50 ms, pregion amplitude = −1 V, and n-region amplitude = 1 V) applied thus far, spikes were continuously applied from 10 to 50 times with a spike interval time of 100 ms. The more the multiple pre-synapse spikes are applied, the more the facilitation of peak EPSC and increase in the resting EPSC. Figure 8c,d show spike cycle dependence of the EPSC change ratio in the p-and n-regions. EPSC change ratio means ((I − I 0 )/I 0 ) × 100%, where I 0 and I are the channel current before and after the gate spike stimulation, respectively [9]. The EPSC change ratio after 10 s increases significantly with the increase in the cycles of pulse, indicating a trend from short-term to long-term synaptic plasticity. Thus, we successfully confirmed the synaptic plasticity in both p-and n-regions by accumulating the mobile ions in the chitosan electrolyte EDL to poly-Si channel on the fabricated ambipolar chitosan synaptic transistor.  To construct a practical neuromorphic system using the conductance variability of the ambipolar chitosan synaptic transistor, we investigated the potentiation and depression curves. When the potentiation/depression properties of the ambipolar chitosan synaptic transistors are applied to an artificial neural network (ANN), more diverse functionalities can be secured to the bio-inspired neuromorphic computing systems [55]. Figure  9a,b show the synaptic weight update states according to 50 excitatory/inhibitory pre-synapse spike cycles in the p-and n-regions, respectively. The synaptic weight was gradually changed by each excitatory/inhibitory stimulus. We extracted weight update margins (ΔG = Gmax − Gmin, G refers to the channel conductance) and nonlinearity (αp and αd, the ideal value = 1) from the potentiation/depression curves for both p-and n-regions [56]. In the learning process implemented through ANN, each of these ΔG values are involved in the efficiency of unidirectional learning for both p-and n-regions. The ΔG values in the pand n-regions are identified as 15.42 and 24.69, respectively. In addition, the values of αp are 1.72 in the p-region and 1.69 in the n-region. The values of αd are −1.63 in the p-region and −0.41 in the n-region, respectively, demonstrating a better learning efficiency in the nregion. In particular, even with the same stimulus (positive or negative spike), the synaptic weight can be potentiated or depressed by whether the ambipolar synaptic transistor operates in the n-region or the p-region. This property can more closely mimic the central nervous system of a human brain, which reacts differently to the same stimulus depending on the external environment [25]. Accordingly, the ambipolar synaptic behavior not only enables various information processing for positive and negative signals using both n-and p-regions but is also more suitable for mimicking the biological human brain. To construct a practical neuromorphic system using the conductance variability of the ambipolar chitosan synaptic transistor, we investigated the potentiation and depression curves. When the potentiation/depression properties of the ambipolar chitosan synaptic transistors are applied to an artificial neural network (ANN), more diverse functionalities can be secured to the bio-inspired neuromorphic computing systems [55]. Figure 9a,b show the synaptic weight update states according to 50 excitatory/inhibitory pre-synapse spike cycles in the p-and n-regions, respectively. The synaptic weight was gradually changed by each excitatory/inhibitory stimulus. We extracted weight update margins (∆G = G max − G min , G refers to the channel conductance) and nonlinearity (α p and α d , the ideal value = 1) from the potentiation/depression curves for both p-and n-regions [56]. In the learning process implemented through ANN, each of these ∆G values are involved in the efficiency of unidirectional learning for both p-and n-regions. The ∆G values in the p-and n-regions are identified as 15.42 and 24.69, respectively. In addition, the values of α p are 1.72 in the p-region and 1.69 in the n-region. The values of α d are −1.63 in the p-region and −0.41 in the n-region, respectively, demonstrating a better learning efficiency in the n-region. In particular, even with the same stimulus (positive or negative spike), the synaptic weight can be potentiated or depressed by whether the ambipolar synaptic transistor operates in the n-region or the p-region. This property can more closely mimic the central nervous system of a human brain, which reacts differently to the same stimulus depending on the external environment [25]. Accordingly, the ambipolar synaptic behavior not only enables various information processing for positive and negative signals using both n-and p-regions but is also more suitable for mimicking the biological human brain.

Conclusions
We proposed the ambipolar chitosan synaptic transistor securing complex information process versatility in neural processing. We laminated high-k Ta2O5 on chitosan EDL as a barrier layer to enable a photolithography process of ambipolar chitosan synaptic transistor. Binary synaptic operation in both the p-region and n-region was successfully implemented by applying ambipolar type poly-Si channel and slow polarization reaction of chitosan mobile ions (H + , CH3COO − , and OH − ). We demonstrated synaptic properties, including EPSC and gradual potentiation/depression characteristics, in the ambipolar chitosan synaptic transistor in each of the p-and n-regions. The fabricated devices can mimic stably the biological synaptic properties. Furthermore, depending on whether the device operates in the n-or p-region, the artificial synapse is potentiated or depressed even under the same gate bias stimulus. The combination of such binary synaptic properties of ambipolar chitosan synaptic transistor provides the capacity to imitate more complex functions in the biological neural system.

Conclusions
We proposed the ambipolar chitosan synaptic transistor securing complex information process versatility in neural processing. We laminated high-k Ta 2 O 5 on chitosan EDL as a barrier layer to enable a photolithography process of ambipolar chitosan synaptic transistor. Binary synaptic operation in both the p-region and n-region was successfully implemented by applying ambipolar type poly-Si channel and slow polarization reaction of chitosan mobile ions (H + , CH 3 COO − , and OH − ). We demonstrated synaptic properties, including EPSC and gradual potentiation/depression characteristics, in the ambipolar chitosan synaptic transistor in each of the p-and n-regions. The fabricated devices can mimic stably the biological synaptic properties. Furthermore, depending on whether the device operates in the n-or p-region, the artificial synapse is potentiated or depressed even under the same gate bias stimulus. The combination of such binary synaptic properties of ambipolar chitosan synaptic transistor provides the capacity to imitate more complex functions in the biological neural system.