Search Results (423)

Stealthy chip-level tamper attacks, such as hardware Trojan insertions or security-critical circuit modifications, can threaten modern microelectronic systems’ security. While traditional inspection and side-channel methods offer potential for tamper detection, they may not reliably detect all forms of attacks and often face practical limitations in terms of scalability, accuracy, or applicability. This work introduces a non-invasive, contactless tamper detection method employing a complementary split-ring resonator (CSRR). CSRRs, which are typically deployed for non-destructive material characterization, can be placed on the surface of the chip’s package to detect subtle variations in the impedance of the chip’s power delivery network (PDN) caused by tampering. The changes in the PDN’s impedance profile perturb the local electric near field and consequently affect the sensor’s impedance. These changes manifest as measurable variations in the sensor’s scattering parameters. By monitoring these variations, our approach enables robust and cost-effective physical integrity verification requiring neither physical contact with the chips or printed circuit board (PCB) nor activation of the underlying malicious circuits. To validate our claims, we demonstrate the detection of various chip-level tamper events on an FPGA manufactured with 28 nm technology. Full article

Optimizing artificial lighting in controlled-environment agriculture is crucial for enhancing crop productivity and resource efficiency. This study presents a spectral–spatial co-optimization strategy for LED lighting tailored to the physiological needs of Italian lettuce (Lactuca sativa L. var. italica). A miniature plant factory system was developed with dimensions of 400 mm × 400 mm × 500 mm (L × W × H). Seven customized spectral treatments were created using 2835-packaged LEDs, incorporating various combinations of blue and violet LED chips with precisely controlled concentrations of red phosphor. The spectral configurations were aligned with the measured absorption peaks of Italian lettuce (450–470 nm and 640–670 nm), achieving a spectral mixing uniformity exceeding 99%, while the spatial light intensity uniformity surpassed 90%. To address spatial light heterogeneity, a particle swarm optimization (PSO) algorithm was employed to determine the optimal LED arrangement, which increased the photosynthetic photon flux density (PPFD) uniformity from 83% to 93%. The system operates with a fixture-level power consumption of only 75 W. Experimental evaluations across seven treatment groups demonstrated that the E-spectrum group—comprising two violet chips, one blue chip, and 0.21 g of red phosphor—achieved the highest agronomic performance. Compared to the A-spectrum group (three blue chips and 0.19 g of red phosphor), the E-spectrum group resulted in a 25% increase in fresh weight (90.0 g vs. 72.0 g), a 30% reduction in SPAD value (indicative of improved light-use efficiency), and compared with Group A, Group E exhibited significant improvements in plant morphological parameters, including a 7.05% increase in plant height (15.63 cm vs. 14.60 cm), a 25.64% increase in leaf width (6.37 cm vs. 5.07 cm), and a 6.35% increase in leaf length (10.22 cm vs. 9.61 cm). Furthermore, energy consumption was reduced from 9.2 kWh (Group A) to 7.3 kWh (Group E). These results demonstrate that integrating spectral customization with algorithmically optimized spatial distribution is an effective and scalable approach for enhancing both crop yield and energy efficiency in vertical farming systems. Full article

This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 MHz and 437 MHz) without the need for additional circuitry. The MEMS resonators, fabricated on silicon-on-insulator (SOI) wafers, exhibit high-quality factors (Q), ensuring superior phase noise performance. Experimental results indicate that the oscillator packaged using 3D-printed chip-carrier assembly achieves a 2–3 dB improvement in phase noise compared to the PCB-based oscillator, attributed to the ABS substrate’s lower dielectric loss and reduced parasitic effects at radio frequency (RF). Specifically, phase noise values between −84 and −77 dBc/Hz at 1 kHz offset and a noise floor of −163 dBc/Hz at far-from-carrier offset were achieved. Additionally, the 3D-printed ABS-based oscillator delivers notably higher output power (4.575 dBm at 260 MHz and 0.147 dBm at 437 MHz). To facilitate modular characterization, advanced packaging techniques leveraging precise 3D-printed encapsulation with sub-100 μm lateral interconnects were employed. These ensured robust packaging integrity without compromising oscillator performance. Furthermore, a comparison between two transistor technologies—a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) and an enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT)—demonstrated that SiGe HBT transistors provide superior phase noise characteristics at close-to-carrier offset frequencies, with a significant 11 dB improvement observed at 1 kHz offset. These results highlight the promising potential of 3D-printed chip-carrier packaging techniques in high-performance MEMS oscillator applications. Full article

This paper proposes a method for determining the contact temperature in the secondary shear zone. The input data include the results of the experimental tests of the orthogonal turning of a Ti-6Al-4V titanium workpiece using uncoated WC-Co tools with a flat rake face. The cutting force components were recorded using a piezoelectric dynamometer, a thermovision camera was used to record the temperature in the cutting zone, and a high-speed camera was used to record the chip-forming process. The independent variables included machining parameters, feed rate, cutting speed, and rake angle. A dual-zone thermomechanical cutting process model that accounted for the sticking and sliding areas was adapted for the identification of the heat flux in the chip–rake face contact zone. Then, based on the Shaw approach, the partition coefficients were determined for the contact temperature on the chip–tool tip contact. In addition, the results of the experimental tests allowed the determination of the relationship among the process parameters, friction coefficients, and the length of the contact of the chip with the tool rake face. A graphical visualization of the temperature distribution on the tool rake face was performed using the MATLAB PDE 3.9 software package. Although the application of the dual-zone model has been well presented in the literature, the results provided in this paper may be helpful in analyzing and modeling thermal phenomena in the secondary shear zone. Full article

Flexographic printing, traditionally used in the packaging industry, has emerged as a promising technology for microfluidic device fabrication due to enabling high resolution and being commercially available at a low cost compared to conventional techniques. This review explores the adaptation of a photopolymer flexographic printing plate mold (FMold) for microfluidics, examining its advantages, challenges, and applications. It offers a state-of-the-art view of the application of FMold for microfluidic systems, which offers a unique opportunity in terms of cost-effectiveness, scalability, and rapid prototyping. Applications are diverse: FMold has enabled the fabrication of microfluidic devices used in enhanced oil recovery to prepare rock-on-a-chip models, droplet generation and storage, suspension cell culture, monoclonal antibody production, complex cell differentiation pattern creation, phage screening, drug screening, cell detection, and cancer stem cell culture. Since its first appearance in 2018, FMold has been utilized in 50 publications in different laboratories around the world. Key advancements, current research trends, and future prospects are discussed to provide a comprehensive overview of this evolving tool. Full article

Objectives: The study investigates runs of homozygosity (ROH) and heterozygosity (ROHet), and their patterns in nine sheep breeds (772 animals in total) maintained in Poland (native and conserved), corresponding to their genetic diversity, inbreeding levels, and selection signatures. Methods: Genotypes were obtained using the Illumina OvineSNP50 BeadChip and quality-filtered SNPs were used to detect ROH and ROHet segments with the detectRUNS R package, following stringent parameters for segment length, SNP density, and genotype quality. Results: Significant variation in ROH characteristics was observed across breeds. Short ROH segments were predominant in all breeds, indicating historical inbreeding events. In contrast, longer ROH segments signified recent inbreeding, particularly in Swiniarka (SW) and Polish Merino of Colored Variety (MPC). The ROH-based genomic inbreeding coefficient (F_ROH) varied across breeds, with SW exhibiting the highest levels, suggesting reduced genetic diversity. ROHet analysis revealed that Uhruska (UHR) had the highest heterozygous segments span, while Black-headed (BH) sheep exhibited the lowest ROHet extent. ROH islands identified across breeds revealed regions under selection, associated with traits such as reproductive performance, wool quality, and body condition. Genes located within these islands (e.g., U6, SPP1, ABCG2) were linked to economically significant traits including milk production, growth, and carcass quality. Conclusions: The presented results highlight the genetic adaptations shaped by selection pressures, while also providing insights into the genetic architecture of sheep breeds maintained in Poland. Full article

This paper presents a 2-stage GaN Doherty power amplifier module (DPAM) on a compact $7\times 7$ quad flat no-lead (QFN) package, designed for the needs of 5G massive MIMO base transceiver systems. The interstage and input matching networks employ high-quality factor integrated passive devices (IPDs) to achieve a small form factor. This multi-chip module consists of three GaN-HEMT bare dies used for the driver stage, carrier amplifier, and peaking amplifier. Additionally, two IPD dies are included for the interstage and input matching networks. The external load network is developed using a printed circuit board (PCB). Utilizing a 5G NR signal of 100 MHz bandwidth and a 9.3 dB PAPR within the 3.4–3.8 GHz band, the developed DPAM demonstrated a power gain exceeding 26.8 dB and a power-added efficiency (PAE) greater than 37.8% at a 39 dBm average output power. Full article

Advancements in semiconductor packaging toward higher integration and interconnect density have increased the risk of structural defects—such as missing solder balls, pad delamination, and bridging—that can disrupt thermal conduction paths, leading to localized overheating and potential chip failure. To address the limitations of traditional non-destructive testing methods in detecting micron-scale defects, this study introduces a multimodal detection approach combining finite-element thermal simulation, infrared thermography, and the YOLO11 deep learning network. A comprehensive 3D finite-element model of a ball grid array (BGA) package was developed to analyze the impact of typical defects on both steady-state and transient thermal distributions, providing a solid physical foundation for modeling defect-induced thermal characteristics. An infrared thermal imaging platform was established to capture real thermal images, which were then compared with simulation results to verify physical consistency. An integrated dataset of simulated and infrared images was constructed to enhance the robustness of the detection model. Leveraging the YOLO11 network’s capabilities in end-to-end training, dataset small-object detection, and rapid inference, the system achieved accurate and rapid localization of defect regions. Experimental results show a mean average precision (mAP) of 99.5% at an intersection over union (IoU) threshold of 0.5 and an inference speed of 556 frames per second on the simulation dataset. Training with the hybrid dataset improved detection accuracy on real images from 41.7% to 91.7%, significantly outperforming models trained on a single data source. Furthermore, the maximum temperature discrepancy between simulation and experimental measurements was less than 5%, validating the reliability of the proposed method. This research offers a high-precision, real-time solution for semiconductor packaging defect detection, with substantial potential for industrial application. Full article

Currently, the global technological competition pattern is accelerating its restructuring, and chip technology, as a core technology for national strategic security and industrial competition, faces a serious bottleneck that seriously restricts the construction of China’s industrial chain security and innovation ecology. A “recognition-evolution” collaborative analysis system was proposed in this study using patent data as a carrier. Firstly, a PKCN-BERT-LDA fusion module was constructed to identify the core technologies of chip design, manufacturing, and packaging testing. Secondly, the traditional main path analysis method was improved by innovatively introducing information entropy theory to construct a dynamic evolution model, and the technological evolution path in the chip field during 2010–2024 was systematically tracked based on the Derwent patent database. According to this study, the field of chip design exhibited a bidirectional innovation feature of “system optimization regional deep cultivation”, while the manufacturing process highlights the non-linear accumulation law of process complexity. Packaging and testing technology tended to develop in synergy with integration and intelligence. Full article

This paper presents a highly linear two-stage InGaP/GaAs power amplifier integrated circuit (PAIC) using a dynamic predistorter for 5G small-cell applications. The proposed predistorter, based on a diode-connected transistor, utilizes a supply voltage to accurately control the linearization characteristics by adjusting its dc current. It is connected in parallel with an inter-stage of the two-stage PAIC through a series configuration of a resistor and an inductor, and features a shunt capacitor at the base of the transistor. These passive components have been optimized to enhance the linearization performance by managing the RF signal’s coupling to the diode. Using these optimized components, the AM−AM and AM−PM nonlinearities arising from the nonlinear resistance and capacitance in the diode can be effectively used to significantly flatten the AM−AM and AM−PM characteristics of the PAIC. The proposed predistorter was applied to the 2.6 GHz two-stage InGaP/GaAs HBT PAIC. The IC was tested using a 5 × 5 mm² module package based on a four-layer laminate. The load network was implemented off-chip on the laminate. By employing a continuous-wave (CW) signal, the AM−AM and AM−PM characteristics at 2.55–2.65 GHz were improved by approximately 0.05 dB and 3°, respectively. When utilizing the new radio (NR) signal, based on OFDM cyclic prefix (CP) with a signal bandwidth of 100 MHz and a peak-to-average power ratio (PAPR) of 9.7 dB, the power-added efficiency (PAE) reached at least 11.8%, and the average output power was no less than 24 dBm, achieving an adjacent channel leakage power ratio (ACLR) of −40.0 dBc. Full article

The development of semiconductor processes and advanced packaging technology has promoted significant advancements in the miniaturization and integration of electronic devices and systems. However, these developments present substantial challenges to the thermal and stress design of current chips, necessitating novel approaches to address these issues. Traditional finite element simulation-assisted design methods have proven inadequate in meeting the demands of highly integrated electronic devices and microsystems due to their inability to effectively simulate the integration process, cross-scale, and multi-physical field coupling. To address these challenges and shorten the design and development period of electronic devices and microsystems, rigorous thermal and stress testing and analyses must be conducted. A promising approach is the utilization of TTC (thermal test chip) technology, a novel in situ testing method, as the primary tool for thermal/stress testing and analyses of the internal interfaces of electronic devices and microsystems. This technology has emerged as a crucial element in validating thermal/stress processes during packaging, as well as in the design of effective heat dissipation solutions. This paper is structured as follows: first, it introduces the principle of thermal test chips; second, it summarizes the domestic and international research progress and index parameter comparison of thermal test chips, as well as the application progress in chip packaging and heat dissipation; and finally, it looks forward to the application prospect of thermal test chips in microsystem design and advanced packaging. Full article

As photonic integrated circuits (PICs) gain prominence in quantum communication and quantum computation, the development of efficient and stable cryogenic packaging technologies becomes paramount. This paper presents a robust and scalable cryogenic packaging method for thin-film lithium niobate (TFLN) photonic chips. The packaged fiber-to-chip interface shows a coupling efficiency of 15.7% ± 0.3%, with minimal variation of ±0.5% as the temperature cools down from 295 K to 1.5 K. Furthermore, the packaged chip exhibits outstanding stability over multiple thermal cycling, highlighting its potential for practical applications in cryogenic environments. Full article

BAW filters have been widely used in RF circuits, and their combination with integrated passive inductors is one of the most common forms of BAW filters. However, the large size of passive inductors increases the area of the filter, making it unable to meet packaging requirements. At the same time, their low quality factor (Q) severely degrades the performance of the BAW filter. This paper presents a miniaturized wide band BAW filter with small-size high-Q active inductor. The active inductor is implemented by a circuit topology with three common-source amplifiers constructed with N-type transistors. The three-stage topology uses a small-size transistor in the middle stage to reduce the parasitic capacitance at the input node, achieving a large inductive bandwidth. The simulation results show that the active inductor has variable inductance from 1 nH to 10 nH, and a quality factor of up to 4 K from 2 to 7 GHz. The 30 × 30 μm² active inductor is embedded in a 4.55–5.05 GHz BAW filter ladder so as to substantially decrease filter size. Simulation results indicate that the BAW filter based on the active inductor achieves a low insertion loss of −1.1 dB, out-of-band rejection of −35 dB on the left side, and out-of-band rejection of −53 dB on the right side. Compared to the traditional passive inductor, this active inductor significantly improves the performance of the BAW filter while occupying a much smaller chip size of 0.83 × 0.75 mm². Full article

The growing complexities, power densities, and cooling demands of modern electronic systems and batteries—such as three-dimensional integrated circuit chip packaging, printed circuit board assemblies, and electronics enclosures—have pushed the urgency for efficient and dynamic thermal management strategies. Traditional numerical methods like computational fluid dynamics (CFD) and the finite element method (FEM) are computationally impractical for large-scale or real-time thermal analysis, especially when dealing with complex geometries, temperature-dependent material properties, and rapidly changing boundary conditions. These approaches typically require extensive meshing and repeated simulations for each new scenario, making them inefficient for design exploration or optimization tasks. Physics-informed neural networks (PINNs) emerge as a powerful alternative approach that incorporates physical principles such as mass and energy conservation equations into deep learning models. This approach delivers rapid and adaptable resolutions to the partial differential equations that govern heat transfer and fluid dynamics. This review examines the basic principle of PINN and its role in thermal management for electronics and batteries, from the small unit scale to the system scale. We highlight recent advancements in PINNs, particularly their superior performance compared to traditional CFD methods. For example, studies have shown that PINNs can be up to 300,000 times faster than conventional CFD solvers, with temperature prediction differences of less than 0.1 K in chip thermal models. Beyond speed, we explore the potential of PINNs in enabling efficient design space exploration and predicting outcomes for previously unseen scenarios. However, challenges such as training convergence in fine-grained or large-scale applications remain. Notably, research combining PINNs with LSTM networks for battery thermal management at a 2.0 C charging rate has achieved impressive results—an R² of 0.9863, a mean absolute error (MAE) of 0.2875 °C, and a root mean square error (RMSE) of 0.3306 °C—demonstrating high predictive accuracy. Finally, we propose future research directions that emphasize the integration of PINNs with advanced hardware and hybrid modeling techniques to advance thermal management solutions for next-generation electronics and battery systems. Full article

Until now, the ultimate solution for blind people has not been achieved, because challenges still exist. Retinal implants have emerged as a promising solution for restoring vision in individuals suffering from retinal degenerative diseases such as retinitis pigmentosa and age-related macular degeneration. Central to the efficacy of these implants is the design and functionality of the electrode arrays responsible for stimulating retinal neurons. This review evaluates the evolution of retinal implants, with particular emphasis on electrode specifications, physiological considerations for electrical stimulation, and recent advancements in electrode design. A comprehensive analysis of state-of-the-art published studies provides a detailed cross-comparison of electrode characteristics, offering insights into current state-of-the-art technologies and future directions. Full article