Search Results (740)

This paper presents a 2-GS/s voltage–time hybrid pipelined analog-to-digital converter (ADC) with a 14-bit digital output, implemented in a 28-nm CMOS process. To alleviate the gain–bandwidth–power trade-off in deeply scaled technologies, the proposed architecture employs a SHA-less front-end and a low-gain inverter-based push–pull RA for energy-efficient coarse quantization. The residue is then transferred to the time domain via a highly linear constant-current voltage-to-time converter (CC-VTC) and digitized by a four-channel time-interleaved gated-ring-oscillator (GRO) TDC. To recover dynamic linearity degraded by low-gain amplification and interleaving mismatches, a multiplier-less digital background calibration engine is implemented. Leveraging mean absolute value (MAV) statistics and dither-injected least-mean-squares (LMS) algorithms, it effectively compensates for inter-channel and interstage errors with minimal hardware overhead. The prototype occupies an active area of 0.16 mm². At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC. Full article

To address the demand for wide-swath, high-resolution short-wave infrared (SWIR) imaging on resource-constrained spaceborne platforms, this study presents the design and on-orbit validation of a compact dual-channel push-broom (line-scanning) imaging system. The system adopts a transmissive optical architecture and a centralized, compact electronic control unit (ECU) configuration. By interleaving and mosaicking sixteen InGaAs linear array detectors, the system achieves an imaging swath of approximately 187 km and a nominal ground sampling distance of about 24 m, while maintaining a total instrument mass of 10.62 kg and a power consumption of approximately 12 W, thereby demonstrating a high level of integration and efficient resource utilization. To address focal plane consistency issues arising from multi-detector mosaicking, a closed-loop leveling method was developed using the modulation transfer function (MTF) as the primary performance metric. Through defocus estimation and quantitative correction of protrusions on a SiC substrate, convergence toward a unified confocal focal plane among multiple detectors was achieved. On-orbit image quality assessment indicates that the full width at half maximum (FWHM) of the line spread function (LSF) for both channels is approximately 1.38 pixels, with favorable signal-to-noise ratio (SNR) performance. These results validate the effectiveness of the proposed focal plane leveling strategy as well as the opto-mechanical-thermal design of the system. The proposed approach provides a practical pathway for the engineering implementation and consistency control of multi-detector mosaicked SWIR payloads under stringent resource constraints. Full article

This paper presents a hardware-accelerated signal processing architecture for OFDM-based vehicular networks that integrates crypto-agile adaptive encryption on a Xilinx Kintex-7 FPGA. The encryption layer is tightly coupled to the OFDM modulation/demodulation pipeline, enabling secure real-time signal processing for V2X communications without disrupting the baseband chain. A context-aware pre-selection unit dynamically selects among hardware cipher primitives based on latency constraints, security requirements, and channel conditions. The current prototype implements and synthesizes AES-128 as the primary block cipher, while ASCON (NIST lightweight AEAD) and Keccak (SHA-3 foundation) are validated through RTL simulation and architectural integration, demonstrating crypto-agility across block, AEAD, and sponge-based primitives. DES is retained solely as a legacy reference for backward-compatibility evaluation and is not recommended for secure V2X deployment. The design adopts a modular decoupling strategy in which cryptographic engines interface with a unified buffering and interleaving subsystem, enabling hardware-based single-cycle cipher switching without partial reconfiguration. FPGA results demonstrate sub-microsecond cryptographic processing latencies with moderate resource utilization, preserving the timing budget of latency-sensitive vehicular services. AES-128 provides standard-strength encryption, while ASCON and Keccak offer lightweight and sponge-based alternatives suited to constrained IoV platforms. Specifically, the implemented AES-128 core achieves a throughput of 1.02 Gbps with a switching latency of 86 ns, verified across 10 randomized transitions with a 99.99% success rate and zero data corruption. The ASCON and Keccak cores attain throughput-to-area efficiencies of 2.01 and 1.47 Mbps/LUT, respectively, at a unified clock frequency of 50 MHz. All acronyms are defined at first use and a complete list of abbreviations is provided prior to the reference section. Full article

Time-interleaved analog-to-digital converters (TI-ADC) are sensitive to inter-phase timing skew, which degrades effective resolution unless mitigated by careful phase alignment or calibration. This paper presents a low-speed proof-of-concept four-phase TI-ADC based on dual-slope pulse-width modulation, incorporating an adjustable ON-TIME delay mechanism at the analog front end. The proposed approach enables controlled shifting of the effective sampling instant at the comparator/D-flip-flop interface without altering waveform amplitude or functional linearity. A four-phase up/down binary counter implemented using a Gray-code-based phase multiplier provides evenly spaced phases with reduced switching activity. Measurements from a breadboard prototype operating at approximately 1.5 MHz demonstrate that the adjustable ON-TIME delay can align adjacent phases and constrain observed inter-phase timing skew to the order of approximately 30 ns within the measurement resolution. The results indicate that analog front-end phase pre-alignment can complement or relax subsequent digital background calibration in time-interleaved ADC systems. Full article

Sonar is a fundamental tool for underwater target detection. However, conventional detection systems often suffer from poor sensor consistency and high fabrication costs. More critically, for low-frequency operation, the required array aperture becomes prohibitively large, limiting their deployment on small, mobile underwater platforms. To address the demand for compact, high-performance sensing solutions, this paper presents a miniaturized Micro-electromechanical Systems (MEMS) hydrophone array designed for underwater target detection. The array consists of six elements with a spacing of 0.25 m. Each element is approximately 22 mm in diameter and encapsulated in polyurethane via a casting and curing process. The core sensing element, a MEMS acoustic pressure hydrophone, exhibits a sensitivity of −177.2 ± 1.5 dB (re: 1 V/µPa) across the 20 Hz to 4 kHz frequency range and a noise resolution of approximately 59.5 dB (re: 1 µPa/√Hz) at 1 kHz. A key challenge in array-based detection is the phase mismatch among acquisition channels, which degrades algorithm performance. To mitigate this, we propose a phase self-correction method based on interleaved ADC acquisition control, enabling synchronous multi-channel sampling and effectively eliminating system-level phase errors. Furthermore, to overcome the inherent aperture limitations of conventional beamforming (CBF) applied to a miniaturized array, a differential beamforming (DBF) algorithm is adopted. This approach is less frequency-dependent and can approximate a frequency-invariant beam pattern, making it well-suited for miniaturized arrays. Simulation results confirm the theoretical validity of the DBF algorithm for the proposed MEMS hydrophone array. Sea trial data further demonstrate that this method achieves higher target detection accuracy compared to CBF techniques. Full article

This paper presents a high-performance and resource-efficient Field Programmable Gate Array (FPGA)-based architecture for satellite telemetry transmission systems. The proposed design implements a flexible channel coding chain, including Reed–Solomon (R-S) encoding, convolutional encoding, symbol interleaving, pseudo-randomization, and Attached Synchronization Marker (ASM) insertion, in accordance with CCSDS recommendations. The architecture is fully integrated and configurable, allowing dynamic selection of coding schemes without requiring structural modifications. The system is implemented on a modern FPGA platform with a 32-bit AXI4-Stream interface at 110 MHz, reaching an effective throughput of up to 1.76 Gbps. Experimental results demonstrate reliable timing with positive setup and hold margins, allowing the system to operate at approximately 130 MHz. Power consumption is measured using Switching Activity Interchange Format (SAIF)-based switching activity, providing a realistic estimate of programmable logic power consumption. The total on-chip power is about 1.77 W for individual coding modes. It rises to 1.91 W in the concatenated setup, which is the worst-case scenario. The results show that the proposed architecture efficiently uses resources, runs reliably at high speeds, and exhibits predictable power consumption. This makes it well suited for high-reliability and energy-constrained satellite communication systems. resources are used. Full article

To address the issues of slow dynamic response and poor disturbance rejection in three-phase interleaved parallel buck converters under disturbance conditions such as voltage or load transients, an improved sliding mode auto-disturbance rejection control (SM-ADRC) strategy is proposed. Firstly, the traditional ADRC algorithm suffers from reduced disturbance observation accuracy in the extended state observer (ESO) due to discontinuous switching of the nonlinear function at segment boundaries. To address this, a novel nonlinear function is designed using an interpolation fitting method. Concurrently, an improved ESO is constructed based on deviation-control principles, utilising the deviation between each state variable and its observed value. Secondly, an enhanced state error feedback law combines an improved exponential approach law with an integral sliding mode surface, thereby enhancing the control system’s robustness. Finally, simulation comparisons of output voltage fluctuations and power response speeds under various operating conditions validate the superiority and feasibility of the proposed SM-ADRC strategy over both the conventional ADRC strategy and PI control strategy. Full article

The integration of photovoltaic (PV) generation with bidirectional electric vehicle (EV) fast-charging systems offers a promising pathway toward sustainable transportation and grid support. However, the dynamic coupling between maximum power point tracking (MPPT) perturbations and grid-side power quality presents a fundamental challenge in such multi-converter architectures. This paper addresses this challenge through a coordinated design and optimization framework for a grid-connected, PV-assisted bidirectional off-board EV fast charger. The system integrates a 184.695 kW PV array via a DC-DC boost converter, a common DC link, a three-phase bidirectional active front-end rectifier with an LCL filter, and a four-phase interleaved bidirectional DC-DC converter for the EV battery interface. A comparative evaluation of three MPPT algorithms establishes the Fuzzy Logic Variable Step-Size Perturb & Observe (Fuzzy VSS-P&O) as the optimal strategy, achieving 99.7% tracking efficiency with 46 μs settling time. However, initial integration of this high-performance MPPT reveals system-level harmonic distortion, with grid current total harmonic distortion (THD) reaching 4.02% during charging. To resolve this coupling, an Artificial Bee Colony (ABC) metaheuristic algorithm performs coordinated optimization of all critical PI controller gains. The optimized system reduces grid current THD to 1.40% during charging, improves DC-link transient response by 43%, and enhances Phase-Locked Loop (PLL) synchronization accuracy. Comprehensive validation confirms robust bidirectional operation with seamless mode transitions and compliant power quality. The results demonstrate that system-wide intelligent optimization is essential for reconciling advanced energy harvesting with stringent grid requirements in next-generation EV fast-charging infrastructure. Full article

We present a checkerboard metasurface integrating interleaved Helmholtz resonator arrays with distinct geometrical parameters, enabling decoupled dual-band coherent perfect absorption (CPA) in both in-phase and anti-phase excitation conditions. Full-wave simulations confirm that the proposed structure achieves absorption rates exceeding 99% at 2.904, 3.024, 3.788 and 3.856 THz, corresponding to two pairs of resonant modes enabled by the asymmetric transmission characteristics. Notably, by actively manipulating the relative phase difference between the two excitation modes, the absorption frequencies associated with each CPA channel can be independently and continuously tuned. Benefiting from the planar checkerboard configuration, which combines compact geometry, suppressed mutual coupling, and balanced energy distribution, the metasurface achieves stable and independent dual-band absorption characteristics. The proposed design provides a promising pathway for the development of terahertz coherent absorbers with enhanced frequency stability and spectral flexibility of dual-mode operations, offering strong potential for practical photonic and electromagnetic applications. Full article

The manipulation of vector beams (VBs) with longitudinally variant polarization states is an important research topic and has potential applications in classical and quantum fields. In this study, we propose a half-wave plate dielectric metasurface composed of two interleaved sub-metasurfaces to generate longitudinally separated dual-channel vectorial structured light fields. The propagation and Pancharatnam–Berry phases are employed to construct hyperbolic, helical, and opposite gradient phases for focusing wavefronts, generating circularly polarized (CP) vortices, and deflecting CP vortices with the same chirality in opposite directions. Consequently, dual-channel higher-order or hybrid-order Poincaré (HOP or HyOP) beams are generated along the optical axis under elliptically polarized illumination, and their polarization states evolve along an arbitrary pair of antipodal meridians on the HOP or HyOP sphere by varying the ellipticity of the incident light, the propagation-phase topological charge, and the rotation order of the meta-atom. The consistency between the theoretical and simulated results demonstrates the feasibility and practicability of the proposed method. This study is significant for compact, integrated, and multifunctional optical devices, and provides an innovative strategy to extend optical field manipulation from two-dimensional to three-dimensional space. Full article

Electric vehicle (EV) chargers play an important role in the popularity of electric vehicles. In order to improve the efficiency of EV chargers, this paper replaces the discrete inductors in an interleaved Boost PFC topology with a coupled inductor. Theoretical analysis of the Boost PFC topology was presented, and the coupled inductor was designed, with simulation verification. Experimental testing of the designed coupled inductor was done on a 7 kW EV charger platform. The experimental results show that the designed coupled inductor can improve the efficiency of an EV charger. Full article

Passenger fuel cell vehicles (FCVs) require high-gain DC/DC converters to achieve voltage matching between the low-power fuel cell (FC) stack (50–200 V) and the vehicle DC bus (400–800 V). To address the challenges in existing step-up DC/DC converters in relation to balancing the requirements of high voltage gain, wide input voltage range, low input current ripple and voltage stress, the common ground of input–output, and high efficiency in passenger FCV applications, this paper proposes three types of high-gain DC/DC converters based on an interleaved structure, incorporating quadratic Boost, quasi-Z source, and switched-inductor impedance networks. These designs effectively balance the scenario requirements of passenger FCVs. Meanwhile, taking one of the proposed converters (Interleaved-Quadratic Boost; I-QB) as an example, its steady-state performance such as voltage gain is analyzed and compared in detail with existing voltage step-up DC/DC converters. Furthermore, a scaled-down SiC-based experimental platform is constructed. Steady-state experiments validate the converter’s maximum voltage step-up capability of ten times, wide input voltage range of 30–80 V, input current ripple of less than 0.3 A, and low voltage stress on devices (≤U_o/2), thereby confirming the feasibility of these converters and the correctness of the performance analysis. The dynamic experimental results indicated that under input voltage step changes of 50–80 V and 100–50% load step changes, the I-QB converter exhibits a minor voltage overshoot with settling time under 200 ms. The prototype achieves a peak efficiency of 94.2%, confirming these converters’ suitability for passenger FCV powertrains. Full article

Electric vehicles (EVs) employ high-voltage battery systems to improve drivetrain efficiency, while numerous auxiliary loads still require low-voltage power supplies, typically at 12 V. This creates a demand for isolated DC–DC auxiliary power modules (APMs) with high step-down ratios, wide operating ranges, and high energy conversion efficiency. In this paper, a high-efficiency DC–DC converter based on an input-series output-parallel (ISOP) LLC resonant architecture is proposed for EV auxiliary power applications. The proposed converter adopts dual LLC modules connected in an ISOP configuration to distribute stress, reduce the transformer turns ratio, and inherently achieve output current sharing. Full-bridge and half-bridge LLC operating modes are combined with hybrid pulse-frequency modulation (PFM) and phase-shift modulation (PSM) control strategies to enable wide voltage operation while maintaining soft-switching characteristics. A two-phase interleaved scheme further suppresses output current ripple. A 1000 W prototype demonstrates stable operation over 200–400 V input and 10–16 V output ranges with a peak efficiency of 97.87%. In this paper, PSM denotes phase-shift modulation, defined as the intentional delay between primary-side switching legs for power regulation. Full article

The use of appropriate learning strategies that accommodate working memory capacity is crucial for successful long-term learning. To our knowledge, there is little evidence in the literature showing which learning strategies STEM students use and their perceived effectiveness of these strategies. This paper addresses this gap by applying a mixed-methods design to gain insight into STEM students’ learning behaviour in terms of the use and perceived effectiveness of available learning strategies. Specifically, we collected quantitative scoping survey data, complemented by qualitative focus group data to gain a rich, holistic understanding of students’ perceptions and rationales for using learning strategies. Students rated content blocking and problem-solving attempts as more effective than interleaving and using worked examples, respectively. Students differentiated their use of different learning strategies, using more worked examples than problem-solving attempts and more rereading than retrieval practice. Additionally, the extent to which they used a strategy was positively correlated with their knowledge about its effectiveness. Our data also show that the use of both highly and moderately effective learning strategies positively predicted grades. The focus group findings highlighted the complexity of learning behaviour in that students used a variety of learning strategies, depending on their learning habits, the nature of their courses, their motivation and interests. Students evaluated the effectiveness of a strategy based on whether it improved their grades and by the combination of perceived and actual effort required to use it. Overall, STEM students have limited knowledge of learning strategies and ultimately need support to engage with their learning in an efficient and productive way. Full article

This paper proposes a single-stage three-phase AC-DC converter based on an LLC resonant topology utilizing a front-end matrix switch. Unlike traditional two-stage solutions, the proposed topology synthesizes a fluctuating equivalent DC voltage from the three-phase input, achieving direct power conversion with high efficiency. To maintain a stable DC output voltage against the time-varying input, a trajectory-based Pulse Frequency Modulation (PFM) control strategy is developed. By employing State-Plane Analysis (SPA), the operational trajectory is divided into four calculation segments, allowing precise derivation of the switching frequency and duty cycles for both boost and buck modes within a single line cycle. Furthermore, to improve power density and reduce parasitic parameters, a high-frequency planar inductor with interleaved windings and a planar transformer are designed for 500 kHz operation. A pipeline control architecture based on a single DSP is implemented to handle the complex real-time computations. A 500 W prototype is built and tested under 100 V input and 130 V output conditions. Experimental results demonstrate that the converter achieves a peak efficiency of 97%, a power factor of 0.99, and a grid current Total Harmonic Distortion (THD) of 3.95%, validating the effectiveness of the proposed topology and control scheme. Full article