Research on Improved Technology of Totem-Pole Bridgeless PFC Circuit Based on Triangular Current Mode

Abstract

The totem-pole bridgeless power factor correction (PFC) circuit based on the triangular current mode (TCM) in the front-end PFC of a switching power supply has the advantage of realizing zero-voltage switching (ZVS) in the full working range. However, the TCM control based on the critical conduction mode (CRM) further increases the inductance current ripple, and the traditional input voltage AC sampling circuit increases the circuit complexity and device cost. Therefore, this paper studies the corresponding improvement technology from two dimensions. Firstly, the coordinated interleaved parallel technology is employed to design the system’s overall control-improvement strategy. This approach not only achieves full working-range ZVS but also reduces both the inductor current ripple and power device stress. Simultaneously, an optimized input voltage sampling circuit is designed to accommodate varying voltage requirements of control chip pins. This circuit demonstrates strong synchronization in both voltage and phase sampling, and the structural characteristics of the optocoupler can also suppress electrical signal interference. Finally, a 600 W totem-pole bridgeless PFC prototype is developed. The experimental results demonstrate the effectiveness of the proposed improved method. The prototype efficiency peak reaches 97.3%.

1. Introduction

A switching mode power supply (SMPS) is a power supply device that converts input power into stable output power through the rapid on and off of high-frequency switching devices. Its core principle involves regulating the duty cycle of switching devices, followed by energy transfer and filtering through inductive and capacitive energy-storage elements, thereby enabling efficient power conversion.

SMPSs have emerged as the predominant power supply solution for modern electronic devices, finding widespread applications in communication systems, renewable energy systems, and consumer electronics, as illustrated in Figure 1 [1,2].

Figure 2 shows the typical structure of an SMPS, consisting of a former AC/DC stage followed by a latter DC/DC stage. The front stage converts the AC to high-voltage DC and dynamically adjusts the input current waveform to make the PF close to 1 to achieve power factor correction (PFC). DC/DC converts the high-voltage DC of the previous stage to isolated and stable low-voltage DC. This design takes into account high efficiency, power factor correction and stable output [3,4].

With the popularity of power electronic equipment, the problem of harmonic pollution in a power grid has become serious [5,6]. To enhance power system stability through improved power quality, numerous countries and international organizations have established various standards, including IEC 61000-3-2, GB/T 14549-1993, and IEEE 519 [7,8,9].

These standards strictly limit the harmonics contained in the input current of power electronic equipment when connected to the grid. As a core technology in modern power electronic system, PFC circuits play an irreplaceable role in power factor improvement, harmonic reduction, and energy efficiency enhancement. Currently, active PFC topologies have become the industry standard solution. The dynamic current waveform control is realized by introducing MOSFET, IGBT, and other high-frequency switching devices [10].

Table 1 provides a comprehensive comparison of various boost PFC rectifier topologies. The totem-pole bridgeless PFC circuit has become a popular topology due to its simple topology, low conduction loss, and common mode interference, which is conducive to achieving higher efficiency and power density [3,11,12,13,14,15].

The performance characteristics of totem-pole bridgeless PFC converters are strongly dependent on their inductor current modulation strategies. Based on the characteristic state of the inductor current during switching cycles, the operation modes can be classified into continuous conduction mode (CCM), discontinuous conduction mode (DCM), and critical conduction mode (CRM). Table 2 presents a comparison of these three operating modes.

Under CCM, the inductor current remains non-zero throughout the entire switching cycle, and the switching devices operate with continuous current flow. This mode exhibits low total harmonic distortion (THD) and reduced current ripple characteristics. However, the Si MOSFET has severe defects of diode reverse recovery characteristics, which makes the circuit difficult to operate stably. Hard switching loss is positively correlated with the switching frequency, which limits the maximum operating frequency of CCM. Compared with CCM, critical conduction mode (CRM) can reduce the inductance current to zero, realize zero-voltage switching (ZVS) through resonance, and reduce the switching loss. Under DCM, the inductor current decays to zero within each switching cycle, achieving natural zero-current switching (ZCS) turn-off. This inherent characteristic eliminates diode reverse recovery issues, thereby maintaining reliable operation even with conventional silicon-based devices. But DCM input current is intermittent, leading to increased harmonic distortion and a reduced power factor. And the inductance current ripple is significant, which adds difficulty to the filter design. Compared with DCM, CRM has better harmonic performance and a higher PF value. Therefore, CRM totem-pole bridgeless PFC converters have emerged as the predominant solution for high-efficiency, high-power-density applications.

However, CRM has inherent constraints: the converter operates with variable switching frequency control, resulting in relatively complex control-methodology implementation. ZVS is achievable when U_in ≤ 0.5U_o. However, for U_in > 0.5U_o, only the valley switching (VS) operation is possible, indicating that full-range ZVS cannot be realized [16,17,18].

Table 1. Comparison of different boost PFC rectifier topologies [18].

Topology	SD	M	FD	L	Co	Tot. Num
Conventional single switch	4	1	1	1	1	8
Dual boost bridgeless	2	2	2	2	1	9
Bi-directional bridgeless	2	2	2	1	1	8
totem-pole bridgeless	2	2	0	1	1	6

SD: slow diodes; M: MOSFETs; FD: fast diodes; L: input inductors; C_o: output capacitors.

Table 1. Comparison of different boost PFC rectifier topologies [18].

Topology	SD	M	FD	L	Co	Tot. Num
Conventional single switch	4	1	1	1	1	8
Dual boost bridgeless	2	2	2	2	1	9
Bi-directional bridgeless	2	2	2	1	1	8
totem-pole bridgeless	2	2	0	1	1	6

SD: slow diodes; M: MOSFETs; FD: fast diodes; L: input inductors; C_o: output capacitors.

Table 2. Comparison of CCM, CRM, and DCM operation modes.

Comparative Elements	CCM	CRM	DCM
Inductor current	Continuous	Critical conduction	Discontinuous
Control methodology	Fixed frequency	Variable frequency	Fixed frequency/Variable frequency
Current ripple	Small	Relatively large	Large
Peak current	Small	Medium	Large
RMS current	Small	Medium	Large
Switching state	Hard switching	Soft switching	Soft switching

Table 2. Comparison of CCM, CRM, and DCM operation modes.

Comparative Elements	CCM	CRM	DCM
Inductor current	Continuous	Critical conduction	Discontinuous
Control methodology	Fixed frequency	Variable frequency	Fixed frequency/Variable frequency
Current ripple	Small	Relatively large	Large
Peak current	Small	Medium	Large
RMS current	Small	Medium	Large
Switching state	Hard switching	Soft switching	Soft switching

To further enhance the efficiency and power factor of totem-pole PFC converters, numerous domestic and international scholars have conducted extensive research and improvements based on these three fundamental modulation modes.

The advent of wide-bandgap (WBG) devices has expanded the applications of totem-pole PFC topologies and facilitated innovative integration with modulation schemes. Ref. [19] implemented a CCM totem-pole bridgeless PFC rectifier using SiC devices, achieving a peak efficiency of 98.6%. Ref. [20] presents a complete 6.6 kW on-board charger (OBC) system utilizing hybrid SiC/GaN power devices, achieving a power density of 37 W/in³ with >96% peak efficiency. Ref. [21] proposed a 6.6 kW bidirectional SiC-based LLC charger featuring an interleaved CCM totem-pole bridgeless PFC front-end and a wide-ZVS-range, magnetically integrated 300 kHz LLC converter, achieving 96% peak discharge efficiency at full load. Ref. [13] developed an 800 W GaN-based CCM bridgeless totem-pole PFC prototype with 98% efficiency.

Control-strategy optimization has also emerged as a key research focus. Ref. [22] introduced interleaving techniques into a GaN HEMT-based CRM totem-pole bridgeless PFC circuit, realizing a 1.2 kW interleaved boost PFC converter prototype with 97.9% peak efficiency. Building upon CRM operation, Ref. [18] proposed a ZVS range-extension method termed triangular current mode (TCM) control. When U_in > 0.5U_o, the rectifier switch remains conducting after the inductor current reaches zero, extending its on-time to ensure sufficient energy storage for complete MOSFET junction capacitance discharge, thereby achieving full-range ZVS without auxiliary circuits. To improve the wide-load-range efficiency in high-frequency SiC-based boost converters, Ref. [23] developed a hybrid TCM–DCM current mode. At the rated load, TCM enables zero-voltage switching. At the same time, light-load conditions employ a TCM–DCM hybrid operation where TCM current pulses are generated during DCM zero-current intervals, simultaneously achieving ZVS and current ripple reduction for maintained high efficiency across load variations.

However, TCM control still has some deficiencies:

• The inductance current ripple is larger in CRM, and the TCM control makes the inductance current ripple further increase;
• Power devices bear higher current stress, and inductors need to adopt larger core sizes to avoid saturation and power density reduction.

Therefore, Ref. [16] integrated the TCM control with interleaving technology, achieving full-range ZVS while further reducing the inductor current ripple, with a peak efficiency of 96.9%. However, this approach requires coordinated control between a DSP and FPGA. Similarly, even for single-phase TCM control, the implementation in ref. [17] necessitates combined DSP and CPLD control. Furthermore, the control scheme in ref. [24] requires additional sampling of the actual inductor current value, which increases system complexity in terms of current sensing.

In addition, the 220 VAC input voltage sampling circuit mainly samples its phase and numerical information. It is necessary to construct the sampling circuit separately, which increases the structural complexity. Furthermore, to meet the requirements of the input voltage threshold range of the analog-to-digital converter (ADC) pin of the control chip, the additional bias voltage of the sampling circuit is required, which increases the workload of the auxiliary power supply design.

To address these challenges, this paper proposes an improved TCM-based control strategy for totem-pole bridgeless PFC circuits that incorporate interleaving technology while utilizing only a single STC32F12K54 control chip. The proposed approach eliminates the need for precise inductor current sampling while achieving ZVS across the entire operating range and significantly reducing inductor current ripple. An optimized AC voltage sampling circuit is designed to concurrently perform two critical functions: precise measurement of both the input voltage amplitude and phase, and the optocoupler structure incorporated optocoupler architecture provides inherent immunity to electrical interference. The design principle of the sampling optimization circuit is universal and can meet the requirements of different control chips for pin input voltage.

This paper is organized as follows: Section 2 analyzes the topology and working mode of the TCM totem-pole bridgeless PFC circuit, studies the two-phase interleaving technology, and constructs the overall improved control architecture of the circuit. Section 3 details the optimized AC voltage sampling circuit design, with a theoretical analysis of its working principles and performance benefits. Section 4 carries out a simulation test on and experimental verification of the circuit to verify the correctness of the improved control method. Section 5 summarizes the research work and results.

2. Research on Improvement Technology of Circuit Control Strategy

2.1. Working Principle of Circuit Based on TCM

Figure 3 shows the topology of the totem-pole bridgeless PFC. U_in denotes the input voltage; L represents the boost inductance; D₁ and D₂ are the body diodes of the high-frequency switches S₁ and S₂, respectively; and C_oss1 and C_oss2 (where C_oss1 = C_oss2 = C_oss) are the junction capacitance of S₁ and S₂, respectively. S₃ and S₄ are power frequency switches, C_o is the output filter capacitance, and R_L is the load resistance. Figure 3 shows the operation mode of the circuit in a high-frequency switching cycle with a positive power frequency half cycle. Figure 4 shows the corresponding characteristic waveform.

A detailed analysis of the circuit’s operational modes and associated waveforms is presented below:

Stage I [t₀, t₁]: Positive energy storage stage. At t₀, the voltage at S₂ end of the main control switch tube is zero, driving S₂ to realize zero-voltage turn-on. U_in is applied to L, and the inductance current i_L rises linearly. Once the current i_off or the conduction time T_on of S₂ is reached, S₂ is turned off, marking the end of this stage.

Stage II [t₁, t₂]: Positive resonance stage. At t₁, S₂ is turned off, and L resonates with the junction capacitors C_oss1 and C_oss2 of S₁ and S₂. During resonance, the inductive current flows continuously through the synchronous rectifier S₁. The inductive current charges C_oss2 and discharges C_oss1. Until t₂, the voltage at both ends of C_oss2 is U_o, and this stage ends.

Stage III [t₂, t₃]: Follow-up stage. At t₂, the voltage at both ends of C_oss1 drops to 0 and S₁ turns on in reverse. i_L flows continuously through S₁, i_L decreases linearly until t₃, and i_L drops to zero. This mode ends.

Stage IV [t₃, t₄]: Reverse recovery stage. At t₃, S₁ is conducting in the forward direction and i_L is conducting in the reverse direction under the control of the drive signal.

When U_in ≤ 0.5U_o, S₂ can be ZVS even if it does not go through this stage. Therefore, S₁ is turned off immediately at t₃.

When U_in > 0.5U_o, i_L is 0 at t₃, and S₁ needs to be turned on for an additional period under certain conditions. At this time, i_L increases negatively, storing energy in the reverse direction.

Stage V [t₄, t₅]: Reverse resonance stage.

If U_in ≤ 0.5U_o, S₁ is turned off at t₃, C_oss1 and C_oss2 are resonant with L, C_oss1 is charged, and C_oss2 is discharged. At t₅, the voltage U_DS2 at both ends of C_oss2 drops to 0, and ZVS can be realized.

If U_in > 0.5U_o, under conventional control, S₁ does not prolong its conduction period and turns off precisely at t₃. Following resonance among C_oss1, C_oss2, and inductance L, U_DS2(t₅) = 2U_in – U_o, unable to drop to 0, and S₂ can only achieve valley switching at t₅.

Under the control of TCM, S₁ remains conducting for an additional period. At t₄, the auxiliary tube S₁ is turned off, and resonance initiates among C_oss1, C_oss2, and L. The inductor has enough energy to charge C_oss1 and discharge C_oss2. Until t₅, the voltage at both ends of C_oss1 rises to bus voltage, U_DS2 at both ends of C_oss2 drops to zero, and this mode ends. It ensures that S₂ can realize ZVS.

This mode is similar to that in the forward resonant phase, except that the polarity of the inductance current is opposite.

Stage VI [t₅, t₆]: Body diode freewheeling stage. At t₅, the voltage at both ends of S₂ is zero. At this time, i_L(t) passes through the body diode D₂ of S₂, and the current increases. During this period, ZVS can be realized by turning on S₂ before the inductance current increases to 0. End this mode at t₆ and enter the next switching cycle.

The planar trajectory diagram of the i_LZ_n-U_DS2 phase at U_in > 0.5U_o and U_in ≤ 0.5U_o obtained through time domain modal analysis and theoretical model derivation is shown in Figure 5. This curve can more intuitively show the working states in the switching cycle.

When U_in ≤ 0.5U_o, as shown in Figure 5a, in stages I, III, and VI, the homogeneity of the inductance current increases or decreases. During stages II and V, the inductance resonates with the switch junction capacitance. This resonance reduces U_DS2 to 0, enabling natural ZVS of the power switch. When U_in > 0.5U_o, an additional TCM-controlled stage IV must be incorporated, as illustrated in Figure 5b, to achieve full-range ZVS operation. The red arrow trajectories in this figure represent the normal operating paths under respective conditions, while the blue arrow trajectory in Figure 5b indicates the critical path that just achieves ZVS in TCM.

From the i_LZ_n-U_DS2 state plane trajectory diagram in Figure 5, T_on1 and i_{SR_off} are set as unknown quantities, and the inductive current and time interval of the totem-pole PFC circuit at each stage can be deduced.

When U_in > 0.5U_o and U_in ≤ 0.5U_o, the derivation process of stages I~III is the same.

The inductance current i_off at the turn-off time of the main switch is as follows:

$$i_{off}={\displaystyle \frac{U_{in}{T}_{on1}}{L}}$$

(1)

The arc radius r_II in the resonance process of stage II is as follows:

$$r_{\mathrm{II}}=\sqrt{U_{in}^2+{\left({\displaystyle \frac{U_{in}{T}_{on1}{Z}_n}{L}}\right)}^2}$$

(2)

where characteristic impedance $Z_n=\sqrt{0.5L/C_{oss}}$.

The peak inductance current i_pk in stage II is as follows:

$$i_{pk}=\sqrt{{\left({\displaystyle \frac{U_{in}}{Z_n}}\right)}^2+{\left({\displaystyle \frac{U_{in}{T}_{on1}}{L}}\right)}^2}$$

(3)

The resonance time T_r1 of stage II can be obtained:

$$T_{r1}={\displaystyle \frac{{\theta }_{\mathrm{II}}}{{\omega }_0}}={\displaystyle \frac{1}{{\omega }_0}}\left(\arcsin {\displaystyle \frac{U_{in}}{\sqrt{U_{in}^2+{\left(\frac{U_{in}{T}_{on1}{Z}_n}{L}\right)}^2}}}+\arcsin {\displaystyle \frac{U_o-U_{in}}{\sqrt{U_{in}^2+{\left(\frac{U_{in}{T}_{on1}{Z}_n}{L}\right)}^2}}}\right)$$

(4)

where θ_II is the center angle of the circular arc during stage II resonance, and the resonant angular frequency ${\omega }_0=1/\sqrt{2L{C}_{oss}}$.

The inductance current i_{SR_on} when the boost rectifier is turned on is as follows:

$$i_{SR\_on}={\displaystyle \frac{\sqrt{r_{\mathrm{II}}^2-{\left(U_o-U_{in}\right)}^2}}{Z_n}}=\sqrt{{\displaystyle \frac{U_o\left(2U_{in}-U_o\right)}{Z_n^2}}+{\left({\displaystyle \frac{U_{in}{T}_{on1}}{L}}\right)}^2}$$

(5)

According to the principle of the voltage second balance of i_L, the conduction time T_SR1 of the boost rectifier in stage III can be calculated:

$$T_{SR1}=\sqrt{{\displaystyle \frac{U_o\left(2U_{in}-U_o\right)}{Z_n^2}}+{\left({\displaystyle \frac{U_{in}{T}_{on1}}{L}}\right)}^2}\cdot {\displaystyle \frac{L}{U_o-U_{in}}}$$

(6)

When U_in > 0.5U_o, the additional conduction time T_SR2 of the boost rectifier in stage IV is as follows:

$$T_{SR2}=-{\displaystyle \frac{i_{SR\_off}L}{U_o-U_{in}}}$$

(7)

Obtain the reverse resonance time T_r2 of stage V:

$$T_{r2}={\displaystyle \frac{{\theta }_{\mathrm{V}}}{{\omega }_0}}=\left\{\begin{array}{l}{\displaystyle \frac{1}{{\omega }_0}}\left(\arcsin {\displaystyle \frac{U_{in}}{U_o-U_{in}}}+{\displaystyle \frac{\pi }{2}}\right),U_{in}\le 0.5U_o\\ {\displaystyle \frac{1}{{\omega }_0}}\left(\arcsin {\displaystyle \frac{U_o-U_{in}}{\sqrt{{\left(i_{SR\_off}{Z}_n\right)}^2+{\left(U_o-U_{in}\right)}^2}}}+\arcsin {\displaystyle \frac{U_{in}}{\sqrt{{\left(i_{SR\_off}{Z}_n\right)}^2+{\left(U_o-U_{in}\right)}^2}}}\right),U_{in}>0.5U_o\end{array}\right.$$

(8)

where θ_V is the center angle of the stage V resonance process.

The inductance valley current i_val in stage V is as follows:

$$i_{val}=\left\{\begin{array}{l}{\displaystyle \frac{U_{in}-U_o}{Z_n}},U_{in}\le 0.5U_o\\ -\sqrt{i_{SR\_off}^2+{\left({\displaystyle \frac{U_o-U_{in}}{Z_n}}\right)}^2},U_{in}>0.5U_o\end{array}\right.$$

(9)

Calculate the opening time of the main switch, and the inductance current i_on is as follows:

$$i_{on}=\left\{\begin{array}{l}-{\displaystyle \frac{\sqrt{{\left(U_o-U_{in}\right)}^2-U_{in}^2}}{Z_n}}=-{\displaystyle \frac{\sqrt{U_o\left(U_o-2U_{in}\right)}}{Z_n}},U_{in}\le 0.5U_o\\ -{\displaystyle \frac{\sqrt{{\left(i_{SR\_off}{Z}_n\right)}^2+{\left(U_o-U_{in}\right)}^2-U_{in}^2}}{Z_n}}=-\sqrt{i_{SR\_off}^2+{\displaystyle \frac{U_o\left(U_o-2U_{in}\right)}{Z_n^2}}},U_{in}>0.5U_o\end{array}\right.$$

(10)

Same as formula (6), the duration T_on2 of the reverse conduction phase of the main switch in stage VI is derived.

$$T_{on2}=\left\{\begin{array}{l}{\displaystyle \frac{\sqrt{U_o\left(U_o-2U_{in}\right)}}{Z_n}}\cdot {\displaystyle \frac{L}{U_{in}}},U_{in}\le 0.5U_o\\ \sqrt{i_{SR\_off}^2+{\displaystyle \frac{U_o\left(U_o-2U_{in}\right)}{Z_n^2}}}\cdot {\displaystyle \frac{L}{U_{in}}},U_{in}>0.5U_o\end{array}\right.$$

(11)

Under TCM control, the i_{SR_off} and T_on1 formulas are further derived. In the positive half cycle of U_in, the turn-off current i_{SR_off} of the synchronous rectifier only needs to meet one condition:

$$i_{SR\_off}=-\sqrt{\max \left\{{\displaystyle \frac{U_o\left(2U_{in}-U_o\right)}{U_o-U_{in}}},0\right\}}$$

(12)

When U_in ≤ 0.5U_o, i_{SR_off} = 0, the rectifier tube does not need additional conduction. When U_in > 0.5U_o, the required additional conduction time T_{SR2_min} is as follows:

$$T_{SR2\_\min }={\displaystyle \frac{\sqrt{U_o\left(2U_{in}-U_o\right)}}{U_o-U_{in}}}\cdot \sqrt{2L{C}_{oss}}$$

(13)

In a switching cycle, the inductance charge per unit time is the average value of inductance current i_{L_avg}, assuming that the power factor PF = 1 and the overall efficiency is 1, then i_{L_avg} is as follows:

$$i_{L\_avg}=i_{ref}={\displaystyle \frac{\sqrt{2}{P}_o}{U_{in\_rms}}}\sin \left({\omega }_{line}t\right)$$

(14)

where ω_line = 2$\mathsf{\pi }$f_line, f_line is the input voltage frequency, taking the power frequency of 50 Hz.

The peak value i_pk of inductance current is as follows:

$$i_{pk}=2i_{L\_avg}-i_{val}$$

(15)

The inductance current i_off when the main switch S₂ is turned off is as follows:

$$i_{off}=\sqrt{i_{pk}^2-{\left({\displaystyle \frac{U_{in}}{Z_n}}\right)}^2}$$

(16)

From the characteristic impedance $Z_n=\sqrt{0.5L/C_{oss}}$ and the inductance current when the main switch S₂ is turned off, the S₂ conduction time T_on1 is obtained as follows:

$$T_{on1}={\displaystyle \frac{i_{off}L}{U_{in}}}$$

(17)

This section verifies the effectiveness of TCM control through a comprehensive analysis of the circuit’s operational principles, stage-by-stage waveforms, and corresponding phase-plane trajectory curves. And the main parameter formulas such as the time and current are derived. This lays the foundation for the subsequent control loop calculation.

2.2. Two-Phase Interleaved Parallel Control

The increased current ripple based on TCM control makes the power devices in the circuit bear higher instantaneous current stress. The inductor needs to adopt a larger core size to avoid saturation, which directly leads to the reduction of power density. Filter capacitors also need to handle larger ripple currents, increasing the volume and cost of capacitors [25,26]. Therefore, this paper will study the two-phase interleaved parallel technology in this section and introduce the circuit to reduce the inductance current ripple.

Figure 6 shows the topology of two-phase interleaved totem-pole bridgeless PFC. L₁ and switches S₁ and S₂ constitute boost module 1, while L₂ and switches S₃ and S₄ constitute boost module 2. The two modules present a 180° phase difference, and the current peaks and valleys of the two inductors alternate, so that the current ripple can partially offset each other and reduce the total inductance current ripple. When the power level is the same, each module bears half of the total power, reducing the inductance volume and the current stress borne by each device to achieve higher power density [27].

The waveforms of the switch voltage signal and inductance current of each interleaved parallel branch when duty cycle D ≤ 0.5 and D > 0.5 are shown in Figure 7. The voltages and driving signals of the two modules exhibit a half-cycle phase difference during the positive half-cycle period. The two inductive currents also have a phase difference of half a switching cycle. By superimposing two groups of inductive currents, the total inductive current i_L is obtained. From the figure, the total current ripple value Δi_L is significantly reduced.

Both the main-phase and slave-phase bridge arms share equal power distribution, with each bearing half of the total power. Based on this, the current ripple Δi_L1 and Δi_L2 of each phase inductance are the same as the current peak i_pk1 and i_pk2, including the following:

$$\Delta i_{L1}=i_{pk1}={\displaystyle \frac{U_{in}}{L_1}}D{T}_s={\displaystyle \frac{U_o-U_{in}}{L_1}}\left(1-D\right)T_s$$

(18)

In the formula, D represents the duty cycle of the corresponding main switch, and L₁ represents the inductance of one phase bridge arm. The inductance of two-phase bridge arm L₁ = L_2.

When D > 0.5, the duration of the rise in the current uniformity of the two inductors is (D − 0.5)T_S, and the total inductance current ripple Δi_L is as follows:

$$\Delta i_L=2{\displaystyle \frac{U_o-U_{in}}{L_1}}\left(0.5-D\right)T_s={\displaystyle \frac{U_o-U_{in}}{L_1}}\left(1-2D\right)T_s$$

(19)

When D ≤ 0.5, the duration of the decrease in the current uniformity of the two inductors is (0.5−D)T_S. The total inductor current ripple Δi_L is as follows:

$$\Delta i_L=2{\displaystyle \frac{U_{in}}{L_1}}\left(D-0.5\right)T_s={\displaystyle \frac{U_{in}}{L_1}}\left(2D-1\right)T_s$$

(20)

Suppose the transformation ratio k = Δi_L/Δi_L2, which is used to describe the quantitative relationship between the total inductance current ripple and the single-phase inductance current ripple under the condition of a two-phase interleaved parallel, then k is as follows:

$$k=\left\{\begin{array}{l}{\displaystyle \frac{1-2D}{1-D}},D\le 0.5\\ {\displaystyle \frac{2D-1}{D}},D>0.5\end{array}\right.$$

(21)

Figure 8 shows the ripple curve. Combining Equation (21) and Figure 7, by implementing the interleaved parallel control, the total inductance current ripple of the system is lower than the value of the inductance current ripple of any phase in the entire duty cycle variation range.

2.3. Control Implementation Strategy

The overall control idea of the system is to calculate the on signal T_{on_ac} and off signal T_{off_ac} of the main control switch S₂ and the on signal T_{on_sr} and off signal T_{off_sr} of the synchronous rectifier S₁ in combination with the corresponding time length of each mode deduced above. Then, the zero crossing detector (ZCD) signal is used as the reference trigger signal of each switch cycle, and the control is carried out according to the calculated opening and closing time of each switch tube.

Figure 9 shows the relationship between the inductance current and control signal in a switching cycle. Each control signal is as follows:

$$\left\{\begin{array}{l}{T}_{off\_sr}=T_{SR2}\\ T_{on\_ac}=T_{SR2}+T_{r2}\\ T_{off\_ac}=T_{SR2}+T_{r2}+T_{on2}+T_{on1}\\ T_{on\_sr}=T_{SR2}+T_{r2}+T_{on2}+T_{on1}+T_{r1}\end{array}\right.$$

(22)

Figure 10 is the overall control block diagram of the totem-pole bridgeless PFC circuit under improved control. The output voltage U_o of the circuit is different from the reference voltage U_ref, where U_ref = 400 V. The error voltage is multiplied by the output signal of the PI regulator and the phase signal of U_in to obtain the inductance current reference current i_ref, that is, the average inductance current i_{L_avg}. i_ref undergoes real-time computation using the sampled U_in and U_o to generate switching signals for both the high-frequency main control switch and rectifier. These signals can control the opening and closing of the main-phase high-frequency switches S₁ and S₂ at the specific time calculated in real time based on the ZCD signal. Since the switching period of the main phase continuously changes with the power frequency period, it is necessary to accurately determine the switching period T_S of the main-phase bridge arm tube through real-time sampling and calculation. The working process of the main phase is started by the ZCD signal ZCD-M of the main phase, while the slave phase begins operation after a time delay of T_S/2 relative to the main-phase turn-on instant.

The determination of the T_S/2 delay time depends on the previous switching cycle value of the main phase. After 1/2 switch cycle delay, the main circuit drive signal is synchronized with the slave circuit drive signal, and the specific control time of the opening and closing of the slave phase high-frequency switches S₃ and S₄ is equal to that of the main circuit. The sampling input voltage U_in numerical signal is combined with the U_in phase signal to control the opening and closing of power frequency switches S₅ and S₆. Finally, the PWM module in the microcontroller unit (MCU) is configured to generate the corresponding drive signal to control the opening and closing of switches.

3. Optimal Design of AC Input Voltage Sampling Circuit

PFC monitors the input voltage signal in real time for subsequent loop calculation and maintains the circuit operation. In addition, the control chip needs to detect whether the input voltage exceeds the limit through the input voltage sampling circuit, trigger the protection circuit to turn off the PWM, and prevent subsequent DC/DC and load damage. Therefore, a 220 VAC input voltage sampling circuit is the key link of system stability and performance optimization [28,29,30].

The traditional 220 VAC input voltage sampling circuit often needs to build a positive and negative half-cycle phase-detection circuit and a digital differential sampling circuit, which has a complex circuit structure. In addition, the external reference voltage of the control chip may fluctuate, and the signal sampling will introduce errors due to the change in the power supply voltage. Therefore, this paper selects the internal 1.19 V reference source of the control chip STC32F12K54 as the reference voltage. The output voltage range of the numerical sampling circuit should be strictly constrained to 0~1.19 V, which requires the auxiliary power supply to provide the additional offset voltage of the sampling circuit and offset the negative voltage to the positive voltage to meet the processing requirements of the processor. The auxiliary power supply is mainly responsible for converting the high voltage of the system into the stable low-voltage DC power required by the controller, sampling circuit, switch driver circuit, and other peripheral circuits. It needs to continuously supply power to the peripheral circuits when the equipment is working. Therefore, too many offset voltages with different values will increase the workload of the auxiliary power supply design [31,32,33].

To address these challenges, this paper proposes an optocoupler-based input voltage sampling circuit optimization. As illustrated in Figure 11, the designed circuit can simultaneously realize two sampling functions of the input voltage value and phase and has higher synchronization. The optimization scheme has multiple advantages:

• There is no electrical connection between the input and output of the optocoupler through optical signal transmission. The isolation voltage of the optocoupler is generally 1~5 kV to achieve electrical isolation, which can isolate the common ground interference between the high-voltage side of input sampling and the low-voltage side of signal processing, as well as a series of signal interference such as grid fluctuation, motor interference, and other common mode noise that may exist;
• The optimized circuit enhances the synchronization of the voltage value and phase signal, reduces the number of components, and reduces the material cost;
• This design greatly simplifies the design requirements for auxiliary power supply, and only a single +5 V power supply is required to meet all sampling requirements [34,35].

In the specific implementation, the digital sampling part of the input-voltage-sampling-optimization circuit adopts the resistance voltage division mode, and the sampling voltage AC− is connected to the ADC input pin of the MCU after proportional attenuation through the resistance voltage division circuit. Taking the selected control chip STC32F12K54 as an example, the voltage range at the input ADC pin can be set according to its ADC part external reference voltage source value or MCU internal reference voltage source value. This circuit selects the internal 1.19 V reference source as the reference voltage, so that the output amplitude of the numerical detection is strictly limited to the intermittent sinusoidal steamed bread wave within the range of 0~1.19 V.

In the phase-detection part, the sampling voltage AC is grounded through the diode, resistance and reverse diode, the reverse diode is connected in parallel to the optocoupler, the optocoupler output is connected to the triode, and its collector is connected to the +5 V voltage through the resistance. This collector output connects directly to the MCU’s ADC pin, utilizing the optocoupler’s switching characteristics to convert the AC voltage into a processed input signal via the diode rectifier network. The output end of the optocoupler adopts a common emitter triode circuit to convert the signal into a square wave signal with an amplitude of +5 V, which can be directly connected to the ADC pin of the MCU for phase identification.

The corresponding relationship of voltage waveforms of power frequency input voltage U_in, optocoupler input terminal voltage U₁, and optocoupler output terminal voltage U_{in_phase} is shown in Figure 12. The light-emitting tube at the input side of the optocoupler has a certain conduction threshold, such as the optocoupler PC817C used in the figure, which has a conduction threshold of about 1.2 V. Consequently, the optocoupler-extracted waveform information does not initiate from the zero level. However, when processing the 220 V RMS input voltage, the threshold voltage effect becomes negligible, enabling the accurate extraction of both period and phase information. Observing the U₁ and U_{in_phase} waveforms, the input and output of the optocoupler are reversed, that is; the rising edge of the output waveform is driven by the falling section of the input voltage. Because the collector is connected to the +5 V voltage through resistance, the top of the U_{in_phase} waveform is limited by the voltage, forming a flat top with an amplitude of 5 V [36].

The output waveform forms regular square wave characteristics, which is convenient for the MCU to accurately capture zero crossing and phase information. The phase detection only needs to detect the rising/falling edge of the level, which can be directly connected to the ADC pin of the MCU for extracting the phase and period information through the level or jump.

The key parameters of the optocoupler PC817C selected for this study are summarized in

Table 3. Key specifications of PC817C optocoupler.

Parameter	Value
Forward voltage drop	1.2 V
Rise time	4 μs
Fall time	3 μs
Output current	50 mA
Isolation voltage	5 kV

. All parameter values were obtained from the component datasheet. As evident from Table 3, the voltage rise and fall times of the optocoupler are significantly faster compared to the 0.02 s period of the line-frequency input voltage. Furthermore, the relatively low forward voltage drop setting will not adversely affect the overall voltage sampling accuracy.

4. Experiment and Discussion

Building upon the theoretical analysis of circuit-improvement techniques, this section validates the effectiveness of the improved control strategy and the proposed AC input voltage sampling circuit through comprehensive simulation and experimental verification.

The medium-power segment has strong adaptability. It can cover a variety of application requirements through parallel or derating use, reduce the R&D cost, and is conducive to the balance between efficiency and cost. The design parameters used in both simulation and experiments are identical, and

Table 4. Main design parameters of circuit.

Parameter	Value
Output power Po	600 W
Input voltage Uin_rms	220 V
Output voltage Uo	400 V
Maximum switching frequency fs_max	100 kHz
Input voltage frequency fline	50 Hz
Branch inductor L1 and L2	1 mH
Output capacitor Co	500 μF

shows the main design parameters of the circuit.

4.1. Simulation Analysis

To validate the proposed control optimization strategy, a complete system model is developed in MATLAB 2021a/Simulink based on the overall control framework presented in Figure 9, followed by a comprehensive analysis of the test results.

Figure 13 shows the overall waveform of a single inductor current at full load. The current envelope follows the sinusoidal variation of the U_in, showing the working characteristics of CRM.

Figure 14 shows the input voltage U_in, output voltage U_o, single inductance current amplification waveform, and the switching waveform U_GS2 and terminal voltage U_DS2 of the main switch S₂. The drain-source voltage U_DS2 of S₂ is the terminal voltage at both ends of S₂. The gate-source voltage U_GS2 of S₂ indicates the switching condition of S₂. There are differences between the simulation environment and the actual experiment. The actual threshold voltage of the switch driver needs to refer to the specific datasheet. In the simulation, U_GS2 is 1 V, indicating that a 1 V voltage is applied to the S₂ grid to drive S₂ on, and U_GS2 is 0 V, indicating that S₂ is in the off state. As shown in the figure, when either U_in > 0.5U_o or U_in ≤ 0.5U_o, U_GS2 rises from 0 V to 1 V only after U_DS2 drops to 0 V. This verifies that the TCM method achieves ZVS across the entire operating range, thereby reducing switching losses.

Figure 15 is the output voltage waveform. The U_o is stable at 400 V, and the voltage ripple is within 5%. Figure 16 shows the waveform of input voltage and current. The input voltage and input current have the same phase and a high sinusoidal degree, indicating that the system can effectively achieve power factor correction.

Figure 17a,b are the overall and amplified waveforms of the inductance current of the main phase and the slave phase, respectively. The inductance current waveforms of the two branches are presented in a staggered manner based on the same phase of the outer contour. The phase difference is half of the switching cycle, and the waveform characteristics maintain good consistency.

Figure 18 shows the waveforms of the branch current and total inductance current of two inductors. The branch inductor current exhibits a period of approximately 19.077 μs, with an intercurrent phase difference of about 9.522 μs, corresponding to half the current period. The ripple of the i_L is about 1 A, and the ripple of the one-phase inductance current is about 1.5 A. It can be seen that the ripple of the total inductance current after interleaving control is less than that of the inductance current of any branch, which thoroughly verifies the ripple-cancellation effect of the interleaving parallel technology based on TCM and proves the effective integration of the improved control technology.

4.2. Empirical Test

Figure 19 is the prototype of the designed totem-pole bridgeless PFC. Based on the system control framework constructed in Figure 10, the overall program flow chart of digital control software for the circuit is shown in Figure 20. The main program is mainly responsible for initializing and setting the system, peripherals, and variables. After completing the configuration, initialize all modules, activate the timer, and wait for interruption.

After the system triggers the interrupt, first read the sampling signal to determine whether the input voltage value is within the set dead band threshold. If it is, turn off the switch. If it is not, further determine the positive and negative half cycles of the input voltage. Next, the loop calculation is carried out to calculate the opening and closing time and switching cycle of the main switch tube and the synchronous rectifier tube, update the PWM output, and finally exit the interrupt and run the interrupt program once. To avoid the influence of signal jitter on the accuracy of level reading in the process of sampling signal extraction, the MCU can read several times and take most of the results as the reading results to eliminate jitter. The fast interruption of each switching cycle is triggered by the ZCD signal.

Figure 21a shows the measured input voltage and current waveforms. The i_in filtered by the LC circuit is sinusoidal and in phase with the U_in, realizing the power-factor-correction function of the circuit. Figure 21b shows the measured output voltage waveform at full load at 220 VAC. To better visualize the ripple characteristics of U_o, the oscilloscope’s central axis was calibrated to represent a 300 V DC offset voltage reference during measurements. The U_o is stable at 400 V, and the voltage ripple is ≤5% U_o, which is 20 V.

According to the plane trajectory curve of the i_LZ_n-U_DS2 state in Figure 5, TCM control is not necessary when U_in ≤ 0.5U_o. When the inductance current drops to 0, the rectifier tube is not required to extend the conduction time, and the system can realize ZVS naturally. Therefore, it is essential to test the implementation of ZVS with TCM control when U_in > 0.5U_o. If ZVS can still be realized in this case, it can be further considered that the circuit can realize ZVS in the full operating range.

Figure 22 presents the measured waveforms under 220 VAC input conditions with U_in > 0.5U_o, showing the single-phase inductor current i_L1 along with the gate-source voltage U_GS2 of the main control switch S₂ and the drain-source voltage U_DS2 of the main control switch S₂. After the inductance current passes 0, the synchronous rectifier S₁ is extended and turned off, so that the voltage resonance at the junction capacitor C_oss2 end of S₂ is 0. After the voltage U_DS2 at S₂ end is reduced to 0, S₂ is turned on again, and ZVS is realized.

The waveforms of input voltage U_in and two-phase inductive currents i_L1 and i_L2 are shown in Figure 23a. Under the interleaving control, the current envelope of the two-phase inductors is sinusoidal, the phase is consistent with the input voltage, and the value is uniform. Figure 23b shows the two-phase inductance current amplification waveform. The inductor currents in both branches exhibit a period of approximately 28.9 μs, with a phase difference of about 14.5 μs between them—corresponding to half of the current period. By employing 180° interleaved phase control, the system achieves a significant reduction in the total inductor current ripple.

The input voltage and current were connected as one channel pair, while the output voltage and current were connected as another channel pair to the power analyzer, enabling direct measurement of input power P_in, output power P_o, and apparent power S. These measurements allowed the subsequent calculation of both the circuit efficiency η and power factor PF. Figure 24a shows the efficiency η of the prototype. The peak efficiency is 97.3%, and the efficiency at full load is 97.1%. Figure 24b shows the PF of the circuit. Under rated operating conditions, the converter maintains a PF above 0.99, thereby achieving power factor correction functionality.

The test results verify the effectiveness and synergy of the improved strategy, and the test waveform can be presented correctly. At the same time, it also shows the correctness of the optimization design principle of the U_in sampling circuit.

Table 5. Comparisons of the proposed method and existing methods.

Article	Single-Phase/Interleaved	The iL Needs to Be Sampled	Controller	Rated Power	Peak Efficiency
[24]	Single-phase	Yes	DSP	1.6 kW	99%
[17]	Single-phase	No	DSP + CPLD	3 kW	98.3%
[18]	Single-phase	No	Unknown	350 W	98.4%
[16]	Interleaved	No	DSP + FPGA	200 W	96.9%
Proposed	Interleaved	No	MCU	600 W	97.3%

provides a comparison between the proposed improved control approach and existing control strategies for TCM totem-pole bridgeless PFC converters. The converter topologies presented in [17,18,24] are restricted to single-phase configurations with [24] further requiring dedicated inductor current sensing and those in [16,17] employing complex dual-controller coordination schemes; the proposed converter architecture offers advantages through its single-controller implementation, elimination of current sampling requirements, and inherent current ripple-reduction capability enabled by interleaved parallel operation.

5. Conclusions

This paper mainly studies the defects of the totem-pole bridgeless PFC circuit based on TCM mode and makes a systematic improvement to research from the two dimensions of integrating interleaving technology and input AC voltage sampling optimization. Aiming at the problem that the TCM control based on CRM mode further increases the current ripple of the inductor, which leads to the increase in the stress of the power device and the increase in the size of the inductor, the interleaving parallel technology is integrated to solve the proposed defects based on realizing the full-working-range ZVS. Furthermore, addressing the limitation of conventional AC input voltage sampling circuits that require separate phase and magnitude sampling circuits, this paper designed an optimized sampling circuit that adapts to various control chip pin voltage requirements. This improved design enhances synchronization between the voltage phase and magnitude measurements while reducing the component count, with the incorporated optocoupler providing additional electrical isolation. The experimental results show that the improved method can effectively reduce the inductance current ripple based on the full-operating-range ZVS, and the effectiveness of the results can also verify the correctness of the design principle of the sampling optimization circuit.

However, the characteristic parameters of the proposed optocoupler-based input voltage sampling circuit—including response time, noise immunity, and phase error—are of critical importance, yet experimental testing of these parameters has not been conducted in the current study. We will address this limitation in our subsequent work by performing comprehensive experimental characterization of the proposed circuit.