Search Results (2,345)

Fault diagnosis technology is a crucial technique for ensuring the reliability of multiprocessor systems. Many previous studies have paid close attention to the permanent faults of systems while ignoring the rise of intermittent faults. Meanwhile, there is a lack of a rapid diagnostic algorithm tailored for intermittent faults. In this paper, we propose multiple theorems to evaluate the intermittent fault diagnosability of different topologies under the $PMC$ model. Through these theorems, we demonstrate that the intermittent fault diagnosability of an n-dimensional augmented cube ($A{Q}_n$) is $(2n-2)$ when n is greater than or equal to 4. Furthermore, we present a fast intermittent fault diagnosis algorithm, which is named as $IFDA$, to identify the processors with intermittent fault in the networks. Finally, we evaluate the performance of the algorithm in terms of the parameters Accuracy and Precision. The simulation experimental results show that the algorithm $IFDA$ has good performance and efficiency. Full article

Supervisory control theory (SCT), based on Petri nets, offers a robust framework for modeling and controlling discrete-event systems but faces significant challenges in scalability, expressiveness, and practical implementation. This paper introduces General-purpose Petri Net Simulator and Real-Time Controller (GPenSIM), a MATLAB version 24.1.0.2689473 (R2024a) Update 6-based modular Petri net framework, as a novel solution to these limitations. GPenSIM leverages modular decomposition to mitigate state-space explosion, enabling parallel execution of weakly coupled Petri modules on multi-core systems. Its programmable interfaces (pre-processors and post-processors) extend classical Petri nets’ expressiveness by enforcing nonlinear, temporal, and conditional constraints through custom MATLAB scripts, addressing the rigidity of traditional linear constraints. Furthermore, the integration of GPenSIM with MATLAB facilitates real-time control synthesis, performance optimization, and seamless interaction with external hardware and software, bridging the gap between theoretical models and industrial applications. Empirical studies demonstrate the efficacy of GPenSIM in reconfigurable manufacturing systems, where it reduced downtime by 30%, and in distributed control scenarios, where decentralized modules minimized synchronization delays. Grounded in systems theory principles of interconnectedness, GPenSIM emphasizes dynamic relationships between components, offering a scalable, adaptable, and practical tool for supervisory control. This work highlights the potential of GPenSIM to overcome longstanding limitations in SCT, providing a versatile platform for both academic research and industrial deployment. Full article

This work investigates the effects of radiation on FinFET-based full adders, which are crucial components of arithmetic units, particularly in aerospace and space applications. While FinFETs offer significant advantages, they remain susceptible to single-event transients (SETs) induced by radiation, which can cause computational errors. We assess three circuit-level mitigation techniques against SETs in FinFET adders: decoupling cells (DCELLs), transistor sizing (TS), and a combined approach incorporating both methods. Our results demonstrate that the most sensitive nodes and critical vectors in the adders vary depending on the mitigation strategy, underscoring their impact on overall radiation resilience. By analyzing these techniques alongside critical node evaluation, we identify their advantages and limitations, providing insights to enhance the robustness of FinFET-based processors in radiation-prone environments. Full article

Terahertz (THz) communications and simultaneous wireless information and power transfer (SWIPT) hold the potential to energize battery-less Internet-of-Things (IoT) devices while enabling multi-gigabit data transmission. However, severe path loss, blockages, and rectifier nonlinearity significantly hinder both throughput and harvested energy. Additionally, high-power THz beams pose safety concerns by potentially exceeding specific absorption rate (SAR) limits. We propose a sensing-adaptive power-focusing (APF) framework in which a reconfigurable intelligent surface (RIS) embeds low-rate THz sensors. Real-time backscatter measurements construct a spatial map used for the joint optimisation of (i) RIS phase configurations, (ii) multi-tone SWIPT waveforms, and (iii) nonlinear power-splitting ratios. A weighted MMSE inner loop maximizes the data rate, while an outer alternating optimisation applies semidefinite relaxation to enforce passive-element constraints and SAR compliance. Full-stack simulations at 0.3 THz with 20 GHz bandwidth and up to 256 RIS elements show that APF (i) improves the rate–energy Pareto frontier by 30–75% over recent adaptive baselines; (ii) achieves a 150% gain in harvested energy and a 440 Mbps peak per-user rate; (iii) reduces energy-efficiency variance by half while maintaining a Jain fairness index of 0.999;; and (iv) caps SAR at 1.6 W/kg, which is 20% below the IEEE C95.1 safety threshold. The algorithm converges in seven iterations and executes within <3 ms on a Cortex-A78 processor, ensuring compliance with real-time 6G control budgets. The proposed architecture supports sustainable THz-powered networks for smart factories, digital-twin logistics, wire-free extended reality (XR), and low-maintenance structural health monitors, combining high-capacity communication, safe wireless power transfer, and carbon-aware operation for future 6G cyber–physical systems. Full article

This paper presents a novel metascheduling algorithm to enhance communication efficiency in off-chip time-triggered multi-processor system-on-chip (MPSoC) platforms, particularly for safety-critical applications in aerospace and automotive domains. Time-triggered communication standards such as time-sensitive networking (TSN) and TTEthernet effectively enable deterministic and reliable communication across distributed systems, including MPSoC-based platforms connected via Ethernet. However, their dependence on static resource allocation limits adaptability under dynamic operating conditions. To address this challenge, we propose an offline metascheduling framework that generates multiple precomputed schedules corresponding to different context events. The proposed algorithm introduces a selective communication strategy that synchronizes context information exchange with key decision points, thereby minimizing unnecessary communication while maintaining global consistency and system determinism. By leveraging knowledge of context event patterns, our method facilitates coordinated schedule transitions and significantly reduces communication overhead. Experimental results show that our approach outperforms conventional scheduling techniques, achieving a communication overhead reduction ranging from 9.89 to 32.98 times compared to a two-time-unit periodic sampling strategy. This work provides a practical and certifiable solution for introducing adaptability into Ethernet-based time-triggered MPSoC systems without compromising the predictability essential for safety certification. Full article

In order to meet the needs for the rapid detection of crop growth and support variable management in farmland, an intelligent chlorophyll content in cotton leaves (CCC) detection system based on hyperspectral imaging (HSI) technology was designed and developed. The system includes a near-infrared (NIR) hyperspectral image acquisition module, a spectral extraction module, a main control processor module, a model acceleration module, a display module, and a power module, which are used to achieve rapid and non-destructive detection of chlorophyll content. Firstly, spectral images of cotton canopy leaves during the seedling, budding, and flowering-boll stages were collected, and the dataset was optimized using the first-order differential algorithm (1D) and Savitzky–Golay five-term quadratic smoothing (SG) algorithm. The results showed that SG had better processing performance. Secondly, the sparrow search algorithm optimized backpropagation neural network (SSA-BPNN) and one-dimensional convolutional neural network (1DCNN) algorithms were selected to establish a chlorophyll content detection model. The results showed that the determination coefficients $R_p^2$ of the chlorophyll SG-1DCNN detection model during the seedling, budding, and flowering-boll stages were 0.92, 0.97, and 0.95, respectively, and the model performance was superior to SG-SSA-BPNN. Therefore, the SG-1DCNN model was embedded into the detection system. Finally, a CCC intelligent detection system was developed using Python 3.12.3, MATLAB 2020b, and ENVI, and the system was subjected to application testing. The results showed that the average detection accuracy of the CCC intelligent detection system in the three stages was 98.522%, 99.132%, and 97.449%, respectively. Meanwhile, the average detection time for the samples is only 20.12 s. The research results can effectively solve the problem of detecting the nutritional status of cotton in the field environment, meet the real-time detection needs of the field environment, and provide solutions and technical support for the intelligent perception of crop production. Full article

In the wide range of human diseases, Parkinson’s disease (PD) has a high incidence, according to a recent survey by the World Health Organization (WHO). According to WHO records, this chronic disease has affected approximately 10 million people worldwide. Patients who do not receive an early diagnosis may develop an incurable neurological disorder. PD is a degenerative disorder of the brain, characterized by the impairment of the nigrostriatal system. A wide range of symptoms of motor and non-motor impairment accompanies this disorder. By using new technology, the PD is detected through speech signals of the PD victims by using the reduced instruction set computing 5th version (RISC-V) processor. The RISC-V microcontroller unit (MCU) was designed for the voice-controlled human-machine interface (HMI). With the help of signal processing and feature extraction methods, the digital signal is impaired by the impairment of the nigrostriatal system. These speech signals can be classified through classifier modules. A wide range of classifier modules are used to classify the speech signals as normal or abnormal to identify PD. We use Matrix Laboratory (MATLAB R2021a_v9.10.0.1602886) to analyze the data, develop algorithms, create modules, and develop the RISC-V processor for embedded implementation. Machine learning (ML) techniques are also used to extract features such as pitch, tremor, and Mel-frequency cepstral coefficients (MFCCs). Full article

Blind and visually impaired (BVI) people face significant challenges in perception, navigation, and safety during travel. Existing infrastructure (e.g., blind lanes) and traditional aids (e.g., walking sticks, basic audio feedback) provide limited flexibility and interactivity for complex environments. To solve this problem, we propose a real-time travel assistance system based on deep learning. The hardware comprises an NVIDIA Jetson Nano controller, an Intel D435i depth camera for environmental sensing, and SG90 servo motors for feedback. To address embedded device computational constraints, we developed a lightweight object detection and segmentation algorithm. Key innovations include a multi-scale attention feature extraction backbone, a dual-stream fusion module incorporating the Mamba architecture, and adaptive context-aware detection/segmentation heads. This design ensures high computational efficiency and real-time performance. The system workflow is as follows: (1) the D435i captures real-time environmental data; (2) the processor analyzes this data, converting obstacle distances and path deviations into electrical signals; (3) servo motors deliver vibratory feedback for guidance and alerts. Preliminary tests confirm that the system can effectively detect obstacles and correct path deviations in real time, suggesting its potential to assist BVI users. However, as this is a work in progress, comprehensive field trials with BVI participants are required to fully validate its efficacy. Full article

Modern x86 processors incorporate performance-enhancing features such as prefetching mechanisms, cache coherence protocols, and support for large memory pages (e.g., 2 MB huge pages). While these architectural innovations aim to reduce memory access latency, boost throughput, and maintain cache consistency across cores, they can also expose subtle microarchitectural side channels that adversaries may exploit. This study investigates how the combination of prefetching techniques and huge pages can significantly enhance the throughput and accuracy of covert channels in controlled computing environments. Building on prior work that examined the impact of the MESI cache coherence protocol using single-cache-line access without huge pages, our approach expands the attack surface by simultaneously accessing multiple cache lines across all 512 L1 lines under a 2 MB huge page configuration. As a result, our 9-bit covert channel achieves a peak throughput of 4940 KB/s—substantially exceeding previously reported benchmarks. We further validate our channel on AMD SEV-SNP virtual machines, achieving up to an 88% decoding accuracy using write-access encoding with 2 MB huge pages, demonstrating feasibility even under TEE-enforced virtualization environments. These findings highlight the need for careful consideration and evaluation of the security implications of common performance optimizations with respect to their side-channel potential. Full article

Automatic keyword extraction (AKE) has gained more importance with the increasing amount of digital textual data that modern computing systems process. It has various applications in information retrieval (IR) and natural language processing (NLP), including text summarisation, topic analysis and document indexing. This paper proposes a simple but effective post-processing-based universal approach to improving the performance of any AKE methods, via an enhanced level of semantic-awareness supported by PoS tagging. To demonstrate the performance of the proposed approach, we considered word types retrieved from a PoS tagging step and two representative sources of semantic information—specialised terms defined in one or more context-dependent thesauri, and named entities in Wikipedia. The above three steps can be simply added to the end of any AKE methods as part of a post-processor, which simply re-evaluates all candidate keywords following some context-specific and semantic-aware criteria. For five state-of-the-art (SOTA) AKE methods, our experimental results with 17 selected datasets showed that the proposed approach improved their performances both consistently (up to 100% in terms of improved cases) and significantly (between 10.2% and 53.8%, with an average of 25.8%, in terms of F1-score and across all five methods), especially when all the three enhancement steps are used. Our results have profound implications considering the fact that our proposed approach can be easily applied to any AKE method with the standard output (candidate keywords and scores) and the ease to further extend it. Full article

The geometric process is a significant monotonic stochastic process widely used in the fields of applied probability, particularly in the failure analysis of repairable systems. For repairable systems modeled by a geometric process, accurate estimation of model parameters is essential. The inference problem for geometric processes has been well-studied in the case of single-sample data. However, multi-sample data may arise when the repair processes of multiple systems are observed simultaneously. This study addresses the non-parametric inference problem for geometric processes based on multi-sample data. Several non-parametric estimators are proposed using the linear regression method, and their asymptotic properties are established. In addition, test statistics are introduced to assess sample homogeneity and to evaluate the significance of the trend observed in the process. The performance of the proposed estimators is evaluated through a comprehensive simulation study under small-sample settings. An artificial data analysis is conducted to model the repair processes of multiple repairable systems using the geometric process. Furthermore, a real-world dataset consisting of multi-sample failure data from two shared memory processors of the Blue Mountain supercomputer is analyzed to demonstrate the practical applicability of the method in multi-sample failure data analysis. Full article

In modern multi-core processors, memory request latency critically constrains overall performance. Prefetching, a promising technique, mitigates memory access latency by pre-loading data into faster cache structures. However, existing core-side prefetchers lack visibility to the DRAM state and may issue suboptimal requests, while conventional memory-side prefetchers often default to simple next-line policies that miss complex access patterns. We propose a comprehensive memory-side prefetch optimization scheme, which includes a prefetcher that utilizes advanced prefetching algorithms and an optimization module. Our prefetcher is capable of detecting more complex memory access patterns, thereby improving both prefetch accuracy and coverage. Additionally, considering the characteristics of DRAM memory access, the optimization module minimizes the negative impact of prefetch requests on DRAM by enhancing coordination with memory operations. Additionally, our prefetcher works in synergy with core-side prefetchers to deliver superior overall performance. Simulation results using Gem5 and SPEC CPU2017 workloads show that our approach delivers an average performance improvement of 10.5% and reduces memory access latency by 61%. Our prefetcher also operates in conjunction with core-side prefetchers to form a multi-level prefetching hierarchy, enabling further performance gains through coordinated and complementary prefetching strategies. Full article

This study investigates the tracking control of quadrotor micro aerial vehicles using nonlinear model predictive control (NMPC), with primary emphasis on the implementation of a real-time embedded control system. Apart from the limited memory size, one of the critical challenges is the limited processor speed on resource-constrained microcontroller units (MCUs). This technical issue becomes critical particularly when the maximum allowed computation time for real-time control exceeds 0.01 s, which is the typical sampling time required to ensure reliable control performance. To reduce the computational burden for NMPC, we first derive a nonlinear quadrotor model based on the quaternion number system rather than formulating nonlinear equations using conventional Euler angles. In addition, an implicit continuation generalized minimum residual optimization algorithm is designed for the fast computation of the optimal receding horizon control input. The proposed NMPC is extensively validated through rigorous simulations and experimental trials using Crazyflie 2.1^®, an open-source flying development platform. Owing to the more precise prediction of the highly nonlinear quadrotor model, the proposed NMPC demonstrates that the tracking performance outperforms that of conventional linear MPCs. This study provides a basis and comprehensive guidelines for implementing the NMPC of nonlinear quadrotors on resource-constrained MCUs, with potential extensions to applications such as autonomous flight and obstacle avoidance. Full article

Deterministic random bit generators (DRBG) play a crucial role in device security because they generate secret information cryptographic systems, e.g., secret keys and parameters. Thus, attacks on DRBGs can result in the exposure of important secret values, which can threaten the entire cryptographic system of the target Internet of Things (IoT) equipment and smart devices. In 2020, Meyer proposed a side-channel attack (SCA) method that recovers the output random bits by analyzing the power consumption traces of the NIST standard AES CTR DRBG. In addition, most algorithmic countermeasures against SCAs also utilize random numbers; thus, such vulnerabilities are more critical than other SCAs on cryptographic modules. Meyer’s attack recovers the secret random number in four stages of the attack using only the power traces, which the CTR DRBG processes in 256 blocks. We present an approach that employs a clustering algorithm to enhance Meyer’s attack. The proposed attack increases the attack success rate and recovers more information using a clustering attack in the first step. In addition, it improves the attack accuracy in the third and fourth steps using the information obtained from the clustering process. These results lead to the possibility of attacks at higher noise levels and increase the diversity of target devices for attacking the CTR DRBG. Experiments were conducted on an Atmel XMEGA128D4 processor to evaluate the effectiveness of the proposed attack method. We also introduced artificial noise into the power traces to compare the proposed attack’s performance at different noise levels. Our results demonstrate that the first step of the proposed attack achieves a higher success rate than Meyer’s attack at all noise levels. For example, at high noise levels, the difference in the success rates is up to 50%. In steps 3 and 4, an average performance improvement of 18.5% greater than Meyer’s proposed method is obtained. The proposed attack effectively extends the target to more noisy environments than previous attacks, thereby increasing the threat of SCA on CTR DRBGs. Full article

The increasing threat of quantum computing to traditional cryptographic systems has prompted intense research into post-quantum schemes. Despite SNOVA’s potential for lightweight and secure digital signatures, its performance on embedded devices (e.g., ARMv8 platforms) remains underexplored. This research addresses this gap by presenting the optimal SNOVA implementations on embedded devices. This paper presents a performance-optimized implementation of the SNOVA post-quantum digital signature scheme on ARMv8 processors. SNOVA is a multivariate cryptographic algorithm under consideration in the NIST’s additional signature standardization. Our work targets the performance bottlenecks in the SNOVA scheme. Specifically, we employ matrix arithmetic over ${\mathbb{GF}}_{16}$ and AES-CTR-based pseudorandom number generation by exploiting the NEON SIMD extension and tailoring the computations to the matrix rank. At a low level, we develop rank-specific SIMD kernels for addition and multiplication. Rank 4 matrices (i.e., 16 bytes) are handled using fully vectorized instructions that align with 128-bit-wise registers, while rank 2 matrices (i.e., 4 bytes) are processed in batches of four to ensure full SIMD occupancy. At the high level, core routines such as key generation and signature evaluation are structurally refactored to provide aligned memory layouts for batched execution. This joint optimization across algorithmic layers reduces the overhead and enables seamless hardware acceleration. The resulting implementation supports 12 SNOVA parameter sets and demonstrates substantial efficiency improvements compared to the reference baseline. These results highlight that fine-grained SIMD adaptation is essential for the efficient deployment of multivariate cryptography on modern embedded platforms. Full article