Search Results (206)

In order to achieve better accuracy, modern models have become increasingly large, leading to an exponential increase in computational load, making it challenging to apply them to edge computing. Binary neural networks (BNNs) are models that quantize the filter weights and activations to 1-bit. These models are highly suitable for small chips like advanced RISC machines (ARMs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chips (SoCs) and other edge computing devices. To design a model that is more friendly to edge computing devices, it is crucial to reduce the floating-point operations (FLOPs). Batch normalization (BN) is an essential tool for binary neural networks; however, when convolution layers are quantized to 1-bit, the floating-point computation cost of BN layers becomes significantly high. This paper aims to reduce the floating-point operations by removing the BN layers from the model and introducing the scaled weight standardization convolution (WS-Conv) method to avoid the significant accuracy drop caused by the absence of BN layers, and to enhance the model performance through a series of optimizations, adaptive gradient clipping (AGC) and knowledge distillation (KD). Specifically, our model maintains a competitive computational cost and accuracy, even without BN layers. Furthermore, by incorporating a series of training methods, the model’s accuracy on CIFAR-100 is 0.6% higher than the baseline model, fractional activation BNN (FracBNN), while the total computational load is only 46% of the baseline model. With unchanged binary operations (BOPs), the FLOPs are reduced to nearly zero, making it more suitable for embedded platforms like FPGAs or other edge computers. Full article

We investigated the radio frequency (RF) performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon carbide substrates, featuring two distinct T-shaped gate structures. A comparative analysis between a silicon nitride (SiN_x)-passivated T-gate and a floating T-gate design reveals significant differences in parasitic capacitance and high-frequency behavior. The floating gate structure effectively reduces fringe capacitance, resulting in improved cut-off frequency (f_T) and maximum oscillation frequency (f_max), achieving f_T = 82.7 GHz and f_max = 80.2 GHz, respectively. These enhancements underscore the critical importance of optimizing gate structures to advance GaN-based HEMTs for high-speed and high-power applications. The findings provide valuable insights for the design of future RF and millimeter-wave (mm-wave) devices. Full article

Charge-trapping memory (CTM) is a viable contender to supersede the floating gate technology in high-density flash memory applications. To this end, very reliable charge storage in CTM should be secured. This requires optimization of trap density, their energy and spatial location as well as a deep understanding of their origin. In this work, we used X-ray photoelectron spectroscopy (XPS) to investigate chemical bonds in nanolaminated and doped HfO₂/Al₂O₃ stacks in an effort to gain insight into the nature of defects in the electron/hole trapping processes. The impact of Al incorporation into the HfO₂ and rapid thermal annealing (RTA) in O₂ on the composition, stoichiometry and bonding configurations was studied. Incorporation of Al into HfO₂ leads to an increased concentration of Hf-suboxides. Subsequent RTA effectively reduces suboxides, enhances the stoichiometry of the HfO₂/Al₂O₃ stacks and facilitates intermixing at the dielectric interface, resulting in the formation of Hf–Al–O bonds. The valence band spectra indicate that both Al incorporation and RTA change the dielectric/Si band alignment in a similar way, lowering the valence band offset. The observed changes were considered in relation to the electrically active defects and traps in the structures. Full article

This work investigates the impact of load-dump stress on p-GaN HEMTs under floating gate condition. The experiments show that preconditioning the device with a small load-dump stress (150 V, @t_d = 100 ms and t_r = 8 ms) enhances its robustness against a larger stress (190 V, @t_d = 100 ms and t_r = 8 ms). If a large load-dump stress (≥160 V, @t_d = 100 ms and t_r = 8 ms) is applied directly to the device’s drain, the device will burn out. This occurs because the rapidly changing drain voltage during a load-dump event can generate a capacitive coupling current, leading to transient positive charge accumulation in the gate region. Consequently, the channel under the gate is turned on, allowing a large current to flow through it. The coexistence of high current and high voltage leads to substantial Joule heating within the device, resulting in eventual burnout. When a small load-dump stress is initially applied, the resulting charging of electron traps in the gate region increases the threshold voltage. As a result, the device can withstand a larger load-dump stress before the channel turns on, which explains the device’s enhanced robustness. This work clarifies the failure threshold of p-GaN HEMTs under the load-dump stress, providing key support for improving the devices’ reliability in the practical applications. It can provide a basis for adding necessary protective measures in device circuit design, and clarify the triggering voltage threshold of protective measures to ensure that they can effectively avoid device damage due to the load-dump stress. Full article

Crack segmentation in cluttered scenes with slender and irregular patterns remains difficult, and practical systems must balance accuracy and efficiency. We present CONTI-CrackNet, which is a lightweight visual state-space network that integrates a Multi-Directional Selective Scanning Strategy (MD3S). MD3S performs bidirectional scanning along the horizontal, vertical, and diagonal directions, and it fuses the complementary paths with a Bidirectional Gated Fusion (BiGF) module to strengthen global continuity. To preserve fine details while completing global texture, we propose a Dual-Branch Pixel-Level Global–Local Fusion (DBPGL) module that incorporates a Pixel-Adaptive Pooling (PAP) mechanism to dynamically weight max-pooled responses and average-pooled responses. Evaluated on two public benchmarks, the proposed method achieves an F1 score (F1) of 0.8332 and a mean Intersection over Union (mIoU) of 0.8436 on the TUT dataset, and it achieves an mIoU of 0.7760 on the CRACK500 dataset, surpassing competitive Convolutional Neural Network (CNN), Transformer, and Mamba baselines. With 512 × 512 input, the model requires 24.22 G floating point operations (GFLOPs), 6.01 M parameters (Params), and operates at 42 frames per second (FPS) on an RTX 3090 GPU, delivering a favorable accuracy–efficiency balance. These results show that CONTI-CrackNet improves continuity and edge recovery for thin cracks while keeping computational cost low, and it is lightweight in terms of parameter count and computational cost. Full article

You Only Look Once (YOLO) is a convolutional neural network-based object detection algorithm widely used in real-time vision applications. However, its high computational demand leads to significant power consumption and cost when deployed in graphics processing units. Field-programmable gate arrays offer a low-power alternative. However, their efficient implementation requires architecture-level optimization tailored to limited device resources. This study presents an optimized YOLOv2 accelerator for the Zynq-7000 system-on-chip (SoC). The design employs 16-bit integer quantization, a filter reuse structure, an input feature map reuse scheme using a line buffer, and tiling parameter optimization for the convolution and max pooling layers to maximize resource efficiency. In addition, a stall-based control mechanism is introduced to prevent structural hazards in the pipeline. The proposed accelerator was implemented on the Zynq-7000 SoC board, and a system-level evaluation confirmed a negligible accuracy drop of only 0.2% compared with the 32-bit floating-point baseline. Compared with previous YOLO accelerators on the same SoC, the design achieved up to 26% and 15% reductions in flip-flop and digital signal processor usage, respectively. This result demonstrates feasible deployment on XC7Z020 with DSP 57.27% and FF 16.55% utilization. Full article

Crack segmentation plays a vital role in ensuring structural safety, yet practical deployment on resource-limited platforms demands models that balance accuracy with efficiency. While high-accuracy models often rely on computationally heavy designs to expand their receptive fields, recent lightweight approaches typically delay this expansion to the deepest, low-resolution layers to maintain efficiency. This design choice leaves long-range context underutilized, where fine-grained evidence is most intact. In this paper, we propose an evidence-preserving receptive-field expansion network, which integrates a multi-scale dilated block to efficiently capture long-range context from the earliest stages and an input-guided gate that leverages grayscale conversion, average pooling, and gradient extraction to highlight crack evidence directly from raw inputs. Experiments on six benchmark datasets demonstrate that the proposed network achieves consistently higher accuracy under lightweight constraints. Each of the three proposed variants—Base, Small, and Tiny—outperforms its corresponding baselines with larger parameter counts, surpassing a total of 13 models. For example, the Base variant reduces parameters by 66% compared to the second-best CrackFormer II and floating-point operations by 53% on the Ceramic dataset, while still delivering superior accuracy. Pareto analyses further confirm that the proposed model establishes a superior accuracy–efficiency trade-off across parameters and floating-point operations. Full article

NO₂ is a toxic gas mainly generated by combustion processes, such as vehicle emissions and industrial activities. It is a key contributor to smog, acid rain, ground-level ozone, and particulate matter, all of which pose serious risks to human health and the environment. Conventional resistive gas sensors, typically based on metal oxide semiconductors, detect NO₂ by resistance modulation through surface interactions with the gas. However, they often suffer from low responsiveness and poor selectivity. This study investigates NO₂ detection using nanoporous zinc oxide thin films integrated into a resistor structure and floating-gate field-effect transistor (FGFET). Both Silvaco-Atlas simulations and experimental fabrication were employed to evaluate sensor behavior under NO₂ exposure. The results show that FGFET provides higher sensitivity, faster response times, and improved selectivity compared to resistor-based devices. In particular, FGFET achieves a detection limit as low as 89 ppb, with optimal performance around 400 °C, and maintains stability under varying humidity levels. The enhanced performance arises from quantum well effects at the floating-gate Schottky contact, combined with NO₂ adsorption on the ZnO surface. These interactions extend the depletion region and confine charge carriers, amplifying conductivity modulation in the channel. Overall, the findings demonstrate that FGFET is a promising platform for NO₂ sensors, with strong potential for environmental monitoring and industrial safety applications. Full article

To address the inherent limitations of single-modality sensors constrained by physical properties and data modalities, we propose DTC-YOLO (Depth-Texture Coupling Mechanism YOLO), a depth-texture coupled multimodal detection framework. The main contributions are as follows: RGB-LiDAR (RGB-Light Detection and Ranging) Fusion: We propose a depth-color mapping and weighted fusion strategy to effectively integrate depth and texture features. ADF³-Net (Adaptive Dimension-aware Focused Fusion Network): A feature fusion network with hierarchical perception, channel decoupling, and spatial adaptation. A dynamic gated fusion mechanism enables adaptive weighting across multidimensional features, thereby enhancing depth-texture representation. Adown Module: A dual-path adaptive downsampling module that separates high-frequency details from low-frequency semantics, reducing GFLOPs (Giga Floating-point Operations Per Second) by 10.53% while maintaining detection performance. DTC-YOLO achieves substantial improvements over the baseline: +3.50% mAP50, +3.40% mAP50-95, and +3.46% precision. Moreover, it maintains moderate improvements for medium-scale objects while significantly enhancing detection of extremely large and small objects, effectively mitigating the scale-related accuracy discrepancies of vision-only models in complex traffic environments. Full article

Lifting hooks equipped with safety latches are critical terminal components of lifting machinery. The safety condition of this component is a crucial factor in preventing load dislodgement during lifting operations. To achieve intelligent monitoring of the hook and the safety latch, precise identification of these components is a crucial initial step. In this study, we propose an improved YOLOv8s detection model called YOLO-HOOK. To reduce computational complexity while simultaneously maintaining precision, the model incorporates an Efficient_Light_C2f module, which integrates a Convolutional Gated Linear Unit (CGLU) with Star Blocks. The neck network utilizes Multi-Scale Efficient Cross-Stage Partial (MSEICSP) to improve edge feature extraction capabilities under complex lighting conditions and multi-scale variations. Furthermore, a HOOK_IoU loss function was designed to optimize bounding box regression through auxiliary bounding boxes, and a piecewise linear mapping strategy was used to improve localization precision for challenging targets. The results of ablation studies and comparative analyses indicate that the YOLO-HOOK secured mAP scores of 90.4% at an Intersection over Union (IoU) threshold of 0.5 and 71.6% across the 0.5–0.95 IoU span, thereby eclipsing the YOLOv8s reference model by margins of 4.6% and 5.4%, respectively. Furthermore, it manifested a paramount precision of 97.0% alongside a commendable recall rate of 83.4%. The model parameters were reduced to 9.6 M, the computational complexity was controlled at 31.0 Giga Floating-point Operations Per Second (GFLOPs), and the inference speed reached 310 frames per second (FPS), balancing a lightweight design with excellent performance. These findings offer a technical approach for the intelligent recognition of hooks and safety latches during lifting operations, thus aiding in refining the safety management of lifting operations. Full article

Surface defect detection in aluminum profiles is critical for maintaining product quality and ensuring efficient industrial production. However, existing detection algorithms often struggle to address the challenges of imbalanced defect categories, low detection accuracy for small-scale defects, and irregular flaw geometries. These limitations compromise both detection accuracy and algorithmic robustness. Accordingly, we proposed MCH-YOLOv12—an improved YOLOv12-based algorithm for precise defect detection. Firstly, we enhanced the original Ghost convolution by incorporating multi-scale feature extraction and named the improved version MultiScaleGhost, which replaced the standard convolutions in the Backbone of YOLOv12. This improvement mitigated the limitations of single-scale convolution, enhancing feature representation and the detection of irregularly shaped defects. Secondly, we addressed the directional and edge-specific nature of defects by enhancing the traditional Channel-wise Gated Linear Unit (CGLU). We proposed the Spatial-Channel Collaborative Gated Linear Unit (SCCGLU), which was embedded after the C3k2 module in the Neck of YOLOv12 to better capture fine-grained features. Finally, we designed a Hybrid Head combining anchor-based and anchor-free detection to improve adaptability to defects of various sizes and shapes. Experimental results on an aluminum profile defect dataset demonstrated improved accuracy, reduced category imbalance, and lower parameters and Floating Point Operations (FLOPs), making the algorithm suitable for real-time industrial inspection. Full article

Air pollution threatens human health and ecosystems, making timely forecasting essential. The spatiotemporal dynamics of pollutants, shaped by various factors, challenge traditional methods. Therefore, spatiotemporal graph-based deep learning has gained attention for its ability to capture spatial and temporal dependencies within monitoring networks. However, many existing models, despite their high predictive accuracy, face computational complexity and scalability challenges. This study introduces clustered and lightweight spatio-temporal graph convolutional network with gated recurrent unit (ClusLite-STGCN-GRU), a hybrid model that integrates spatial clustering based on pollutant time series for graph construction, Copula-based dependency analysis for selecting relevant pollutants to predict PM_2.5, and graph convolution combined with gated recurrent units to extract spatiotemporal features. Unlike conventional approaches that require learning or dynamically updating adjacency matrices, ClusLite-STGCN-GRU employs a fixed, simple cluster-based structure. Experimental results on Tehran air quality data demonstrate that the proposed model not only achieves competitive predictive performance compared to more complex models, but also significantly reduces computational cost—by up to 66% in training time, 83% in memory usage, and 84% in number of floating-point operations—making it suitable for real-time applications and offering a practical balance between accuracy, interpretability, and efficiency. Full article

A chili pepper variety and origin detection system that integrates a field-programmable gate array (FPGA) with an electronic nose (e-nose) is proposed in this paper to address the issues of variety confusion and origin ambiguity in the chili pepper market. The system uses the AIRSENSE PEN3 e-nose from Germany to collect gas data from thirteen different varieties of chili peppers and two specific varieties of chili peppers originating from seven different regions. Model training is conducted via the proposed lightweight convolutional neural network ChiliPCNN. By combining the strengths of a convolutional neural network (CNN) and a multilayer perceptron (MLP), the ChiliPCNN model achieves an efficient and accurate classification process, requiring only 268 parameters for chili pepper variety identification and 244 parameters for origin tracing, with 364 floating-point operations (FLOPs) and 340 FLOPs, respectively. The experimental results demonstrate that, compared with other advanced deep learning methods, the ChiliPCNN has superior classification performance and good stability. Specifically, ChiliPCNN achieves accuracy rates of 94.62% in chili pepper variety identification and 93.41% in origin tracing tasks involving Jiaoyang No. 6, with accuracy rates reaching as high as 99.07% for Xianjiao No. 301. These results fully validate the effectiveness of the model. To further increase the detection speed of the ChiliPCNN, its acceleration circuit is designed on the Xilinx Zynq7020 FPGA from the United States and optimized via fixed-point arithmetic and loop unrolling strategies. The optimized circuit reduces the latency to 5600 ns and consumes only 1.755 W of power, significantly improving the resource utilization rate and processing speed of the model. This system not only achieves rapid and accurate chili pepper variety and origin detection but also provides an efficient and reliable intelligent agricultural management solution, which is highly important for promoting the development of agricultural automation and intelligence. Full article

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations. Full article

Predictive maintenance (PdM) is a proactive strategy that enhances safety, minimizes unplanned downtime, and optimizes operational costs by forecasting equipment failures before they occur. This study presents a novel Field Programmable Gate Array (FPGA)-accelerated predictive maintenance framework for UAV engines using a Singular Value Decomposition (SVD)-optimized Long Short-Term Memory (LSTM) model. The model performs binary classification to predict the likelihood of imminent engine failure by processing normalized multi-sensor data, including temperature, pressure, and vibration measurements. To enable real-time deployment on resource-constrained UAV platforms, the LSTM’s weight matrices are compressed using Singular Value Decomposition (SVD), significantly reducing computational complexity while preserving predictive accuracy. The compressed model is executed on a Xilinx ZCU-104 FPGA and uses a pipelined, AXI-based hardware accelerator with efficient memory mapping and parallelized gate calculations tailored for low-power onboard systems. Unlike prior works, this study uniquely integrates a tailored SVD compression strategy with a custom hardware accelerator co-designed for real-time, flight-safe inference in UAV systems. Experimental results demonstrate a 98% classification accuracy, a 24% reduction in latency, and substantial FPGA resource savings—specifically, a 26% decrease in BRAM usage and a 37% reduction in DSP consumption—compared to the 32-bit floating-point SVD-compressed FPGA implementation, not CPU or GPU. These findings confirm the proposed system as an efficient and scalable solution for real-time UAV engine health monitoring, thereby enhancing in-flight safety through timely fault prediction and enabling autonomous engine monitoring without reliance on ground communication. Full article