Search Results (58)

As robotic platforms have become more capable, the need for improved power efficiency has grown due to increased applications and computational loads. Several methods and controllers are available in various types of robotics that can achieve increased power efficiency. This paper reviews intelligent power management methods and energy-efficient controls in untethered battery-powered robotics including dynamic power management (DPM), dynamic voltage and frequency scaling (DVFS), AI-assisted adaptive dynamic programming (DP) control systems, AI-assisted model predictive control (MPC) systems, and hybrid energy storage system (HESS) hardware well suited for multi-objective AI integration. Robotic neural networks and AI-enhancement are identified as promising directions for advanced research. However, the need to improve training power efficiency calls for further research if these AI-enhancement systems are to be integrated onboard robotic platforms. This paper provides the background and case study implementation of robotic power efficiency methods across various scales of development to illustrate the current capabilities of robotic platforms. Efficiency improvements are quantified and opportunities for advancements are presented, as well as key findings reached through this in-depth review. Full article

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current ($IC{C}_{max}$) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths $ICC$ trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining $IC{C}_{max}$ and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning. Full article

This paper conducts a multi-objective comparative study on various ventilation–radiant coupled heating systems that combine mixing ventilation (MV) and displacement ventilation (DV) with ceiling, side wall, and floor radiant heating. The aim is to explore the differences in indoor environmental quality (IEQ) and human thermal comfort under different system configurations, as well as the impact of the radiant temperature in the radiant modules and the supply air temperature in the ventilation module on system performance. The research results show that the combination of displacement ventilation and floor radiant heating (DV-F) performs the best in terms of thermal comfort and energy efficiency. In this configuration, the Predicted Mean Vote (PMV) for the indoor environment and human thermal comfort is close to neutral (−0.15 to 0.35), the Draught Rate (DR) is significantly lower than in other systems (3.7% to 4.4%), and the ventilation efficiency is relatively high. In addition, a comprehensive evaluation of different system configurations using the CRITIC weight method further verified that the DV-F configuration with a radiant temperature of 26.2 °C to 28.2 °C and a supply air temperature of 26 °C to 28 °C is superior. This study provides theoretical guidance for the design and optimization of heating systems. Full article

Swarm robots often need to cover the designated area to complete specific tasks. While robots possess local perception and limited communication capabilities, they struggle to handle coverage issues in dynamic environments. This paper proposes a self-organizing algorithm for swarm robots based on Dynamic Virtual Force (DVF) to cover dynamic areas. Robots in the swarm can locally perceive their surrounding robots and dynamically select adjacent ones to generate virtual repulsion, thereby controlling their movement. The algorithm enables swarm robots to be rapidly and evenly deployed in unknown areas, adapt to dynamic area changes, and solve the problem of symmetrical robot distribution during coverage. It also allows for adaptive coverage of different density areas, divided as needed. Experimental validation across 20 benchmark scenarios (including obstacles, dynamic boundaries, and multi-density zones) demonstrates that the DVF method outperforms existing approaches in coverage rate, total robot movement distance, and coverage uniformity. The results validate its effectiveness and superiority in addressing area coverage problems. By addressing these challenges, the DVF algorithm can be widely applied to forest firefighting, oil spill cleanup in the ocean, and other swarm robot tasks. Full article

With the demand for workflow processing driven by edge computing in the Internet of Things (IoT) and cloud computing growing at an exponential rate, task scheduling in heterogeneous distributed systems has become a key challenge to meet real-time constraints in resource-constrained environments. Existing studies now attempt to achieve the best balance in terms of time constraints, energy efficiency, and system reliability in Dynamic Voltage and Frequency Scaling environments. This study proposes a two-stage collaborative optimization strategy. With the help of an innovative algorithm design and theoretical analysis, the multi-objective optimization challenges mentioned above are systematically solved. First, based on a reliability-constrained model, we propose a topology-aware dynamic priority scheduling algorithm (EAWRS). This algorithm constructs a node priority function by incorporating in-degree/out-degree weighting factors and critical path analysis to enable multi-objective optimization. Second, to address the time-varying reliability characteristics introduced by DVFS, we propose a Fibonacci search-based dynamic frequency scaling algorithm (SEFFA). This algorithm effectively reduces energy consumption while ensuring task reliability, achieving sub-optimal processor energy adjustment. The collaborative mechanism of EAWRS and SEFFA has well solved the dynamic scheduling challenge based on DAG in heterogeneous multi-core processor systems in the Internet of Things environment. Experimental evaluations conducted at various scales show that, compared with the three most advanced scheduling algorithms, the proposed strategy reduces energy consumption by an average of 14.56% (up to 58.44% under high-reliability constraints) and shortens the makespan by 2.58–56.44% while strictly meeting reliability requirements. Full article

The emergence of Flexible Manufacturing Systems (FMS) presents new challenges in Industrial IoT (IIoT) environments. Unlike traditional real-time systems, FMS must accommodate task set variability driven by human–machine interaction. As such variations can lead to abrupt resource overload or idleness, a dynamic scheduling mechanism is required. Although prior studies have explored dynamic scheduling, they often relax deadlines for lower-criticality tasks, which is not well suited to IIoT systems with strict deadline constraints. In this paper, instead of treating dynamic scheduling as a prediction problem, we model it as deterministic planning in response to explicit, observable user input. To this end, we precompute feasible resource plans for anticipated task set variations through offline optimization and switch to the appropriate plan at runtime. During this process, our approach jointly optimizes processor speeds, memory allocations, and edge/cloud offloading decisions, which are mutually interdependent. Simulation results show that the proposed framework achieves up to 73.1% energy savings compared to a baseline system, 100% deadline compliance for real-time production tasks, and low-latency responsiveness for user-interaction tasks. We anticipate that the proposed framework will contribute to the design of efficient, adaptive, and sustainable manufacturing systems. Full article

The TDM Test Scheduler and TAM Optimization Toolkit is a novel, integrated, and user-friendly solution designed for engineers, researchers, and instructors working in the field of manufacturing tests. It effectively supports test planning for multicore, DVFS-based SoCs with multiple voltage islands, offering optimized solutions that minimize test costs while ensuring compliance with power and thermal constraints. The toolkit provides (a) a high-level language (HLL) for the intuitive representation of test processes, along with a smart syntax and logic checker for verification; (b) an advanced compilation and execution environment featuring two computationally efficient Time-Division Multiplexing (TDM)-specialized solvers; (c) a sophisticated Test Access Mechanism (TAM) optimization framework; (d) a customized visualization environment capable of depicting and animating power- and thermal-annotated test schedules; (e) a versatile testbed for educational and research activities. Full article

Seafloor hydrothermal vent areas are potential sources of polymetallic sulfide deposits and exhibit distinct mineralization structures under different tectonic settings. The Daxi Vent Field (DVF), located on the Carlsberg Ridge in the northwestern Indian Ocean, represents a basalt-hosted hydrothermal system. To investigate the alteration zone structure of the DVF, high-resolution near-bottom bathymetric and magnetic data were collected during the Chinese DY57 expedition in 2019. Based on the results of magnetic anomaly data processing, including reduction to a level surface and Euler deconvolution, the location and depth of the magnetic sources were identified. In addition, two 2.5D magnetic forward models crossing the active and inactive vent fields were constructed. The results indicate that the range of the alteration zone in the active vent at the DVF extends up to 120 m in width and 80 m in depth, while the hydrothermal deposit at the extinct vent on the northeastern side extends up to 220 m along the ridge axis with a thickness of 30 m. Full article

Accurate image registration is essential for various remote sensing applications, particularly in multi-temporal image analysis. This paper introduces DVF-NET, a novel deep learning-based framework for dual-temporal remote sensing image registration. DVF-NET integrates two displacement vector fields to address nonlinear distortions caused by significant variations between images, enabling more precise image alignment. A key innovation of this method is the incorporation of a Structural Attention Module (SAT), which enhances the model’s ability to focus on structural features, improving the feature extraction process. Additionally, we propose a novel loss function design that combines multiple similarity metrics, ensuring more comprehensive supervision during training. Experimental results on various remote sensing datasets indicate that the proposed DVF-NET outperforms the existing methods in both accuracy and robustness, particularly when handling images with substantial geometric distortions such as tilted buildings. The results validate the effectiveness of our approach and highlight its potential for various remote sensing tasks, including change detection, land cover classification, and environmental monitoring. DVF-NET provides a promising direction for the advancement of remote sensing image registration techniques, offering both high precision and robustness in complex real-world scenarios. Full article

One of the most important challenges in modern digital systems, especially regarding autonomous embedded systems, is energy efficiency. This work studies an energy consumption optimization approach on a microcontroller that implements IoT-like applications, featuring Dynamic Voltage and Frequency Scaling (DVFS) capabilities, by dynamically changing the supply voltage and clock frequency. The proposed approach categorizes tasks according to their demands on timing requirements and analyzes speed–energy efficiency trade-offs. Results strongly indicate that energy performance is improved due to the proper adjustment of configurations towards required tasks. The findings are verified within a set of scenarios that highlight the potential balance between energy economy and operational demands for specialized IoT contexts. Full article

In a kind of system, where strong time constraints exist, very often, worst-case design is applied. It could drive to the suboptimal usage of resources. In previous work, the mechanism of self-adaptive software that is able to reduce this was presented. This paper introduces a novel extension of the method for self-adaptive software synthesis applicable for real-time multicore embedded systems with dynamic voltage and frequency scaling (DVFS). It is based on a multi-criteria approach to task scheduling, optimizing both energy consumption and proof against time delays. The method can be applied to a wide range of embedded systems, such as multimedia systems or Industrial Internet of Things (IIoT). The main aim of this research is to find the method of automatic construction of the task scheduler that is able to minimize energy consumption during the varying execution times of each task. Full article

Digital low-dropout (LDO) regulators are popular in research today as compact power supply solutions. This paper provides a unique approach to analyze digital LDO feedback mechanics and stability, to reduce voltage ripple and extend operating speed over the state-of-the-art. A novel error-subtracting counter is proposed to exponentially improve the response time of any digital LDO, to keep the loop stable outside the typical operating limits, and to increase power-supply rejection (PSR). This leverages the fact that digital LDOs are fundamentally one-bit relaxation oscillators in steady-state. Theory and simulations show how the analog-to-digital (ADC) and digital-to-analog converters (DAC) in these systems affect stability. When compromised, a digital LDO produces uncontrolled sub-clock oscillations at the output that the proposed error-subtracting counter removes. Full article

Power management (PM) is cumbersome for today’s computing systems. Attainable performance is bounded by the architecture’s computing efficiency and capped in temperature, current, and power. PM is composed of multiple interacting layers. High-level controllers (HLCs) involve application-level policies, operating system agents (OSPMs), and PM governors and interfaces. The application of high-level control decisions is currently delegated to an on-chip power management unit executing tailored PM firmware routines. The complexity of this structure arises from the scale of the interaction, which pervades the whole system architecture. This paper aims to characterize the cost of the communication backbone between high-level OSPM agents and the on-chip power management unit (PMU) in high performance computing (HPC) processors. For this purpose, we target the System Control and Management Interface (SCMI), which is an open standard proposed by Arm. We enhance a fully open-source, end-to-end FPGA-based HW/SW framework to simulate the interaction between a HLC, a HPC system, and a PMU. This includes the application-level PM policies, the drivers of the operating system-directed configuration and power management (OSPM) governor, and the hardware and firmware of the PMU, allowing us to evaluate the impact of the communication backbone on the overall control scheme. With this framework, we first conduct an in-depth latency study of the communication interface across the whole PM hardware (HW) and software (SW) stack. Finally, we studied the impact of latency in terms of the quality of the end-to-end control, showing that the SCMI protocol can sustain reactive power management policies. Full article

Benchmarks play an essential role in the performance evaluation of novel research concepts. Their effectiveness diminishes if they fail to exploit the available hardware of the evaluated microprocessor or, more broadly, if they are not consistent in comparing various systems. An empirical analysis of the consecrated Splash-2 benchmarks suite vs. the latest version Splash-4 was performed. It was shown that on a 64-core configuration, half of the simulated benchmarks reach temperatures well beyond the critical threshold of 105 °C, emphasizing the necessity of a multi-objective evaluation from at least the following perspectives: energy consumption, performance, chip temperature, and integration area. During the analysis, it was observed that the cores spend a large amount of time in the idle state, around 45% on average in some configurations. This can be exploited by implementing a predictive dynamic voltage and frequency scaling (DVFS) technique called the Simple Core State Predictor (SCSP) to enhance the Intel Nehalem architecture and to simulate it using Sniper. The aim was to decrease the overall energy consumption by reducing power consumption at core level while maintaining the same performance. More than that, the SCSP technique, which operates with core-level abstract information, was applied in parallel with a Value Predictor (VP) or a Dynamic Instruction Reuse (DIR) technique, which rely on instruction-level information. Using the SCSP alone, a 9.95% reduction in power consumption and an energy reduction of 10.54% were achieved, maintaining the performance. By combining the SCSP with the VP technique, a performance increase of 8.87% was obtained while reducing power and energy consumption by 3.13% and 8.48%, respectively. Full article

Dynamic voltage and frequency scaling (DVFS) is a technique used to optimize energy consumption in ultra-low-power embedded systems. To ensure sufficient computational capacity, the system must scale up its performance settings. The objective is to conserve energy in times of reduced computational demand and/or when battery power is used. Fast Fourier Transform (FFT), Cyclic Redundancy Check 32 (CRC32), Secure Hash Algorithm 256 (SHA256), and Message-Digest Algorithm 5 (MD5) are focused functions that demand computational power to achieve energy-efficient performance. Selected operations are analyzed from the energy consumption perspective. In this manner, the energy required to perform a specific function is observed, thereby mitigating the influence of the instruction set or system architecture. For stable operating voltage scaling, an exponential model for voltage calculation is presented. Statistical significance tests are conducted to validate and support the findings. Results show that the proposed optimization technique reduces energy consumption for ultra-low-power applications from 27.74% to up to 47.74%. Full article