Search Results (20)

For next-generation biomedical and biochemical sensor nodes, the analog front-end demands a direct interface with current-output sensors, extreme miniaturization, and nanowatt power consumption to enable energy autonomy. This work directly addresses these needs by presenting a comparative analysis of four minimalist, first-order, current-mode $\Delta \Sigma$ modulator ($\Delta \Sigma$M) architectures. Optimized for ultra-low-voltage operation (supply $\le 0.5$ V), the investigated topologies—including resistive, switched-capacitor, and current-reference-based cores—exploit passive integration and charge-domain feedback, eliminating the need for power-hungry active blocks. Detailed circuit-level simulations confirm that, with ad hoc techniques, it is possible to achieve stable first-order noise shaping in the deep near-threshold region, delivering up to 10-bit resolution while consuming less than 10 nW at a 0.5 V supply voltage achieving a signal bandwidth in the sub-10 hertz range. This study validates that robust $\Delta \Sigma$ conversion is feasible under extreme area and power constraints by leveraging architectural simplicity. The clear performance–complexity trade-offs outlined make these current-mode architectures ideal candidates for monolithic integration within miniaturized, energy-autonomous sensing systems. Full article

This paper presents an all-digital fractional-N phase-locked loop (ADPLL) operating in the 2.86–3.2 GHz range, optimized for IoT and high-frequency RF transceiver applications demanding stringent phase noise performance, fast settling time, and high integration capability. The key innovation lies in the introduction of a bandpass delta-sigma time-to-digital converter (BPDSTDC) that achieves high-resolution phase detection, an extended detection range of ±2$\pi$, and superior noise-shaping characteristics, completely eliminating the complex calibration procedures typically required in conventional TDC designs. The proposed architecture synergistically combines the BPDSTDC with digital down-conversion blocks to extract phase error at baseband, a divider chain integrated with phase interpolators achieving 1/4 fractional resolution to suppress in-band quantization noise, and a wide-bandwidth digital loop filter (>1 MHz) ensuring fast dynamic response and robust stability. The bandpass delta-sigma modulator is implemented with compact resonator structures and a flash quantizer, achieving an optimal balance among resolution, power consumption, and silicon area. The incorporation of highly linear phase interpolators extends fractional frequency synthesis capability without requiring complex digital-to-time converters (DTCs), significantly reducing design complexity and calibration overhead. Fabricated in a 180-nm CMOS technology, the proposed chip demonstrates robust measured performance. The band-pass delta-sigma TDC achieves a low integrated rms timing noise of 183 fs within a 1-MHz bandwidth. Leveraging this low TDC noise, the complete ADPLL exhibits a measured in-band phase noise of −120 dBc/Hz at a 1-MHz offset for a 3.2-GHz output frequency while operating with a loop bandwidth exceeding 1 MHz. This corresponds to a normalized phase noise of −216 dBc/Hz. The system operates from a 1.8-V supply and consumes 10 mW, achieving competitive performance compared with prior noise-shaping TDC-based all-digital PLLs. Full article

Reliable and low-latency seizure detection from electroencephalography (EEG) is critical for continuous clinical monitoring and emerging wearable health technologies. Spiking neural networks (SNNs) provide an event-driven computational paradigm that is well suited to real-time signal processing, yet achieving competitive seizure detection performance with constrained model complexity remains challenging. This work introduces a hybrid spike encoding scheme that combines Delta–Sigma (change-based) and stochastic rate representations, together with two spiking architectures designed for real-time EEG analysis: a compact feed-forward HybridSNN and a convolution-enhanced ConvSNN incorporating depthwise-separable convolutions and temporal self-attention. The architectures are intentionally designed to operate on short EEG segments and to balance detection performance with computational practicality for continuous inference. Experiments on the CHB–MIT dataset show that the HybridSNN attains 91.8% accuracy with an F1-score of 0.834 for seizure detection, while the ConvSNN further improves detection performance to 94.7% accuracy and an F1-score of 0.893. Event-level evaluation on continuous EEG recordings yields false-alarm rates of 0.82 and 0.62 per day for the HybridSNN and ConvSNN, respectively. Both models exhibit inference latencies of approximately 1.2 ms per 0.5 s window on standard CPU hardware, supporting continuous real-time operation. These results demonstrate that hybrid spike encoding enables spiking architectures with controlled complexity to achieve seizure detection performance comparable to larger deep learning models reported in the literature, while maintaining low latency and suitability for real-time clinical and wearable EEG monitoring. Full article

This paper presents a low-power continuous-time delta-sigma (CT-DS) analog-to-digital converter (ADC) for use in high-sensitivity automotive-grade sub-1 GHz receivers in emerging wireless sensors network applications. The proposed ADC employs a third-order Cascade of Integrators FeedForward and Feedback (CIFF-B) loop filter operating at a sampling frequency of 150 MHz to achieve high energy efficiency and robust noise shaping. A low-noise phase-locked loop (PLL) is integrated to provide high-precision clock signals. The loop filter combines active-RC and GmC integrators with the source degeneration technique to optimize power consumption and linearity. To minimize complexity and enhance stability, a 1-bit quantizer with isolation switches and return-to-zero (RZ) digital-to-analog converters (DACs) are used in the modulator. With a 500 kHz bandwidth, the sensitivity of the receiver is −105.5 dBm. Fabricated in a 180 nm standard CMOS process, the prototype achieves a peak signal-to-noise ratio (SNR) of 76.1 dB and a signal-to-noise and distortion ratio (SNDR) of 75.3 dB, resulting in a Schreier figure of merit (FoM) of 160.7 dB based on SNDR, while consuming only 0.8 mA from a 1.8 V supply. Full article

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB. Full article

This paper presents a low-power CMOS receiver with a complex continuous-time delta–sigma ADC designed for IoT applications in the 2.4 GHz band. The architecture employs a quadrature bandpass continuous-time delta–sigma ADC optimized for Bluetooth Low Energy (BLE) standards, achieving an ENOB of 10.9 bits while consuming only 0.81 mW from a 1.0 V supply. The receiver demonstrates impressive performance metrics, including a sensitivity of −95 dBm at a 10⁻³-bit error rate, an image rejection ratio of 54.2 dBc, and a spurious-free dynamic range of 79.8 dBc. Operating at a 1.5 MHz intermediate frequency with a 2 MHz bandwidth, the ADC achieves superior energy efficiency with a figure of merit (FOM_W) of 103.2 fJ/conv. Implemented in 28 nm CMOS technology, the complete receiver occupies 0.375 mm² for the RF front-end and 0.145 mm² for the ADC while consuming 4.08 mW total power, making it well suited for battery-powered IoT sensor nodes requiring both power efficiency and reliable wireless connectivity. Full article

Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs. Full article

The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown. Full article

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW. Full article

Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator ($\Sigma \Delta$M) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of $\Sigma \Delta$M. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC $\Sigma \Delta$M simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC $\Sigma \Delta$M, 4th Order Magnetically Coupled $\Sigma \Delta$M and 4th Order Capacitively Coupled $\Sigma \Delta$M. Full article

Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm² while achieving input-referred noise levels of 6.26 and 3.54 µV_rms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mV_pp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces. Full article

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth. Full article

In this work, an idea of a wideband, precision, power electronics programmable voltage source (PVS) is presented. One of the basic elements of the converter, the control section, contains a continuous-time sigma-delta modulator (SDM) with a pair of interconnected complementary comparators, which represents a new approach. In this case, the SDM uses comparators with a dynamic hysteresis loop (DHC) that includes an AC circuit rather than an R-R network. Dynamic hysteresis is a very effective way of eliminating parasitic oscillation during the signal transition at the input of the comparator; it also affects the frequency characteristics and, especially, the phase properties of the comparator, and this phenomenon is exploited in the proposed converter. The main disadvantage of all pulse-modulated converters is the presence of a ripple component in the output voltage (current), which reduces the quality of the output signal and may cause high-frequency disturbances. A basic feature of PVS is a lower RMS value for the pulse modulation component in the output voltage of the converter, compared to the typical value. Another important feature of the proposed converter is the ability of precise mapping of the output voltage to the reference (input) signal. The structure of the control circuit is relatively simple—no complex, digital components are used. Due to the high frequency of the SDM output bit-stream, the simulation model of the power stage of PVS is based on the power modules with gallium-nitride field effect transistors (GaN FETs). The work discusses the rules of PVS operations and the results from PVS simulation model studies as well as highlights the possible application fields for systems with a PVS. Full article

This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm². The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C. Full article

The switching noise and conversion efficiency of step-up DC-DC converters need to be improved to meet increasing demand. The delta-sigma modulation (DSM) technique is typically used to improve the performance of buck converters; however, this control scheme is not directly applicable for boost converters. This paper presents a boost DC–DC converter using a continuous-time delta-sigma modulator (DSM) controller for battery-powered and noise-sensitive applications. The proposed converter can adjust a wide range of output voltages dynamically by clamping the maximum duty cycle of the DSM, thus enabling stable and robust transient responses of the converter. The switching harmonics in the converter output are reduced effectively by the noise shaping property of the modulator. Moreover, the converter does not suffer from instability of mode switching due to the use of a fixed third-order DSM. Fabricated in a 180 nm CMOS, the converter occupies an active area of 0.76 mm². It produced an output voltage ranging from 2.5 V to 5.0 V at an input voltage of 2.0 V and achieved a peak conversion efficiency of 95.5%. The output voltage ripples were maintained under 25 mV for all load conditions. A low noise output spectrum with a first spurious peak located −91 dBc from the signal was achieved. Full article