Minimalist Continuous-Time Delta-Sigma Modulators for Ultra-Low-Voltage Current-Sensing Front-Ends

Abstract

For next-generation biomedical and biochemical sensor nodes, the analog front-end demands a direct interface with current-output sensors, extreme miniaturization, and nanowatt power consumption to enable energy autonomy. This work directly addresses these needs by presenting a comparative analysis of four minimalist, first-order, current-mode $\Delta \Sigma$ modulator ($\Delta \Sigma$M) architectures. Optimized for ultra-low-voltage operation (supply $\le 0.5$ V), the investigated topologies—including resistive, switched-capacitor, and current-reference-based cores—exploit passive integration and charge-domain feedback, eliminating the need for power-hungry active blocks. Detailed circuit-level simulations confirm that, with ad hoc techniques, it is possible to achieve stable first-order noise shaping in the deep near-threshold region, delivering up to 10-bit resolution while consuming less than 10 nW at a 0.5 V supply voltage achieving a signal bandwidth in the sub-10 hertz range. This study validates that robust $\Delta \Sigma$ conversion is feasible under extreme area and power constraints by leveraging architectural simplicity. The clear performance–complexity trade-offs outlined make these current-mode architectures ideal candidates for monolithic integration within miniaturized, energy-autonomous sensing systems.

1. Introduction

Delta-Sigma modulators ($\Delta \Sigma$Ms) are pivotal components in high-resolution analog-to-digital converters (ADCs), bridging the analog sensor world with digital processing domains. Their unique noise-shaping property makes them the architecture of choice for diverse applications, from audio processing and wireless communications to the demanding arena of ultra-low-power (ULP) sensor interfaces [1,2]. In particular, the proliferation of wearable biomedical and biochemical monitoring systems [3,4,5] has driven the need for ADCs that excel under extreme constraints: direct interface with current-output transducers, nanowatt power budgets, sub-0.5 V operation, and minimal silicon area for multi-channel readout integrated circuits (ROICs) [6,7]. Given that many physiological and chemical signals—such as those from glucose monitoring or slow-varying electrochemical sensors—occupy very low frequencies, the target bandwidth for such interfaces is typically in the sub-10 Hz range.

$\Delta \Sigma$Ms are broadly classified into discrete-time (DT) and continuous-time (CT) implementations. DT-$\Delta \Sigma$Ms, typically based on switched-capacitor circuits, offer robust coefficient control and low sensitivity to clock jitter, making them mature solutions for medium-to-high performance applications [8,9,10]. However, their precise charge-transfer mechanisms often limit efficient operation at ultra-low voltages (ULV), although recent work has demonstrated sub-0.5 V switched-capacitor $\Delta \Sigma$ modulators [11,12]. In contrast, CT-$\Delta \Sigma$Ms provide inherent anti-aliasing filtering, higher bandwidth potential, and, crucially, superior power efficiency and adaptability to ULV supplies, making them particularly attractive for ULP sensor front-ends [13,14,15].

The pursuit of higher dynamic range and resolution in CT-$\Delta \Sigma$Ms has led to extensive research on second and higher-order loops, employing active-RC, Gm-C, or other integrator techniques [16,17,18,19]. Advanced studies have also focused on mitigating inherent CT challenges such as clock jitter sensitivity and excess loop delay [20,21]. While successful, these high-order designs often incur significant costs: increased circuit complexity, higher bias currents, greater area, and reduced energy efficiency. This complexity penalty is especially detrimental in multi-channel ROICs for sensor arrays, where area and power per channel are paramount [22,23].

A compelling alternative for ULP/ULV sensing is the first-order CT-$\Delta \Sigma$M, whose architecture is illustrated in Figure 1. Its inherent simplicity—requiring only a single integrator, a comparator, and a feedback DAC—promises minimal area and power consumption. When combined with current-mode operation and passive integration, it enables direct interface with current-output sensors (e.g., amperometric electrochemical cells, photodiodes) [24,25,26] while operating deep in the near-threshold region [27,28,29]. Unlike traditional voltage-input $\Delta \Sigma$Ms, which require an input transconductor or resistor to convert a voltage signal into the charge domain, the current-input architectures studied here treat the sensor current as the direct integration operand. This direct-to-modulator interface eliminates the need for an intermediate V-to-I conversion step, significantly reducing the voltage headroom requirements—a critical advantage when $V_{DD}$ is limited to 0.4 V. Despite its potential, this minimalist approach has received limited exploration compared to its higher-order counterparts [30]. A systematic comparison of such minimalist topologies is needed to chart the performance–complexity trade-offs for current-sensing applications.

This work directly addresses this gap by presenting a comprehensive comparative analysis of four minimalist, first-order, current-mode CT-$\Delta \Sigma$M architectures optimized for ULV current-sensing. The topologies—including switched-capacitor, inverter-based comparator, and current-reference-based cores—are designed to operate with a supply voltage below 0.5 V, taking advantage of passive integration and charge-domain feedback to eliminate power-hungry active blocks. The study validates, through detailed circuit-level simulations performed in an n-well 180-nm CMOS technology, that robust noise shaping and up to 10-bit resolution are achievable for a signal bandwidth of 6 Hz with nanowatt power consumption, making these architectures ideal candidates for area- and power-constrained multi-channel sensor ROICs.

The remainder of this paper is organized as follows. Section 2 details the four proposed CT-$\Delta \Sigma$M architectures and their operating principles. Section 3 presents the simulation methodology and comparative results. Finally, Section 4 concludes the paper.

2. Continuous-Time First-Order Delta-Sigma Modulators: Architecture Overview

This section presents the four proposed minimalist, current-mode, continuous-time Delta-Sigma modulators (CT-$\Delta \Sigma$Ms). The comparative analysis is conducted under consistent operating conditions to isolate the impact of the feedback DAC architecture. All modulators share a sampling frequency ($f_s$) of 12.5 kHz and an oversampling ratio (OSR) of 1024, resulting in an effective signal bandwidth of approximately 6.1 Hz. The designs are implemented in a standard 180 nm CMOS process and operate from an ultra-low supply voltage ($V_{DD}$) of 0.4 V. An input current comprising a DC component of 20 nA superimposed on a sinusoidal component with a full-scale amplitude of 20 nA is used for characterization. The evaluation metrics are the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), and total power consumption.

2.1. Common Building Blocks

All four architectures are built upon two shared, power-optimized analog blocks: a passive current integrator and a dynamic comparator.

2.1.1. Current-Mode Passive Integrator

The loop filter is implemented as a passive, current-mode, capacitor-based integrator. It performs continuous-time integration of the error current between the input signal and the feedback DAC current. This is realized using a single integration capacitor $C_{int}=240$ pF. This choice eliminates the power-hungry active operational transconductance amplifier (OTA) typically required in active-RC or Gm-C integrators, drastically reducing static power dissipation and simplifying design for ultra-low-voltage (ULV) operation [27,31]. As discussed below, such a large value is required to minimize the impact of non-idealities of the passive current-mode modulator.

The integrator output voltage $V_{int}\left(t\right)$ is given by

$$V_{int}\left(t\right)={\int }_0^t{\displaystyle \frac{1}{C_{int}}}\left(I_S\left(t^{\prime }\right)-I_{FB}\left(t^{\prime }\right)\right)d{t}^{\prime }+V_{int}\left(0\right).$$

(1)

In a standard CMOS process, implementing a 240 pF linear capacitor using only Metal–Insulator–Metal (MIM) options would consume a prohibitively large silicon area. To achieve a compact implementation, we realized $C_{int}$ as a non-linear, zero-threshold-voltage NMOS capacitor ($C_{\mathrm{MOS}}$). For the resulting MOSCAP device, the following capacitance to gate–voltage relation applies [32]:

$$C_{\mathrm{MOS}}\left(V_{int}\right)={\displaystyle \frac{C_{\mathrm{ox}}·W·L}{\sqrt{1+\frac{V_{int}-V_{\mathrm{FB}}}{2{\varphi }_F}}}},$$

(2)

where $C_{\mathrm{ox}}$ is the gate oxide capacitance per unit area, W and L are the device dimensions, $V_{\mathrm{FB}}$ is the flat-band voltage, and ${\varphi }_F$ is the Fermi potential.

The MOS capacitor is biased around 200 mV ($V_{DD}/2$). Within the closed-loop $\Delta \Sigma$ modulation, the integrator voltage $V_{int}$ exhibits a statistical distribution; its typical excursion range ($\Delta V_{int}$) is contingent upon the input signal amplitude, feedback current level, sampling period, and the loop dynamics. For the chosen parameters ($C_{int}\approx 240$ pF, $I_S\le 50$ nA, $f_s=12.5$ kHz), transient simulations show that $\Delta V_{int}$ remains bounded within approximately 20–30 mV for typical operating conditions. This bounded excursion helps confine operation to a region of the C–V curve where capacitance variation is moderate, thereby mitigating the impact of non-linearity on overall modulator performance.

This bounded excursion confines the signal-dependent integration gain introduced by the non-linear capacitance to a moderate level. While this gain variation can potentially degrade harmonic distortion and reduce the overall SNDR, for the target resolution (ENOB $\le 10$ bits), such controlled non-linearity is acceptable in exchange for a significant area reduction.

To quantify this trade-off, two preliminary simulations of the modulator in Figure 1 were performed. In both cases, all elements were considered ideal except for the integration capacitor, which was modeled once as a linear MIM capacitor and once as a non-linear zero-threshold MOS capacitor (MOSCAP).

The simulation results, presented in Figure 2, show the output spectrum under the following conditions: an input sine wave of frequency $f_{\mathrm{in}}=1.22$ Hz with 20 nA amplitude superimposed on a 20 nA DC bias, a clock frequency $f_s=12.5$ kHz, and a feedback current $I_{FB}=\pm 50$ nA. The ENOB, evaluated within a 6.1 Hz signal bandwidth, exceeds 11 bits for both implementations. No significant in-band distortion is introduced by the non-linear capacitor, thanks also to the fact that the $V_{int}$ swing is very limited around its average value of 200 mV. This result validates the design trade-off, guiding the physical implementation of the integrator toward a compact yet performance-adequate solution. The resulting MOSCAP area is $793\times 50$ $\mathsf{\mu }{\mathrm{m}}^2$.

More advanced capacitive multiplication techniques are known in the literature, which enable more aggressive silicon area scaling and remain compatible with ultra-low-voltage operation—for example, the technique described in [33]. Although a detailed exploration of these methods is out of the scope of this work, the interested reader is directed to the recent review article [34].

2.1.2. Dynamic Clocked Comparator

A fully dynamic, clocked regenerative comparator samples the integrator output voltage $V_{int}$ and generates the 1-bit digital output. It compares $V_{int}$ to a reference voltage $V_{REF}=V_{DD}/2$ (200 mV). Its schematic is shown in Figure 3.

The comparator adopts an inverter-based architecture optimized for operation at ultra-low supply voltages [19,35]. Its functionality is organized into two non-overlapping phases that jointly implement sampling, amplification, and regenerative decision making.

During the sampling phase, the differential quantity $(V_i-V_{\mathrm{REF}})$ is stored on the hold capacitor $C_H$ ($C_0=200$ fF). The input switches driven by complementary clock phases (CK, nCK) connect the respective nodes such that the instantaneous difference between the signal and reference is directly translated into an equivalent voltage on $C_H$. This phase isolates the subsequent stages from the input and defines the initial condition for the amplifier chain.

In the evaluation phase, the stored voltage on $C_H$ is applied to a cascaded three-stage inverter amplifier. Each stage operates as a gain-boosting element with a self-referenced switching threshold, enabling the overall chain to provide substantial voltage amplification despite the reduced supply headroom. Because the inverters’ switching points depend on device operating conditions rather than an externally imposed bias, the structure inherently tracks process, voltage, and temperature variations, thereby maximizing small-signal gain near the metastable region. As a result, even small deviations around zero differential input are amplified to rail-to-rail levels before entering the regeneration stage.

The amplified output drives a master–slave latch that performs the final regeneration and ensures a fully resolved digital output. The latch is clocked with the same two-phase signals, guaranteeing that decision making occurs only after amplification has settled, and that the output bit is robustly held during the next sampling interval. The combination of charge-based sampling, inverter-based gain, and clocked regeneration yields a comparator capable of reliable operation at very low supply voltages while maintaining adequate speed and noise immunity for $\Delta \Sigma$ modulation.

The comparator employs a differential sampling front-end with an inter-node coupling capacitor $C_0=200$ fF, followed by a cross-coupled inverter latch for regeneration. This topology ensures rail-to-rail digital outputs while consuming zero static power. Transistor sizing, optimized for the 0.4 V supply, is summarized in

Table 1. Transistor sizing for the dynamic comparator.

Parameter	Value (W/L)	Multiplicity
PMOS Devices	0.8 $\mathsf{\mu }$m/0.2 $\mathsf{\mu }$m	4
NMOS Devices	0.2 $\mathsf{\mu }$m/0.18 $\mathsf{\mu }$m	1

. The key design focus was to maintain sufficient regeneration gain ($g_m$) in the deep near-threshold region to achieve a reliable decision within the clock period.

2.2. Feedback DAC Architectures: A Comparative Study

The primary architectural differentiator among the four proposed modulators is the implementation of the 1-bit feedback digital-to-analog converter (DAC). The linearity, noise, and power efficiency of the DAC are critical to overall modulator performance. The four investigated DAC topologies are described below and illustrated in Figure 4.

2.2.1. Architecture A: Resistive-Feedback DAC (RF-DAC)

The first architecture, shown in Figure 4a, employs a simple voltage-to-current conversion using a resistive-feedback DAC. The comparator’s digital output is buffered by two inverter stages to restore full rail-to-rail logic levels. These signals drive a complementary switch pair (Mp, Mn), which connects a resistor $R_{FB}$ to either $V_{DD}$ or ground. As it will be discussed later, this creates an average feedback current $\mathbb{E}\left\{I_{FB}\right\}=\pm V_{DD}/(2\times R_{FB})$ that is injected into the summing node at the integrator input. Since $V_{REF}$ is obtained by the voltage division of a series of two nominally identical PMOS operating in deep cut-off region, the DAC is inherently $V_{DD}$-ratio-metric, meaning its output current is directly proportional to the supply voltage.

A more analytical approach can be provided as follows. With the notation

$$b\left(t\right)\in \{-1,+1\}$$

(3)

representing the instantaneous digital output ($+1$ when the resistor is connected to $V_{DD}$, $-1$ when connected to ground), the instantaneous feedback current injected into the summing node is

$$I_{FB}\left(t\right)=\left\{\begin{array}{cc}{\displaystyle \frac{V_{DD}-V_{int}\left(t\right)}{R_{FB}}},\hfill & b\left(t\right)=-1,\hfill \\ {\displaystyle \frac{V_{int}\left(t\right)}{R_{FB}}},\hfill & b\left(t\right)=+1.\hfill \end{array}\right.$$

(4)

This can be written in the compact form

$$I_{FB}\left(t\right)={\displaystyle \frac{1+b\left(t\right)}{2}}·{\displaystyle \frac{V_{DD}}{R_{FB}}}-{\displaystyle \frac{V_{int}\left(t\right)}{R_{FB}}}.$$

(5)

Two observations follow directly from (5):

(i)

A $V_{int}$-dependent term is always present: Regardless of the bit value, there is an additive term $-V_{int}\left(t\right)/R_{FB}$. Taking the time average (or expectation) of (5) for a bit stream with mean $m\equiv \mathbb{E}\left\{b\right(t\left)\right\}$:

$$\mathbb{E}\left\{I_{FB}\left(t\right)\right\}={\displaystyle \frac{1+m}{2}}·{\displaystyle \frac{V_{DD}}{R_{FB}}}-{\displaystyle \frac{\mathbb{E}\left\{V_{int}\left(t\right)\right\}}{R_{FB}}}.$$

(6)

While the modulator is stable (i.e., it does not produce a divergent behavior of $V_{int}\left(t\right)$): $\mathbb{E}\left\{V_{int}\left(t\right)\right\}=V_{REF}=V_{DD}/2$ and, consequently, $\mathbb{E}\left\{I_{F}B\left(t\right)\right\}=\mathbb{E}\left\{I_S\left(t\right)\right\}$. Hence,

$$\mathbb{E}\left\{I_S\left(t\right)\right\}={\displaystyle \frac{m}{2}}·{\displaystyle \frac{V_{DD}}{R_{FB}}}\Rightarrow m={\displaystyle \frac{2R_{FB}}{V_{DD}}}·\mathbb{E}\left\{I_S\left(t\right)\right\}.$$

(7)

This relationship demonstrates the linear dependence of the DC output stream to the DC of the input signal.

(ii)

For a discrete-time forward Euler integrator with sampling period T:

$$\begin{array}{cc}\hfill V_{int}[n+1]& =V_{int}\left[n\right]+{\displaystyle \frac{1}{C_{int}}}{\int }_{nT}^{(n+1)T}\left(I_S\left(t\right)-I_{FB}\left(t\right)\right)dt\hfill \\ \hfill & =V_{int}\left[n\right]+{\displaystyle \frac{1}{C_{int}}}{\int }_{nT}^{(n+1)T}{I}_S\left(t\right)dt+{\displaystyle \frac{1+b\left[n\right]}{2}}{\displaystyle \frac{V_{DD}T}{R_{FB}{C}_{int}}}-{\displaystyle \frac{1}{R_{FB}{C}_{int}}}{\int }_{nT}^{(n+1)T}{V}_{int}\left(t\right)dt\hfill \end{array}$$

(8)

The derived difference equation for the integrator output voltage, $V_{int}[n+1]$, reveals a critical deviation from the ideal, standard model of a first-order $\Delta \Sigma$ modulator. While the standard discrete-time model is characterized by a clean accumulation of the integral of the input current and a digital feedback current quantized to two levels, our model includes an additional, analog-dependent term:

$$-{\displaystyle \frac{1}{R_{FB}{C}_{int}}}{\int }_{nT}^{(n+1)T}{V}_{int}\left(t\right)dt.$$

(9)

This term arises physically because the feedback DAC is not an ideal current source. It is a voltage-mode switched resistor. Consequently, the feedback current, $I_{FB}\left(t\right)$ is not solely determined by the digital code $b\left(t\right)$ and the reference voltage $V_{DD}$, but is also linearly modulated by the instantaneous voltage $V_{int}\left(t\right)$ at the summing node, as seen in Equation (5). This introduces a linear, time-varying, negative feedback path through the resistor $R_{FB}$ that is always active, regardless of the DAC switch state.

The previous analysis highlights several impacts on the modulator dynamics:

1.

Effective Integration Time Constant: The parasitic term is proportional to the integral of $V_{int}\left(t\right)$ itself. This is mathematically equivalent to adding a leaky or lossy component to the ideal integrator. The difference equation can be reinterpreted as

$$V_{int}[n+1]=\left(1-{\displaystyle \frac{T}{R_{FB}{C}_{int}}}\right)V_{int}\left[n\right]+\Delta V_S\left[n\right]+\Delta V_{FB}\left[n\right]+\mathcal{H},$$

(10)

where $\Delta V_S\left[n\right]$ and $\Delta V_{FB}\left[n\right]$—respectively, corresponding to terms ${\displaystyle \frac{1}{C_{int}}}{\int }_{nT}^{(n+1)T}{I}_S\left(t\right)dt$ and ${\displaystyle \frac{1+b\left[n\right]}{2}}{\displaystyle \frac{V_{DD}T}{R_{FB}{C}_{int}}}$ in (8)—are the ideal input and feedback increments, and $\mathcal{H}$ represents higher-order terms from the precise integration of the time-varying $V_{int}\left(t\right)$. The coefficient $(1-{\displaystyle \frac{T}{R_{FB}{C}_{int}}})$ indicates that the pole of the integrator is not at the ideal DC ($z=1$) but is shifted inside the unit circle, located at $z=1-T/\left(R_{FB}{C}_{int}\right)$. This reduces the DC gain of the integrator, which is the key building block for shaping quantization noise.

2.

Effects on noise shaping: In linearized models of DSM, the suppression of quantization noise is directly related to the gain of the integrator within the signal band. A finite DC gain $A_0$ modifies the first-order noise transfer function (NTF) from $1-z^{-1}$ to $(1-z^{-1})/(1-z^{-1}/A_0)$. The parasitic feedback path effectively sets $A_0\approx R_{FB}{C}_{int}/T$. This limits the achievable noise shaping, causing the in-band quantization noise floor to saturate rather than decrease indefinitely for $f\to 0$. A first-order estimation shows that the maximum SQNR improvement from oversampling is capped at approximately [1]

$${\mathrm{SQNR}}_{\max }\approx A_0^2={\left({\displaystyle \frac{R_{FB}{C}_{int}}{T}}\right)}^2.$$

(11)

3.

Signal-Dependent Feedback and Non-Linearity: While the time-average of the $V_{int}$-dependent term cancels for a stable modulator with $\mathbb{E}\left\{V_{int}\right\}=V_{REF}$, its instantaneous effect is signal-dependent. This introduces a non-linear distortion mechanism. The feedback current is not a clean, two-level waveform but is “contaminated” by the analog integrator output. This distortion is distinct from and potentially more harmful than the simple gain error described in point (i) of the previous analysis, as it generates harmonic tones.

4.

Design Implication: the $R_{FB}{C}_{int}$ time constant. The analysis reveals that the product $R_{FB}{C}_{int}$ is a crucial design parameter. For the modulator to approach ideal behavior,

$$R_{FB}{C}_{int}\gg T.$$

(12)

This condition ensures the parasitic leak is small, restoring high integrator gain. However, increasing $R_{FB}$ reduces the feedback current step size ($\propto V_{DD}/R_{FB}$), which can compromise stability for a given input range. Increasing $C_{int}$ is, on the other hand, viable without compromising input full-scale stability, at cost of silicon area. Thus, selecting $R_{FB}$ and $C_{int}$, once the product $R_{FB}{C}_{int}$ is fixed in order to satisfy (12), represents a fundamental trade-off between the modulator input full-scale and area (cost).

The primary design priority is to satisfy the integrator gain condition $R_{FB}{C}_{int}\gg T$ from (12). This can be achieved by increasing either $R_{FB}$ or $C_{int}$. However, these choices have divergent effects:

• Increasing $R_{FB}$ reduces the nominal feedback current step. While simulations show stability can be maintained over a wider range than the simple $V_{DD}/R_{FB}$ relation suggests, it ultimately reduces the loop gain available to correct large input currents, thereby compressing the stable input range.
• Increasing $C_{int}$ directly satisfies (12) without altering the DAC’s current drive, preserving the intrinsic feedback strength. Its penalty is increased silicon area.

Consequently, selecting the $R_{FB}{C}_{int}$ pair involves navigating a trade-off between the modulator’s stable input range and its physical size. Electrical simulations show that for a 240 pF $C_{int}$, a 40 nA peak-to-peak stable input fullscale is obtained with $R_{FB}$ = 5 MΩ.

Potential for digital compensation of the signal-dependent distortion previously highlighted is fundamentally limited. While the non-linearity arises from a known and deterministic mechanism—the parasitic feedback current proportional to $V_{int}$—effective correction would require precise, real-time knowledge of this internal analog state. However, $V_{int}$ is obscured by the large, shaped quantization noise and is only indirectly observed through the single-bit output $b\left[n\right]$, making accurate estimation impractical. Furthermore, any compensation algorithm would need to track variations in $R_{FB}$ and $C_{int}$ over PVT, adding calibration complexity that negates the architectural simplicity of the RF-DAC approach. Consequently, rather than attempting digital post-correction of this inherent distortion, more efficient solutions are explored to avoid distortion generation altogether.

2.2.2. Architecture B: Switched-Capacitor DAC (SC-DAC)

The second architecture, shown in Figure 4b, replaces the continuous resistive feedback with a discrete-time switched-capacitor (SC) feedback network. This approach generates the feedback current through controlled charge redistribution, decoupling the integration time constant from the feedback scaling factor.

Two identical branches, each consisting of a capacitor $C_{FB}$ and complementary switches, operate in a time-interleaved fashion using non-overlapping clock phases ${\theta }_1$ and ${\theta }_2$. During phase ${\theta }_1$, one branch samples either $V_{DD}$ or ground according to the comparator output. During phase ${\theta }_2$ the same branch is connected to the integrator node. Hence, at each phase n, a charge equal to $C_{FB}\left({\displaystyle \frac{1+b\left[n\right]}{2}}\right)V_{DD}$ is stored into one of the two $C_{FB}$ elements. Based on the principle of charge conservation between the feedback capacitor $C_{FB}$ and the integration capacitor $C_{int}^{\prime }$, we can establish the following relationship at the end of each phase, provided that sufficient time for any transient to extinguish is available:

$$C_{FB}\left({\displaystyle \frac{1+b\left[n\right]}{2}}\right)V_{DD}+C_{int}^{\prime }{V}_{int}\left[n\right]=(C_{int}^{\prime }+C_{FB})V_{int}[n+1].$$

(13)

With the following definitions,

$$\Delta V_{int}[n+1]=V_{int}[n+1]-V_{int}\left[n\right]\mathrm{and}\Delta Q[n+1]=(C_{int}^{\prime }+C_{FB})\Delta V_{int}[n+1],$$

(14)

Equation (13) can be elaborated to obtain

$$\Delta Q[n+1]=C_{FB}\left({\displaystyle \frac{1+b\left[n\right]}{2}}{V}_{DD}-V_{int}\left[n\right]\right)$$

(15)

The second branch performs the complementary sequence, ensuring that at least one branch is always delivering charge. This time-interleaving prevents interruption of the loop and yields a quasi-continuous feedback action.

Averaging the charge transferred, expressed by Equation (15) over the switching period T, each branch produces an equivalent feedback current

$$\langle I_{FB}\rangle ={\displaystyle \frac{\Delta Q}{T}}={\displaystyle \frac{C_{FB}}{T}}\left({\displaystyle \frac{1+b\left[n\right]}{2}}{V}_{DD}-V_{int}\left[n\right]\right),$$

(16)

which, when compared to the expression of Equation (5), matches (on average) the behavior of the resistive DAC in Architecture A when

$${\displaystyle \frac{C_{FB}}{T}}={\displaystyle \frac{1}{R_{FB}}}.$$

(17)

Because $C_{FB}$ periodically appears in parallel with the integration capacitor during the transfer phase, the physical integration capacitor is reduced to $C_{int}^{\prime }=C_{int}-C_{FB}$, ensuring the net capacitance seen during the evaluation phase equals the target $C_{int}$. The equivalence expressed in Equation (17) can be obtained also from general application of the nodal analysis of switched-capacitor networks [36,37].

This SC implementation maintains $V_{DD}$-ratiometric operation while improving PVT robustness: the key feedback coefficient is now determined by the capacitor ratio $C_{FB}/(C_{int}^{\prime }+C_{FB})$ and the clock period T, rather than by the absolute value of a passive resistor. Compared to Architecture A, the SC-DAC offers two principal advantages. First, it achieves far greater area efficiency: the required $C_{FB}$ for a given average feedback current is typically orders of magnitude smaller than the $C_{int}$ needed in Architecture A to satisfy $R_{FB}{C}_{int}\gg T$. For the same input-current full-scale current at $12.5\mathrm{kHz}$ ($T=80\mathsf{\mu }\mathrm{s}$), $C_{FB}=T/R_{FB}=16\mathrm{pF}$, which is one order of magnitude smaller with respect to the $240\mathrm{pF}$ integration capacitor. Second, it enables more precise coefficient matching; in integrated technologies, capacitor ratios offer better accuracy and temperature stability compared to poly or diffusion resistors.

Despite these advantages, the SC-DAC introduces several implementation challenges. Finite switch resistance and limited phase time result in incomplete charge transfer, effectively scaling the feedback gain and requiring non-minimal sizing of switches relative to $C_{FB}$ and sufficient phase duration. Moreover, the signal-dependent feedback non-linearity and the limited noise-shaping capability discussed for the Architecture A modulator remain inherent to this implementation.

2.2.3. Architecture C: Current-Reference DAC (CR-DAC)

The third architecture, shown in Figure 4c, decouples the feedback current from the supply voltage by using an on-chip current reference rather than a $V_{DD}$-ratiometric mechanism. A master reference current $I_{REF}$ (e.g., $1\mathrm{nA}$) is generated by a dedicated biasing block and mirrored with a gain factor K to produce the feedback current $I_{FB}=K{I}_{REF}$. The use of a high mirror gain ($K=64$) minimizes the static power overhead of the reference branch while providing a feedback current sufficient to cover the input full-scale ($I_{FS}$) range of approximately 64 nA. A complementary switch pair, driven by the bitstream $\mathtt{bs}$, either routes this current into the integrator through M2 ($\mathtt{bs}=1$) or turns M2 off ($\mathtt{bs}=0$), implementing a 1-bit DAC. This topology provides unidirectional feedback (a current sink), consistent with the non-negative nature of the sensor current $I_S$, thus simplifying the DAC structure.

A key advantage of this architecture is its high output impedance. Once settled, the output transistor M2 operates as a current source, making $I_{FB}$ virtually independent of the summing-node voltage $V_{int}$. This eliminates the signal-dependent feedback distortion inherent in Architectures A and B and avoids the sampling noise and switching transients of Architecture B.

However, the CR-DAC introduces distinct challenges. First, generating a stable nanoampere-level reference across PVT corners requires a dedicated low-power biasing circuit (e.g., a subthreshold PTAT/CTAT-compensated reference), which adds design complexity and static power [38,39,40,41,42]. In contrast, Architectures A and B use passive or switched-passive components that consume no static power. Second, the accuracy of $I_{FB}$ is limited by current-mirror mismatch, channel-length modulation, and sensitivity to drain-voltage variations. As the drain of M2 follows the large-signal excursions of the integrator output, the finite output resistance $r_o$ introduces DAC gain error and signal-dependent non-linearity—partially analogous to the non-linearities in Architectures A and B, but mitigable through design techniques such as using non-minimum channel lengths for M1 and M2.

The most significant non-ideality in this architecture stems from the finite settling of the output current during switching events. When the DAC is turned on, the gate capacitance of the output transistor must be charged through the series switch; when turned off, it is discharged through the shunt switch. A detailed analytical description of these processes is provided in [43]; for the present analysis, a simplified exponential RC relaxation model suffices. The resulting settling transient has a time constant ${\tau }_{\mathrm{sw}}\approx R_{\mathrm{sw}}{C}_{\mathrm{g},\mathrm{out}}$, where $R_{\mathrm{sw}}$ is the on-resistance of the active switch and $C_{\mathrm{g},\mathrm{out}}$ is the total gate capacitance of the output transistor. If the switching period T is not significantly larger than ${\tau }_{\mathrm{sw}}$, the current at the end of a clock phase depends on the previous DAC state. This history dependence averages the charge delivered per cycle is determined not only by the current digital code $b\left[n\right]$ but also by the preceding code $b[n-1]$.

This effect is directly analogous to Inter-Symbol Interference (ISI) in communication systems: the intended current pulse is distorted by residual transients from prior symbols. In a $\Delta \Sigma$ modulator, such dynamic distortion introduces a non-linear, data-dependent error in the feedback charge, translating into harmonic distortion in the output spectrum. The severity of the distortion increases with the ratio ${\tau }_{\mathrm{sw}}/T$ and becomes particularly problematic when switch gates are driven with low voltages (increasing $R_{\mathrm{sw}}$) or when mirror transistors are sized for high output impedance (increasing $C_{\mathrm{g},\mathrm{out}}$). Given the clock frequency dictated by system-level specifications, this ISI-like settling becomes the primary bottleneck for the achievable resolution of Architecture C—a limitation only resolved by Architecture D.

The unidirectional feedback also shifts the loop’s operating point relative to Architectures A and B. Because the bitstream can only remove current from the integrator, the average input current must satisfy $I_S<I_{FB,\mathrm{avg}}$ to avoid integrator saturation. Consequently, the modulator requires careful biasing and selection of $I_{FB}$ to ensure sufficient dynamic range while maintaining stability. This contrasts with Architectures A and B, whose symmetric DAC accommodates bipolar feedback.

Finally, the noise mechanisms of the CR-DAC differ substantially from those of the previous architectures. The current mirror introduces both thermal and flicker ($1/f$) noise directly into the signal path—contributions absent in the passive resistor of Architecture A and present only during switching events in Architecture B (kT/C noise). A particularly effective technique for suppressing flicker noise in the current reference can be implemented by exploiting the multi-element structure of the 1:K mirror itself. Figure 5 shows an implementation of a multi-phase chopper stabilization principle applied to a generic current mirror ($K=2$).

The mirror of Figure 4d is composed of $K+1$ nominally identical unit elements. Each element contributes flicker noise that, when the element is placed in the input (reference) branch, is amplified by the mirror gain K and appears as a positive contribution to the output current; when placed in the output (feedback) branch, it contributes negatively. By cyclically rotating all $K+1$ elements through both input and output roles in a deterministic sequence over $K+1$ clock cycles, each unit experiences exactly K cycles in the input branch and one cycle in the output branch. Over this complete rotation period, the net integrated contribution of each element’s low-frequency flicker noise averages to zero, provided the flicker noise is sufficiently correlated across the switching period. This technique effectively implements a multi-phase chopper stabilization in the current domain, canceling flicker noise contribution to $V_{int}$ without requiring additional capacitors or complex filtering.

Although reminiscent of dynamic element matching (DEM) used in multi-bit DACs for linearity improvement, here, the mechanism is tailored specifically to cancel $1/f$ noise by ensuring each noise source contributes equally in both polarities over time. If ultra-low in-band noise is required, such cycling can be implemented with modest digital overhead (a simple counter plus a basic combinational logic), though it introduces additional switch complexity and potential settling constraints.

2.2.4. Architecture D: Bootstrapped Current-Reference DAC (BS-CR-DAC)

The fourth architecture, shown in Figure 4d, is an enhanced version of Architecture C designed to overcome the switch linearity limitations inherent in the basic current-steering design. It achieves this by employing bootstrapped switches in the gate-drive path of the M1–M2 current-steering pair.

The bootstrapping circuit (indicated by the “BS” block in Figure 4d) maintains a constant gate-source voltage ($V_{GS}$) across the steering switch during its conduction phase [44,45]. This is achieved independently of the voltage at the switch’s source node (i.e., the integrator summing point). By ensuring a stable $V_{GS}$, the circuit minimizes variations in on-resistance, thereby reducing harmonic distortion and improving the overall SNDR compared to the basic current-reference DAC.

The primary trade-off for this improved linearity is a modest increase in circuit complexity and power consumption. The bootstrapping circuitry requires additional switches, capacitors—which are small relative to the integration capacitor $C_{int}$—and non-overlapping clock phases. This results in a slight increase in silicon area and dynamic power. Architecture D, therefore, represents a viable choice for applications where enhanced SNDR is critical, even within the constraints of ultra-low-voltage and low-power operation. Detailed electrical simulations presented in the following section will quantify this specific performance–complexity trade-off.

2.3. Summary of Architectural Features

Table 2. Summary and comparison of the four proposed feedback DAC architectures for ultra-low-voltage CT-$\Delta \Sigma$Ms.

Architecture	DAC Core	Key Advantages	Primary Limitations
A: RF-DAC, Figure 4a	Resistive	Minimal complexity Predominantly passive implementation	Leaky integrator limits achievable ${\mathrm{SQNR}}_{max}$ Supply-dependent ($V_{DD}$-ratio-metric) High sensitivity to PVT corners
B: SC-DAC, Figure 4b	Switched-Capacitor	Good component matching	Shares limitations of Architecture A Switching noise and charge injection
C: CR-DAC, Figure 4c	Current-Reference	Reduced integrator leakage, enabling higher ${\mathrm{SQNR}}_{max}$ for a given OSR and $f_s$ compared to Architectures A and B.	Current mirror turn-on delay introduces distortion Requires an auxiliary current reference circuit
D: BS-CR-DAC, Figure 4d	Bootstrapped Current-Reference	Mitigates distortion by reducing the current mirror’s turn-on delay	Highest complexity (requires bootstrapping auxiliary circuit) Extra dynamic power consumption

summarizes the key characteristics of the four feedback DAC architectures, highlighting their fundamental trade-offs in complexity, supply dependence, and expected performance.

3. Results and Discussion

3.1. Nominal Simulations

To investigate the feasibility of the different proposed architectures in aggressively scaled energy-constrained environments, they were simulated under an ultra-low supply voltage of 0.4 V using Cadence Spectre’s NOISETRAN analysis. The spectral performance of the four architectures was evaluated using a sinusoidal input current ($I_{in}=20{\mathrm{nA}}_{\mathrm{DC}}+20{\mathrm{nA}}_{peak}·sin\left(2\pi f_{in}t\right)$) at a frequency $f_{in}$ of 1.52 Hz. This frequency was specifically chosen to capture up to the third harmonic within the signal bandwidth (6.1 Hz), enabling a clear assessment of non-linear distortion. Power spectral densities (PSDs) were computed via a 16,384-point FFT to provide sufficient frequency resolution for the targeted oversampling ratio.

The following analysis summarizes the key behaviors observed in the frequency-domain response and amplitude-domain behavior, links them to the fundamental device-level mechanisms that dominate at such low supply levels, and evaluates the resulting performance metrics.

The resistive-feedback DAC-based modulator ($\Delta \Sigma$M-A) is evaluated first. At this low supply voltage, $\Delta \Sigma$M-A exhibits stable limit-cycle behavior and maintains quantization functionality, as reflected by the spectral characteristics and the high-frequency first-order noise-shaping behavior observed in the FFT analysis shown in Figure 6a. Nevertheless, the low-frequency portion of the spectrum is dominated by distortion harmonics. This behavior was anticipated by the analysis provided in Section 2.2.1. The resulting performance demonstrates an SNR of 59.9 dB, a THD of −52.5 dB, corresponding to an SNDR of 51.7 dB, and an effective resolution of 8.3 bits over the signal bandwidth. The average power consumption of the modulator is 8.10 nW.

Using Equation (11), with $R_{FB}=50\mathrm{M}\mathsf{\Omega }$, $C_{int}=240\mathrm{pF}$, and $T=80\mathsf{\mu }\mathrm{s}$, the estimated SQNR_max is approximately 31 dB. The discrepancy with the simulation results can be understood by noting that the full-scale amplitude of the input signal is 40 nA (composed of a 20 nA DC bias plus a 20 nA sinusoidal amplitude), while the maximum amplitude of the feedback current $I_{FB}$ is limited to 4 nA (${\displaystyle \frac{1}{2}}{V}_{DD}/R_{FB}$). As evident from Figure 6b, the modulator reaches a plateau for input signals above −20 dBFS, where performance is dominated by harmonic distortion. It is also worth noting that the thermal noise from the feedback resistor itself is largely negligible in the signal bandwidth, amounting to less than 0.14 nA_RMS.

Figure 7a shows the power spectrum of the $\Delta \Sigma$M-B. The spectrum reveals reduced in-band noise compared to Architecture A ($\Delta \Sigma$M-A), and is now primarily dominated by the third harmonic component. With an average power consumption of 8.11 nW, the $\Delta \Sigma$M-B achieves an SNDR of 55.2 dB, corresponding to an ENOB of 8.9 bits.

The same $\Delta \Sigma$M-B modulator was also tested at $V_{DD}=0.5$ V. With an average power consumption of 10.12 nW, the maximum SNDR improved to 57.4 dB ($\mathrm{ENOB}=9.2$ bits).

The CR-DAC-based modulator ($\Delta \Sigma$M-C) is analyzed next. Its power spectrum, shown in Figure 8a, reveals elevated in-band noise and strong harmonic components dominating the spectrum up to approximately 100 Hz. With an average power consumption of 1.85 nW (including the 1-nA current reference branch), the performance is far from optimal; as shown in Figure 8b, the $\Delta \Sigma$M-C achieves an SNDR of 36.8 dB, corresponding to an ENOB of 5.7 bits. As discussed in Section 2.2.3, the distortion originates from both $V_{DS}$ modulation effects on the DAC transistor responsible for delivering $I_{FB}$ and its associated turn-on transients.

The FFT analysis for the BS-CR-DAC-based modulator ($\Delta \Sigma$M-D) is shown in Figure 9a. It exhibits a cleaner noise-shaping profile, though the in-band noise is dominated by second-harmonic distortion due to the $V_{DS}$ modulation of the DAC feedback transistor discussed in Section 2.2.4. As shown in Figure 9b, the $\Delta \Sigma$M-D achieves an SNDR of 43.8 dB, corresponding to an effective number of bits (ENOB) of 6.9 bits. Furthermore, the dynamic range (DR) derived from Figure 9b is approximately 61.4 dB. These results demonstrate the efficacy of switch bootstrapping in removing the spread-spectrum ISI distortion affecting the CR-DAC ($\Delta \Sigma$M-C). These improvements are achieved without a significant power penalty, as the $\Delta \Sigma$M-D dissipates 2.17 nW on average (including the bootstrapping logic and the 1 nA current reference branch), validating that the proposed $\Delta \Sigma$M-D scheme enhances resolution while maintaining ultra-low-power operation.

The relatively high noise floor in the spectrum (Figure 9a) buries any flicker noise component from the DAC MOSFET devices within the total simulated duration of 10.5 s. Since flicker noise is not the dominant limitation in this implementation, the multi-phase chopper stabilization technique described in Section 2.2.3 was not employed, though it remains an original contribution of this work applicable to scenarios with stricter flicker noise requirements.

For further investigation, the $\Delta \Sigma$M-D was also tested at $V_{DD}=0.5$ V, achieving a maximum SNDR (${\mathrm{SNDR}}_{\max }$) of 62.5 dB ($\mathrm{ENOB}=10.09$ bits) and a DR of 65.2 dB, while consuming 2.22 nW. These improved results are a direct consequence of the reduced impact of $V_{DS}$ effects on the DAC feedback transistor providing the $I_{FB}$ current.

Table 3. Simulated performance summary of the four proposed first-order CT-$\Delta \Sigma$M architectures at $V_{DD}=0.4$ V. ENOB is calculated from SNDR_max; FOM_S is calculated from DR. Main distortion cause, limiting the SNDR, is also shortly resumed for each architecture.

Metric	A: RF-DAC	B: SC-DAC	C: CR-DAC	D: BS-CR-DAC
SNDRmax [dB]	51.7	55.2	36.8	55.0
DR [dB]	61.5	63.0	47.4	61.4
ENOB [bits]	8.3	8.9	5.7	8.8
Power [nW]	8.10	8.11	1.85	2.17
FOMS [dB]	150.3	151.8	142.6	155.9
Main distortion cause	Signal-dependent feedback leakage through R	Charge transfer non-idealities (leakage)	Inter-Symbol Interference (ISI)	Residual ISI + MOS dissaturation

summarizes the simulated performance of the four proposed architectures at a supply voltage of 0.4 V. The comparison includes key metrics such as SNDR, ENOB, power consumption, and the Schreier figure of merit (${\mathrm{FOM}}_{\mathrm{S}}=\mathrm{DR}+10{log}_{10}(\mathrm{BW}/\mathrm{Power})$). The power distribution across different architectures is illustrated in Figure 10.

At 0.4 V, all four designs operate within the targeted ultra-low-power regime, exhibiting power dissipation below 10 nW. Architecture D (BS-CR-DAC) achieves the highest FOM_S of 155.9 dB, confirming the effectiveness of the bootstrapping technique in enhancing linearity. Architecture B (SC-DAC) shows the highest resolution with $\mathrm{ENOB}=8.9$ bits, although with a slightly lower FOM_S (151.8 dB). These two promising architectures were also tested at $V_{DD}=0.5$ V, yielding a notable improvement, with Architecture D reaching a peak ENOB of 10.09 bits, at the cost of a modest increase in power consumption (2.22 nW).

As highlighted in the table, each architecture is characterized by a specific dominant non-ideality that limits its peak resolution. For Architectures A and B, the performance is primarily constrained by signal-dependent feedback leakage (as analytically derived in Section 2.2.1, whereas Architecture C suffers from severe Inter-Symbol Interference (ISI) due to the slow settling of the current-reference DAC (discussed in Section 2.2.3).

To further characterize the dynamic performance of the most promising designs, Figure 11 illustrates the SNDR as a function of the input frequency $f_{in}$ for Architectures B and D. The input frequency is swept from $\mathrm{BW}/15$ (0.4 Hz) up to $\mathrm{BW}/3$ (2 Hz). For Architecture D, the SNDR remains nearly constant across the band, with minor fluctuations (<0.5 dB) attributed to spectral leakage and windowing effects in the FFT. In contrast, Architecture B exhibits a slight degradation at very low frequencies; this is due to the presence of non-negligible higher-order harmonics (5th and 7th) relative to the 3rd, which are more prominent in the SC-DAC implementation.

It should be noted that for $f_{in}>\mathrm{BW}/3$, the 3rd harmonic—which is the dominant distortion component in these first-order loops—begins to fall outside the 6.1 Hz integration bandwidth. While this would result in a numerical improvement in SNDR, such an evaluation would be misleading as it fails to capture the core non-linearities of the modulator. Therefore, the characterization is focused on the region where the primary distortion products are fully accounted for within the signal bandwidth.

3.2. Robustness Analysis

Given the stringent 0.4 V supply, global process corners—Slow–Slow (SS) and Fast–Fast (FF)—were selected as the primary robustness metric, as they represent the most critical boundaries for subthreshold device transconductance and leakage. While Monte Carlo analysis provides statistical distribution, the corner analysis performed here identifies the absolute worst-case operating conditions, ensuring that the proposed architectures remain functional and efficient across the entire manufacturing spread. The results, summarized in

Table 4. Robustness analysis: effect of process corners at $V_{DD}=0.4$ V ($I_{in}=20{\mathrm{nA}}_{\mathrm{DC}}\pm 20{\mathrm{nA}}_{\mathrm{peak}}$ at $f_{in}=1.52$ Hz).

Corner	Architecture B (SC-DAC)			Architecture D (BS-CR-DAC)
	TYP	SS	FF	TYP	SS	FF
SNDR [dB]	55.21	51.41	47.45	54.96	53.95	63.95
ENOB [bits]	8.88	8.25	7.59	8.84	8.67	10.33
$\Delta$SNDR [dB]	—	$-3.80$	$-7.76$	—	$-1.01$	$+8.99$

, demonstrate distinct behaviors for the two topologies.

Architecture B (SC-DAC) exhibits a performance degradation of approximately 7.8 dB in the FF corner, primarily due to increased subthreshold leakage in the switches, which compromises the integrity of the charge-transfer process. Conversely, Architecture D (BS-CR-DAC) shows remarkable robustness; in the SS corner, the SNDR remains within 1 dB of the nominal value. Interestingly, performance improves in the FF corner (reaching 63.95 dB), as the higher device transconductance and reduced parasitics further alleviate the settling-related ISI identified in Section 2.2.3. This analysis confirms that while both designs are feasible at 0.4 V, Architecture D offers superior resilience to global process variations.

3.3. Frequency Scaling Analysis

To further explore the dynamic limits of the proposed architectures, simulations were performed at a doubled sampling frequency ($f_s=$25 kHz) while maintaining a constant OSR of 1024. Architecture B shows almost the same SNDR 55.02 dB (−0.2 dB), while Architecture D exhibits an improvement in SNDR reaching 60.95 dB (+6 dB). This enhancement is attributed to the reduced impact of leakage in the bootstrapping logic, hence increasing the current-copying accuracy at higher operating speeds. This demonstrates that the architectures are not speed-limited at the nominal 12.5 kHz frequency and offer a flexible trade-off between power and resolution for higher-bandwidth applications.

3.4. Design Guidelines and Trade-Off Regions

Based on the systematic analysis of Architectures A–D, the following guidelines are proposed for designing ULV current-input CT-$\Delta \Sigma$Ms:

1.

Integration Swing vs. Area: In a passive integrator at 0.4 V, the maximum linear swing is limited to approximately $\Delta V_{int,\max }$= 200 mV. To avoid integrator saturation, the maximum voltage step per clock cycle must satisfy $\Delta V_{int,\mathrm{wc}}=I_{FS}T/C_{int}$, where $I_{FS}$ is the sensor full-scale current. With $f_s=1/T$ and given that $\Delta V_{int,\mathrm{wc}}\le \Delta V_{int,\max }$, the minimum integration capacitor is bounded by

$$C_{int}\ge {\displaystyle \frac{I_{FS}}{f_s·\Delta V_{int,\max }}}.$$

(18)

For $I_{FS}=50$ nA and $f_s=12.5$ kHz, this results in the 240 pF value used in this work, establishing a clear area-efficiency limit for current-mode sensing. When utilizing MOSCAPs to save area, the non-linear $C\left(V\right)$ characteristic (Equation (2)) introduces signal-dependent gain variation. Our analysis indicates that while this adds to the total harmonic distortion (THD), the effect remains secondary to DAC-induced leakage at 0.4 V.

2.

Mitigating Signal-Dependent Leakage: According to the analytical considerations derived in Section 2.2.1 and expressed in Equation (12), to ensure that the leakage through the feedback network does not degrade the SNDR below the quantization limit, the sampling frequency must be chosen such that

$$f_s\gg {\displaystyle \frac{1}{R_{FB,\mathrm{eff}}·C_{int}}}$$

(19)

where $R_{FB,\mathrm{eff}}$ is the effective DAC resistance (relevant for Architectures A and B). At ULV, $f_s$ is often capped by digital logic reliability ($f_{limit}$). In such constrained scenarios, Architecture D (BS-CR-DAC) is the superior choice, as it decouples the feedback current from the integrator voltage, effectively linearizing the loop.

3.

Frequency Scaling and Noise vs. Distortion: For sub-10 Hz medium-to-low resolution sensing, while flicker noise is traditionally the bottleneck, ULV operation makes the modulator highly susceptible to switch leakage and settling-induced distortion. Scaling $f_s$ toward $f_{limit}$ (e.g., from 12.5 kHz to 25 kHz) mitigates these effects, yielding a significant +6 dB SNDR improvement. It should be noted that for Architectures A and C, non-idealities manifest as broadband noise, whereas for B and D, they appear as distinct harmonics; thus, the choice of architecture should also consider the spectral requirements of the specific sensing application.

3.5. Comparative Study

A comprehensive performance comparison with state-of-the-art ultra-low-voltage (ULV) and ultra-low-power continuous-time $\Delta \Sigma$ modulators is presented in Table 5. The two most promising architectures proposed in this work—$\Delta \Sigma$M-B and $\Delta \Sigma$M-D—operating at 0.4–0.5 V, are benchmarked against recent low-order continuous-time designs specifically targeting the constrained ULV/ULP design space.

At the lowest operating voltage of 0.4 V, both $\Delta \Sigma$M-B and $\Delta \Sigma$M-D achieve comparable resolutions of 8.9 and 8.8 bits, respectively. However, at 0.5 V, the ranking is reversed: $\Delta \Sigma$M-D achieves an ENOB of 10.1 bits. Since the power consumption of the latter architecture is largely insensitive to $V_{DD}$ due to the current-reference biasing, its overall efficiency benefits significantly from the increased headroom. At 0.5 V, the resolution of both proposed designs is superior to other first-order implementations [22,27,30,46].

While our designs utilize a minimalist first-order loop, they approach the resolution of more complex second-order designs [47,48,49] that operate at higher supply voltages. Notably, the second-order design in [50] achieves over 10-bit resolution at 0.4 V; however, unlike our proposed current-input solution, it requires differential voltage-type inputs. Nevertheless, the duty-cycled resistor technique proposed in [50] suggests a potential path for further investigation into higher-order current-mode modulators. Recently, Seol et al. [51] reported a 136.6 dB DR current-input CT-$\Delta \Sigma$M consuming 64.1 $\mathsf{\mu }\mathrm{W}$, achieving a Schreier FOM of 174.3 dB, which highlights the potential of current-mode $\Delta \Sigma$ conversion for high-resolution applications at a higher power budget.

The energy efficiency of the proposed architectures is highlighted by two key figures of merit. The Walden FOM (${\mathrm{FOM}}_{\mathrm{W}}=\mathrm{Power}/(2^{\mathrm{ENOB}}\times 2\times \mathrm{BW})$, [52]) of the $\Delta \Sigma$M-D reaches 0.166 pJ/conv.-step at 0.5 V, making it highly competitive with all other benchmarked designs except for [31,50]. Similarly, the Schreier FOM (${\mathrm{FOM}}_{\mathrm{S}}$) for both $\Delta \Sigma$M-B and $\Delta \Sigma$M-D demonstrates high efficiency compared to other first-order modulators, while predictably lagging behind the more complex higher-order architectures in [13,31,47,48,49] that utilize aggressive noise-shaping.

Table 5. Performance comparison with state-of-the-art low-voltage and/or low-power continuous-time $\Delta \Sigma$ modulators. The Input Signal Type (^★) is indicated to be either current (I) or voltage (V). ^†: FOM_S calculated from SNDR_max.

Metric	This Work $\Delta \Sigma$M-B		This Work $\Delta \Sigma$M-D		[22]	[46]	[27]	[30]	[50]	[47]	[48]	[49]	[31]	[13]
Technology [nm]	180		180		2500	500	65	130	65	180	65	180	65	150
Supply Voltage [V]	0.4	0.5	0.4	0.5	5.0	3.3	1.2	1.2	0.4	1.8	1.5	1.2	0.7	1.5
Input Signal Type ★	I		I		I	V	V	V	V	V	V	V	V	V
$f_s$ [MHz]	0.0125		0.0125		0.0010	0.512	15	5.47	0.64	0.3	10.24	8	320	6.144
Bandwidth [kHz]	0.0061		0.0061		0.0005	0.5	58.59	21.36	10	0.25	20	0.2 × 16	2	6
Power [μW]	0.0081	0.0101	0.0022	0.0022	15	72.6	9.42	80	0.16	23	300	34.8	256	110
SNDRmax [dB]	55.2	57.4	55.0	62.5	71.0	55.0	51.1	51.34	56.4	78.0	82.0	75.9	69.1	92.4
Dynamic Range [dB]	61.5	65.3	61.4	65.2	–	58	–	–	63.1	90	91	86	76.2	94.4
Area [mm2]	0.094		0.094		6.44	9.0	0.0011	0.0024	0.035	0.088	0.07	0.34	0.013	0.016
Modulator order	1st		1st		1st	1st	1st	1st	2nd	2nd	2nd	2nd	3rd	3rd
ENOB [bits]	8.9	9.2	8.8	10.1	11.5	8.8	8.2	8.23	10.2	12.7	13.3	12.3	11.2	15.0
FOMW [pJ/conv.-step]	1.392	1.410	0.399	0.166	5279	158.0	0.27	6.25	0.015	7.11	0.73	1.07	0.027	0.271
FOMS [dB]	150.3	153.1	155.9	159.6	116.2 †	126.4	149.0 †	135.6 †	171.1	160.4	160.2	165.6	175.1	171.8

Table 5. Performance comparison with state-of-the-art low-voltage and/or low-power continuous-time $\Delta \Sigma$ modulators. The Input Signal Type (^★) is indicated to be either current (I) or voltage (V). ^†: FOM_S calculated from SNDR_max.

Metric	This Work $\Delta \Sigma$M-B		This Work $\Delta \Sigma$M-D		[22]	[46]	[27]	[30]	[50]	[47]	[48]	[49]	[31]	[13]
Technology [nm]	180		180		2500	500	65	130	65	180	65	180	65	150
Supply Voltage [V]	0.4	0.5	0.4	0.5	5.0	3.3	1.2	1.2	0.4	1.8	1.5	1.2	0.7	1.5
Input Signal Type ★	I		I		I	V	V	V	V	V	V	V	V	V
$f_s$ [MHz]	0.0125		0.0125		0.0010	0.512	15	5.47	0.64	0.3	10.24	8	320	6.144
Bandwidth [kHz]	0.0061		0.0061		0.0005	0.5	58.59	21.36	10	0.25	20	0.2 × 16	2	6
Power [μW]	0.0081	0.0101	0.0022	0.0022	15	72.6	9.42	80	0.16	23	300	34.8	256	110
SNDRmax [dB]	55.2	57.4	55.0	62.5	71.0	55.0	51.1	51.34	56.4	78.0	82.0	75.9	69.1	92.4
Dynamic Range [dB]	61.5	65.3	61.4	65.2	–	58	–	–	63.1	90	91	86	76.2	94.4
Area [mm2]	0.094		0.094		6.44	9.0	0.0011	0.0024	0.035	0.088	0.07	0.34	0.013	0.016
Modulator order	1st		1st		1st	1st	1st	1st	2nd	2nd	2nd	2nd	3rd	3rd
ENOB [bits]	8.9	9.2	8.8	10.1	11.5	8.8	8.2	8.23	10.2	12.7	13.3	12.3	11.2	15.0
FOMW [pJ/conv.-step]	1.392	1.410	0.399	0.166	5279	158.0	0.27	6.25	0.015	7.11	0.73	1.07	0.027	0.271
FOMS [dB]	150.3	153.1	155.9	159.6	116.2 †	126.4	149.0 †	135.6 †	171.1	160.4	160.2	165.6	175.1	171.8

3.6. Broader Implications and Limitations

While this study demonstrates the feasibility of 10-bit resolution at 0.5 V, several limitations remain. The current-mode approach is inherently sensitive to the sensor’s output impedance; if this impedance is comparable to the feedback DAC’s $R_{FB,\mathrm{eff}}$, additional non-linearities may arise and a specialized input current buffer would be necessary [53].

Furthermore, while Architecture D provides high robustness, its area is dominated by the large current-reference integration capacitor. Future research into capacitor-multiplier techniques or higher-order loops utilizing ULV-compatible inverter-based amplifiers could further improve the resolution-to-area ratio.

As is characteristic of subthreshold circuits, the performance is sensitive to temperature-induced leakage. This work assumes a controlled operating environment consistent with wearable biomedical sensors (approx. 20–40 °C); operation at high industrial temperatures would likely require additional leakage-compensation or calibration techniques.

4. Conclusions

This work has addressed the need for ultra-low-voltage (ULV) and ultra-low-power analog front-ends for next-generation low-frequency biomedical and biochemical sensors. We presented a comprehensive comparative analysis of four minimalist, first-order, current-mode continuous-time Delta-Sigma modulator (CT-$\Delta \Sigma$M) architectures, each optimized for direct interfacing with current-output transducers at supply voltages below 0.5 V.

This study confirms that first-order CT-$\Delta \Sigma$ modulation based on passive integration is a highly viable strategy for deep near-threshold operation. All four proposed architectures, implemented in a standard 180 nm CMOS technology, achieve stable noise-shaping while consuming power in the nanowatt range, validating their suitability for systems with nanowatt power budgets. Among them, the bootstrapped current-reference DAC (BS-CR-DAC) architecture delivered the most promising performance, achieving a peak 10.1-bit ENOB at 0.5 V. At the extreme 0.4 V supply, both the SC-DAC and BS-CR-DAC architectures demonstrate comparable resolutions (∼9-bit ENOB), with the latter offering superior resilience to process variations.

Through the systematic comparison of these four topologies, this work establishes the fundamental limits of current-mode CT-$\Delta \Sigma$Ms in the ULV regime. The proposed design guidelines (Section 3.4) provide analytical boundaries for selecting integration capacitance and sampling frequency, ensuring that future designs can effectively balance area constraints against leakage-induced distortion. Architecture D (BS-CR-DAC) emerges as the most robust solution, successfully decoupling feedback linearity from supply-limited headroom.

These results advance the current state of the art in the performance–complexity trade-off inherent to ULV design. The proposed current-mode minimalist architectures achieve competitive resolution and energy efficiency primarily through passive integration and precise charge-domain/current feedback. This approach sidesteps the design overhead—such as excess-loop-delay compensation, multi-bit quantization, or FIR filtering—typically required to stabilize high-performance voltage-mode modulators at low voltages. Finally, further research is required to assess whether higher absolute resolutions can be achieved under the inherent constraints of subthreshold operation.