Search Results (91)

To satisfy the superior surface quality requirements in the fabrication of HBM (High-Bandwidth Memory) and 3D NAND Flash Memory, high-efficiency Si chemical mechanical planarization (CMP) is essential. In this study, a colloidal silica abrasive-based Si-wafer CMP slurry was developed to simultaneously achieve a high polishing rate (≥10 nm/min) and low surface roughness (≤0.2 nm) without inducing CMP-induced scratches. The proposed Si-wafer CMP slurry incorporates two functional components: triammonium phosphate (TAP) as a hydrolysis reaction accelerator and hydroxyethyl cellulose (HEC) as an abrasive drag force accelerator. The polishing rate enhancement mechanism of TAP was analyzed by monitoring the OH⁻ mol concentration, surface adsorption behavior, and XPS spectra. The results showed that increasing the TAP concentration raised the OH⁻ mol concentration and converted Si–Si and Si–O–Si bonds to Si–OH via a hydrolysis reaction, thereby increasing the polishing rate. However, excessive hydrolysis also led to increased surface roughness. On the other hand, HEC influenced slurry viscosity, abrasive dispersibility, and drag force. At low HEC concentrations, increased abrasive drag force improved the polishing rate. At high concentrations, however, HEC formed a hindrance layer on the Si surface via hydrogen bonding and condensation reactions, reducing the effective contact area of abrasives and thus decreasing the polishing rate. By optimizing the concentrations of TAP (0.0037 wt%) and HEC (≤0.0024 wt%), the proposed slurry formulation achieved high-performance Si-wafer CMP, satisfying both surface roughness and polishing rate targets required for advanced memory packaging applications. Full article

Silicon carbide (SiC) is widely utilized in semiconductors, microelectronics, optoelectronics, and other advanced technologies. However, its inherent characteristics, such as its hardness, brittleness, and high chemical stability, limit the processing efficiency and application of SiC wafers. This study explores the use of plasma etching as a pre-treatment step before chemical mechanical polishing (CMP) to enhance the material removal rate and improve CMP efficiency. Experiments were designed based on the Taguchi method to investigate the etching rate of plasma under various processing parameters, including applied power, nozzle-to-substrate distance, and etching time. The experimental results indicate that the etching rate is directly proportional to the applied power and increases with nozzle-to-substrate distance within 3–5 mm, while it is independent of etching time. A maximum etching rate of 5.99 μm/min is achieved under optimal conditions. And the etching mechanism and microstructural changes in SiC during plasma etching were analyzed using X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), white light interferometry, and ultra-depth-of-field microscopy. XPS confirmed the formation of a softened SiO₂ layer, which reduces hardness and enhances CMP efficiency; SEM revealed that etching pits form in relation to distance; and white light interferometry demonstrated that etching causes a smooth surface to become rough. Additionally, surface defects resulting from the etching process were analyzed to reveal the underlying reaction mechanism. Full article

To address the issue of surface glazing that occurs during prolonged polishing with gel tools, this study employs a triethanolamine (TEA)-based polishing fluid system to enhance the self-sharpening capability of the gel polishing disc. The inhibitory mechanism of TEA concentration on disc glazing is systematically analyzed, along with its impact on the gel disc’s frictional wear behaviour. Furthermore, the synergistic effects of process parameters on both surface quality and material removal rate (MRR) of SiC are examined. The results demonstrate that TEA concentration is a critical factor in regulating polishing performance. At an optimal concentration of 4 wt%, an ideal balance between chemical chelation and mechanical wear is achieved, effectively preventing glazing while avoiding excessive tool wear, thereby ensuring sustained self-sharpening capability and process stability. Through orthogonal experiment optimization, the best parameter combination for SiC polishing is determined: 4 wt% TEA concentration, 98 N polishing pressure, and 90 rpm rotational speed. This configuration delivers both superior surface quality and desirable MRR. Experimental data confirm that TEA significantly enhances the self-sharpening performance of gel discs through its unique complex reaction. During the rough polishing stage, the MRR increases by 34.9% to 0.85 μm/h, while the surface roughness S_a is reduced by 51.3% to 6.29 nm. After subsequent CMP fine polishing, an ultra-smooth surface with a final roughness of 2.33 nm is achieved. Full article

High-Bandwidth Memory (HBM) enables the bandwidth required by modern AI and high-performance computing, yet its three dimensional stack traps heat and amplifies thermo mechanical stress. We first review how conventional solutions such as heat spreaders, microchannels, high density Through-Silicon Vias (TSVs), and Mass Reflow Molded Underfill (MR MUF) underfills lower but do not eliminate the internal thermal resistance that rises sharply beyond 12layer stacks. We then synthesize recent hybrid bonding studies, showing that an optimized Cu pad density, interface characteristic, and mechanical treatments can cut junction-to-junction thermal resistance by between 22.8% and 47%, raise vertical thermal conductivity by up to three times, and shrink the stack height by more than 15%. A meta-analysis identifies design thresholds such as at least 20% Cu coverage that balances heat flow, interfacial stress, and reliability. The review next traces the chain from Coefficient of Thermal Expansion (CTE) mismatch to Cu protrusion, delamination, and warpage and classifies mitigation strategies into (i) material selection including SiCN dielectrics, nano twinned Cu, and polymer composites, (ii) process technologies such as sub-200 °C plasma-activated bonding and Chemical Mechanical Polishing (CMP) anneal co-optimization, and (iii) the structural design, including staggered stack and filleted corners. Integrating these levers suppresses stress hotspots and extends fatigue life in more than 16layer stacks. Finally, we outline a research roadmap combining a multiscale simulation with high layer prototyping to co-optimize thermal, mechanical, and electrical metrics for next-generation 20-layer HBM. Full article

In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer formation, and double-sided Cu electroplating. This method enhances the TSV stability by eliminating Cu contamination issues during chemical–mechanical polishing (CMP), which are a common challenge in traditional blind via fabrication processes. Additionally, the liner and barrier layer/seed layer achieve a high step coverage exceeding 80%, ensuring excellent conformality and structural integrity. For electroplating, a multi-stage bi-directional electroplating technique is introduced to enable void-free Cu filling in TSVs. The fabricated TSVs exhibit an ultra-low leakage current of 135 fA at 20 V, demonstrating their potential for advancing 3D integration technologies in heterogeneous integration. Full article

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs. Full article

The wastewater from Chemical Mechanical Polishing (CMP) generated in the semiconductor industry contains a significant concentration of suspended particles and necessitates rigorous treatment to meet environmental standards. Ceramic ultrafiltration membranes offer significant advantages in treating such high-solid wastewater, including a high separation efficiency, environmental friendliness, and straightforward cleaning and maintenance. However, the preparation of high-precision ceramic ultrafiltration membranes with a smaller pore size (usually <20 nm) is very complicated, requiring the repeated construction of transition layers, which not only increases the time and economic costs of manufacturing but also leads to an elevated transport resistance. In this work, halloysite nanotubes (HNTs), characterized by their high aspect ratio and lumen structure, were utilized to create a high-porosity transition layer using a spray-coating technique, onto which a γ-Al₂O₃ ultrafiltration selective layer was subsequently coated. Compared to the conventional α-Al₂O₃ transition multilayers, the HNTs-derived transition layer not only had an improved porosity but also had a reduced pore size. As such, this strategy tended to simplify the preparation process for the ceramic membranes while reducing the transport resistance. The resulting high-flux γ-Al₂O₃ ultrafiltration membranes were used for the high-efficiency treatment of CMP wastewater, and the fouling behaviors were investigated. As expected, the HNTs-mediated γ-Al₂O₃ ultrafiltration membranes exhibited excellent water flux (126 LMH) and high rejection (99.4%) of inorganic particles in different solvent systems. In addition, such membranes demonstrated good operation stability and regeneration performance, showing promise for their application in the high-efficiency treatment of CMP wastewater in the semiconductor industry. Full article

The atomic level polishing of a material surface affects the accuracy of devices and the application of materials. Silica slurries play an important role in chemical mechanical polishing (CMP) by polishing the material surface. In this study, an efficient and controllable Stöber approach was developed to synthesize uniform monodisperse silica spheres with different cationic surfactants. The obtained silica spheres exhibited a regular shape with a particle size of 50–150 nm and were distributed evenly and narrowly. The highest surface specific area of the silica spheres was approximately 1155.9 m²/g, which was conducive to the polish process. The monodisperse SiO₂ spheres were applied as abrasives in chemical mechanical polishing. The surface micrographs of silicon wafers during the CMP process were studied using atomic force microscopy (AFM). The results demonstrated that the surface roughness Ra values reduced from 1.07 nm to 0.979 nm and from 1.05 nm to 0.933 nm when using a CTAB-SiO₂ microsphere as an abrasive. These results demonstrate the advantages of monodisperse SiO₂ spheres as abrasive materials in chemical mechanical planarization processes. Full article

This study establishes a bidirectional kinematic analysis framework for single-sided chemical mechanical polishing systems through innovative coordinate transformation synergies (rotational and translational). To address three critical gaps in existing research, interaction dynamics for both pad–wafer and abrasive–wafer interfaces are systematically derived via 5-inch silicon wafers. Key advancements include (1) the development of closed-form trajectory equations for resolving multibody tribological interactions, (2) vector-based relative velocity quantification with 17 × 17 grid 3D visualization, and (3) first-principle parametric mapping of velocity nonuniformity (NUV = 0–0.42) across 0–80 rpm operational regimes. Numerical simulations reveal two fundamental regimes: near-unity rotational speed ratios (ω_P/ω_C = [0.95, 1) and (1, 1.05]) generate optimal spiral trajectories that achieve 95% surface coverage, whereas integer multiples produce stable relative velocities (1.75 m/s at 60 rpm). Experimental validation demonstrated 0.3 μm/min removal rates with <1 μm nonuniformity under optimized conditions, which was attributable to velocity stabilization effects. The methodology exhibits inherent extensibility to high-speed operations (>80 rpm) and alternative polishing configurations through coordinate transformation adaptability. This work provides a systematic derivation protocol for abrasive trajectory analysis, a visualization paradigm for velocity optimization, and quantitative guidelines for precision process control—advancing beyond current empirical approaches in surface finishing technology. Full article

This study optimized the proportions of synergistic catalysts to efficiently activate potassium peroxymonosulfate (Oxone), generate more reactive oxygen species, and accelerate the chemical oxidation of silicon carbide (4H-SiC) wafers during chemical–mechanical polishing (CMP) for an improved material removal rate (MRR) and surface quality. The Oxone was activated using ultraviolet (UV) catalysis with a photocatalyst (TiO₂) and transition metal (Fe₃O₄) to enhance the oxidation capacity of the polishing slurry through the production of strong oxidizing sulfate radicals (${\mathrm{S}\mathrm{O}}_4^{·-}$). First, the effects of the TiO₂, Fe₃O₄, and Oxone concentrations on the MRR were studied by conducting multiple single-factor experiments. Next, 4H-SiC wafers were polished using different catalyst combinations to verify the synergistic activation of Oxone by multiple catalysts. Finally, the roughnesses, physical features, and elemental compositions of the wafer surfaces were observed before and after polishing. The results showed that CMP with a TiO₂ concentration of 0.15 wt%, Fe₃O₄ concentration of 0.75 wt%, and Oxone concentration of 48 mM decreased the wafer surface roughness from Sa 134 to 8.251 nm and achieved a maximum MRR of 2360 nm/h, which is significantly higher than that associated with traditional CMP methods. The surface of a 4H-SiC wafer polished using CMP with the optimal catalytic system was extremely smooth with no scratches and exhibited many oxides that reduced its hardness. In summary, the proposed UV-TiO₂-Fe₃O₄-Oxone composite catalytic system for 4H-SiC CMP exhibited significant synergistic enhancements and demonstrated excellent surface quality, indicating considerable potential for the polishing of hard materials. Full article

The third-generation semiconductor single-crystal silicon carbide (SiC), as a typical difficult-to-machine material, improves the chemical reaction rate on the SiC surface during the polishing process, which is key to realizing efficient chemical mechanical polishing (CMP). In this paper, a new core-shell structure Fe₃O₄@MIL-100(Fe) magnetic catalyst was successfully synthesized, which can effectively improve the reaction rate during the SiC polishing procesSs. The catalyst was characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), and X-ray photoelectron spectroscopy (XPS), and was used as a heterogeneous photocatalyst for chemical mechanical polishing, and the polishing results of SiC were optimized using response surface methodology (RSM). The experimental results show that the surface roughness of SiC can reach the minimum value of 0.78 nm when the polishing pressure is 0.06 MPa, the polishing speed is 60 rpm, and the polishing flow rate is 12 mL/min. The results of the study provide theoretical support for the visible photocatalysis-assisted CMP of SiC. Full article

Chemical mechanical polishing (CMP) is a widely used technique in semiconductor manufacturing to achieve a flat and smooth surface on silicon wafers. A key challenge in CMP is enhancing the material removal rate (MRR) while reducing within-wafer non-uniformity (WIWNU). A computational fluid dynamics (CFD) model is employed to analyze the slurry flow between the wafer and the polishing pad. Several factors influence the CMP process, including the type of abrasives, slurry flow rate, pad patterns, and contact pressure distribution. In this study, two polishing pad patterns with concentric and radial grooves are proposed to address how morphology variations influence wafer removal rate and consistency. Under the same operating conditions, the CFD simulations show that (i) the radial grooves have higher wall shear stress, a more significant negative pressure region, and a more evenly distributed mass on the wafer surface than the concentric grooves, and (ii) the radial grooves exhibit superior slurry mass distribution. It is noted that reducing the negative pressure differential field area results in a less pronounced back-mixing effect. A comparison of radial and concentric polishing pad grooves reveals that radial grooves improve slurry distribution, reduce the slurry saturation time (SST), and increase wall shear stress, leading to higher MRR and improved non-uniformity (NU). Precisely, the errors between the experimental SST values of 21.52 s and 16.06 s for concentric circular and radial groove pads, respectively, and the simulated SST values of 22.23 s and 15.73 s are minimal, at 3.33% and 3.35%. Full article

The rapid advancement of 3D packaging technology has emerged as a key solution to overcome the scaling-down limitation of advanced memory and logic devices. Redistribution layer (RDL) fabrication, a critical process in 3D packaging, requires the use of polyimide (PI) films with thicknesses in the micrometer range. However, these polyimide films present surface topography variations in the range of hundreds of nanometers, necessitating chemical–mechanical planarization (CMP) to achieve nanometer-level surface flatness. Polyimide films, composed of copolymers of pyromellitimide and diphenyl ether, possess strong covalent bonds such as C–C, C–O, C=O, and C–N, leading to inherently low polishing rates during CMP. To address this challenge, the introduction of Fe(NO₃)₃ into CMP slurries has been proposed as a polishing rate accelerator. During CMP, this Fe(NO₃)₃ deformed the surface of a polyimide film into strongly positively charged 1,2,4,5-benzenetetracarbonyliron and weakly negatively charged 4,4′-oxydianiline (ODA). The chemically dominant polishing rate enhanced with the concentration of the Fe(NO₃)₃ due to accelerated surface interactions. However, higher Fe(NO₃)₃ concentrations reduce the attractive electrostatic force between the positively charged wet ceria abrasives and the negatively charged deformed surface of the polyimide film, thereby decreasing the mechanically dominant polishing rate. A comprehensive investigation of the chemical and mechanical polishing rate dynamics revealed that the optimal Fe(NO₃)₃ concentration to achieve the maximum polyimide film removal rate was 0.05 wt%. Full article

Cavity silicon on insulator (Cavity-SOI) offers significant design flexibility for microelectromechanical systems (MEMS). Notably, the shape and depth of the cavity can be tailored to specific requirements, facilitating the realization of intricate multi-layer structural designs. The novelty of the proposed fabrication methodology is manifested in its employment of a micromachining process flow, which integrates dry etching, wafer level Au–Si eutectic bonding, and chemical mechanical polishing (CMP) to create Cavity-SOI. This innovative approach substantially mitigates the complexity of fabrication, and the implementation of wafer-level gold–silicon eutectic bonding and vacuum packaging can be achieved, representing a distinct advantage over conventional methods. To evaluate the technical viability, a MEMS resonant pressure sensor (RPS) was designed. Experimental findings demonstrate that during the formation of Cavity-SOI, dry etching can accurately fabricate cavities of predefined dimensions, wafer-level Au–Si eutectic bonding can achieve efficient sealing, and CMP can precisely regulate the depth of cavities, thus validating the feasibility of the Cavity-SOI formation process. Additionally, when implementing Cavity-SOI in the fabrication of MEMS RPS, it enables the spontaneous release of resonators, effectively circumventing the undercut and adhesion issues commonly encountered with hydrofluoric acid (HF) release. The sensors fabricated using Cavity-SOI exhibit a sensitivity of 100.695 Hz/kPa, a working temperature range spanning from −10–60 °C, a pressure range of 1–120 kPa, and a maximum error of less than 0.012% full scale (FS). The developed micromachining process for Cavity-SOI not only streamlines the fabrication process but also addresses several challenges inherent in traditional MEMS fabrication. The successful fabrication and performance validation of the MEMS RPS confirm the effectiveness and practicality of the proposed method. This breakthrough paves the way for the development of high-performance MEMS devices, opening up new possibilities for various applications in different industries. Full article

The chemical–mechanical polishing (CMP) of silicon wafers involves high-precision surface machining after double-sided lapping. Silicon wafers are subjected to chemical corrosion and mechanical removal under pressurized conditions. The multichip CMP process for 4~6-inch silicon wafers, such as those in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), and MEMS (Micro-Electromechanical System) field materials, is conducted to maintain multiple chips to improve efficiency and improve polish removal uniformity; that is, the detected TTV (total thickness variation) gradually increases from 10 μm to less than 3 μm. In this work, first, a mathematical model for calculating the small deflection of silicon wafers under pressure is established, and the limit values under two boundary conditions of fixed support and simple support are calculated. Moreover, the removal uniformity of the silicon wafers is improved by improving the uniformity of the wax-coated adhesion state and adjusting the boundary conditions to reflect a fixed support state. Then, the stress distribution of the silicon wafers under pressure is simulated, and the calculation methods for measuring the TTV of the silicon wafers and the uniformity measurement index are described. Stress distribution is changed by changing the size of the pressure ring to achieve the purpose of removing uniformity. This study provides a reference for improving the removal uniformity of multichip silicon wafer chemical–mechanical polishing. Full article