Search Results (37)

The performance of single-photon avalanche diodes (SPADs) is highly dependent on the operating temperature, while traditional SPAD models neglect the self-heating effect induced by avalanche current during long-term device operation, leading to insufficient prediction accuracy. This paper proposes an electro-thermal coupled SPAD simulation model that self-consistently integrates the transient thermal effects of the avalanche process with temperature-dependent electrical parameters, including junction capacitance, breakdown voltage, impact ionization coefficients, and Shockley–Read–Hall (SRH) recombination rates. The complete electro-thermal coupled model is constructed based on Sentaurus-TCAD thermal simulation and Virtuoso circuit simulation and implemented via the Verilog-A language. Simulation results demonstrate that after the device operates for 100 μs under repeated avalanche-quenching processes, the self-heating effect causes a 0.34 V shift in breakdown voltage, increases the device dead time by 3.34 ps, and simultaneously reduces the photon detection probability and elevates the dark count rate. This study conducts a systematic investigation into the performance degradation mechanism of SPAD devices induced by the self-heating effect, laying a theoretical foundation at the device self-heating level for subsequent research on the electrothermal interaction between quenching circuits and device bodies. Full article

We present an analytic compact model for p-type cylindrical gate-all-around (GAA) MOSFETs in the quasi-ballistic/ballistic regime, incorporating drain-induced barrier lowering (DIBL). To describe the potential profile, an undetermined parameter is used to represent the channel potential, which is derived from the Laplace equation in the subthreshold region and from Gauss’s law combined with quantum statistics in the inversion region. A smoothing function is applied to this parameter to ensure a continuous source—drain current across all operating regions. The current model is based on the Landauer approach and captures both quasi-ballistic/ballistic transport and quantum-confinement effects. It is validated against non-equilibrium Green’s function (NEGF) simulation results and implemented in Verilog-A for SPICE circuit-level simulation of a CMOS inverter, demonstrating its applicability for nanoscale design. Full article

Associative learning is a fundamental neural mechanism in human memory and cognition. It has attracted considerable attention in neuromorphic system design owing to its multimodal integration, fault tolerance, and energy efficiency. However, prior studies mostly focused on single inputs, with limited attention to multibit pairs or recall under non-orthogonal input patterns. To address these issues, this study proposes a bidirectional associative learning system using paired multibit inputs. It employs a synapse–neuron structure based on spiking neural networks (SNNs) that emulate biological learning, with simple circuits supporting synaptic operations and pattern evaluation. Importantly, the update and read functions were designed by drawing inspiration from the operational characteristics of emerging synaptic devices, thereby ensuring future compatibility with device-level implementations. The proposed system was verified through Cadence-based simulations using CMOS neurons and Verilog-A synapses. The results show that all patterns are reliably recalled under intact synaptic conditions, and most patterns are still robustly recalled under biologically plausible conditions such as partial synapse loss or noisy initial synaptic weight states. Moreover, by avoiding massive data converters and relying only on basic digital gates, the proposed design achieves associative learning with a simple structure. This provides an advantage for future extension to large-scale arrays. Full article

In this paper, a novel Tunneling-Drift-Diffusion Field-Effect Transistor (TDDFET) based on the combination of the quantum tunneling and conventional drift-diffusion mechanisms is proposed for the design of ternary logic circuits. The working principle of the TDDFET is analyzed in detail. Then, the device is packaged as a “black box” based on the table lookup method and further embedded into the HSPICE platform using the Verilog-A language. The basic unit circuits, such as the Standard Ternary Inverter (STI), Negative Ternary Inverter (NTI), Positive Ternary Inverter (PTI), Ternary NAND gate (T-NAND), and Ternary NOR gate (T-NOR), are designed. In addition, based on the designed unit circuits, the combinational logic circuits, such as the Ternary Encoder (T-Encoder), Ternary Decoder (T-Decoder), and Ternary Half Adder (T-HA), and the sequential logic circuits, such as the Ternary D-Latch and edge-triggered Ternary D Flip-Flop (T-DFF), are built, which has important significance for the subsequent investigation of ternary logic circuits. Full article

The timing jitter of a single-photon avalanche diode (SPAD) plays a critical role in the design and optimization of front-end circuits. This paper proposes a simplified timing jitter model based on Verilog-A. This model uses random numbers to determine the locations of photon absorptions and carrier avalanches based on absorption and avalanche probabilities, thereby achieving a calculation of the response time. By introducing photon detection probability, the model has corrected the response time obtained under ideal assumptions and achieved compatibility with excess bias voltage effects, which can describe the Gaussian peak of the timing jitter concisely and effectively. The simulation results are in good agreement with the measurement results, demonstrating the advantages of this model in terms of accuracy, flexibility, and adaptability. The model provides support for the collaborative optimization of the design of SPAD devices and circuits. Full article

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures. Full article

This paper presents a novel Verilog-A model for the Fermi velocity in Graphene Field-Effect Transistors (GFETs). The Fermi velocity is an important parameter associated with the energy spectrum of the delocalized bonds in graphene which impact the performance of a GFET. Unlike existing GFET models where the Fermi velocity is assumed to have a constant value, the proposed model considers carrier concentrations in the channel and gate dielectrics to create a closed-form solution for the Fermi velocity, a parameter previously demonstrated to vary based on these two factors. The proposed mathematical model is then adapted to Verilog-A for interfacing with computer-aided design (CAD) circuit simulators. To demonstrate the accuracy of the proposed model, the simulation results are compared to measured drain–source currents obtained from various GFET devices (including GFETs measured by authors). The measured results show good agreement with the values predicted using the proposed model (<±1%), demonstrating the superior accuracy of the model compared to other published Verilog-A-based models, especially around the Dirac point. Full article

In this paper, we present a framework of modeling memristor noise for circuit simulators using physics-informed neural networks (PINNs). The variability of the memristor that is directly related to the neuromorphic system can be handled with this approach. The memristor noise model is transformed into a Fokker–Planck equation (FPE) from a probabilistic perspective. The translated equations are physically interpreted through the PINN. The weights and biases extracted from the PINN are implemented in Verilog-A through simple operations. The characteristics of the stochastic system under the noise are obtained by integrating the probability density function. This approach allows for the unification of different memristor models and the analysis of the effects of noise. Full article

The use of Moore’s law appears to be coming to an end due to technological and physical constraints, as complementary metal-oxide semiconductor (CMOS) transistors become smaller and closer to the atomic scale. Therefore, various emerging technologies are being researched as potential successors to traditional CMOS transistors, and one of the most exciting candidates is the magnetoelectric spin-orbit (MESO) device. The MESO device comprises two portions (input and output) and it cascades charge/voltage as input and output signals. In the MESO device’s output portion, ferromagnetic (FM) and high-spin-orbit-coupling layers are employed to provide spin-polarized current and charge/voltage output. In this paper, we offer a description and analysis of the operating mechanism of the MESO device’s output portion using a spin flow approach and propose a double-FM-layer structure. In the double-FM-layer structure, we implement two FM layers with antiparallel magnetization directions, instead of using a single-FM-layer structure to increase the output charge/voltage. The proposed structure is verified through the Verilog-A compact model. Full article

In this article, we propose a circuit to imitate the behavior of a Reward-Modulated spike-timing-dependent plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness in the shared synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130 nm process. The article’s main goal is to provide the basic building blocks for deep neural networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity. Full article

Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths ($L_{ref}$), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model’s validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V. Full article

Memristor devices have diverse physical models depending on their structure. In addition, the physical properties of memristors are described using complex differential equations. Therefore, it is necessary to integrate the various models of memristor into an unified physics-based model. In this paper, we propose a physics-informed neural network (PINN)-based compact memristor model. PINNs can solve complex differential equations intuitively and with ease. This methodology is used to conduct memristor physical analysis. The weight and bias extracted from the PINN are implemented in a Verilog-A circuit simulator to predict memristor device characteristics. The accuracy of the proposed model is verified using two memristor devices. The results show that PINNs can be used to extensively integrate memristor device models. Full article

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (V_bg) and threshold voltage (V_th) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. Full article

In this paper, we propose a temperature sensor based on a 4H-SiC CMOS oscillator circuit and that is able to operate in the temperature range between 298 K and 573 K. The circuit is developed on Fraunhofer IISB’s 2 μm 4H-SiC CMOS technology and is designed for a bias voltage of 20 V and an oscillation frequency of 90 kHz at room temperature. The possibility to relate the absolute temperature with the oscillation frequency is due to the temperature dependency of the threshold voltage and of the channel mobility of the transistors. An analytical model of the frequency-temperature dependency has been developed and is used as a starting point for the design of the circuit. Once the circuit has been designed, numerical simulations are performed with the Verilog-A BSIM4SiC model, which has been opportunely tuned on Fraunhofer IISB’s 2 μm 4H-SiC CMOS technology, and their results showed almost linear frequency-temperature characteristics with a coefficient of determination that was higher than 0.9681 for all of the bias conditions, whose maximum is 0.9992 at a $V_{DD}$ = 12.5 V. Moreover, we considered the effects of the fabrication process through a Monte Carlo analysis, where we varied the threshold voltage and the channel mobility with different values of the Gaussian distribution variance. For example, at $V_{DD}$ = 20 V, a deviation of $17.4\%$ from the nominal characteristic is obtained for a Gaussian distribution variance of $20\%$. Finally, we applied the one-point calibration procedure, and temperature errors of +8.8 K and −5.8 K were observed at $V_{DD}$ = 15 V. Full article

Extracting behavioral models of RRAM devices is challenging due to their unique “memory” behaviors and rapid developments, for which well-established modeling frameworks and systematic parameter extraction processes are not available. In this work, we propose a physics-informed recurrent neural network (PiRNN) methodology to generate behavioral models of RRAM devices from practical measurement/simulation data. The proposed framework can faithfully capture the evolution of internal state and its impacts on the output. A series of modifications informed by the RRAM device physics are proposed to enhance the modeling capabilities. The integration strategy of Verilog-A equivalent circuits, is also developed for compatibility with existing general-purpose circuit simulators. The Verilog-A model can be easily adopted into the SPICE-type simulator for the circuit design with a variable step that differs from the training process. Numerical experiments with real RRAM devices data demonstrate the feasibility and advantages of the proposed methodology. Full article