An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation
Abstract
:1. Introduction
2. Simplified Timing Jitter Model
2.1. The Structure and Principle of SPAD
2.2. Modeling of Response Time
- Only the absorption region is capable of absorbing photons.
- The quantum efficiency of the absorption region is assumed to be 100%, meaning that each photon generates one electron–hole pair.
- Only the multiplication region can perform avalanche multiplication, and the probability of avalanche events occurring is 100%.
- The avalanche multiplication process is assumed to occur instantaneously within an extremely short period of time.
- Carriers are generated at a location in the absorption region and are injected into the multiplication region.
- Within the multiplication region, carriers are accelerated by the strong electric field, gradually gathering momentum until they trigger the first avalanche ionization at a location.
- Carriers continuously perform avalanche multiplication, generating a sufficiently large current and exiting the multiplication region under the influence of the built-in electric field.
2.2.1. Absorption Region Transit Time
2.2.2. Momentum Accumulation Time
2.2.3. Multiplication Region Transit Time
2.2.4. Response Time Correction
3. Verilog-A HDL Implementation
3.1. Jitter Module
3.2. SPAD Circuit Simulation Model
4. Simulation and Verification
4.1. Measurement Platform and Simulation Parameters
4.2. Results and Discussion
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Abbreviations
SPAD | Single-photon avalanche diode |
APD | Avalanche photo diode |
DCR | Dark count rate |
AP | After-pulse |
FWHM | Full width at half maximum |
PDP | Photon detection probability |
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Parameter | Symbol | Value |
---|---|---|
saturation current | A | |
built-in voltage | 0.8 V | |
breakdown voltage | or | 67 V |
breakdown current | or | A |
zero-bias junction capacitance | F | |
sidewall zero-bias junction capacitance | 0 F | |
absorption coefficient | /cm | |
electron mobility | cm2/(V·s) | |
hole mobility | cm2/(V·s) | |
saturation drift velocity | cm/s | |
absorption region width | cm | |
multiplication region width | cm | |
absorption region electric field | V/cm | |
multiplication region electric field | V/cm | |
25.2%@5 V, 20.7% @ 4 V, | ||
photon detection probability | PDP | 15.7%@3 V, 12.9% @ 2 V, |
10.1%@1 V, 9.4% @ 0.5 V |
Reference | Year | Method * | Error | Computational Consumption | Compatible with Circuit Simulators |
---|---|---|---|---|---|
[8] | 2020 | 3D-MC | <9.7% | ∼20 h (Intel x64 CPU + 32 GB RAM) | No |
[13] | 2022 | 1D Anal. + 3D Numer. | <23.5% | >20 min (32 CPUs) | No |
[14] | 2023 | Fourier series + 2D Anal. | <16.4% | N.A. | No |
[10] | 2024 | 1D-MC + 2D Numer. | <24.1% | N.A. | No |
This work | 2025 | 1D Anal. + 1D Numer. | <14.8% | <2 min (Intel i5 8400 + 16 GB RAM) | Yes |
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Xu, L.; Chang, Y.; Liu, L.; Qiao, K.; Xu, Z.; Wang, J.; Su, C.; Liu, T.; Yin, F.; Wang, X. An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation. Electronics 2025, 14, 1115. https://doi.org/10.3390/electronics14061115
Xu L, Chang Y, Liu L, Qiao K, Xu Z, Wang J, Su C, Liu T, Yin F, Wang X. An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation. Electronics. 2025; 14(6):1115. https://doi.org/10.3390/electronics14061115
Chicago/Turabian StyleXu, Linmeng, Yu Chang, Liyu Liu, Kai Qiao, Zefang Xu, Jieying Wang, Chang Su, Tianye Liu, Fei Yin, and Xing Wang. 2025. "An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation" Electronics 14, no. 6: 1115. https://doi.org/10.3390/electronics14061115
APA StyleXu, L., Chang, Y., Liu, L., Qiao, K., Xu, Z., Wang, J., Su, C., Liu, T., Yin, F., & Wang, X. (2025). An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation. Electronics, 14(6), 1115. https://doi.org/10.3390/electronics14061115