Search Results (115)

Press-pack insulated-gate bipolar transistor (IGBT) devices are key components of modular multilevel converter (MMC)-based HVDC systems, yet the parallel connection of tens of chips inside one sealed housing makes their internal aging difficult to monitor—existing methods cannot determine which chip or thermal interface has degraded without invasive sensing. This paper proposes a two-layer aging condition monitoring framework based solely on non-invasive external case temperature measurements, comprising an online detection layer and a detection layer. For the diagnosis layer, a coupled thermal network state-space model of the press-pack module is established; its observability matrix is shown to be of full rank, proving that aging at any internal location is detectable from external case temperatures, and a steady-state sensitivity analysis reduces the required measurement to the module-center case-temperature pair and yields a failure-signature rule that discriminates five aging modes. A 3D electrothermal finite-element model, validated against fiber Bragg grating (FBG) measurements on an MMC sub-module with deviations below 1.2 °C at all load levels, is then used to build an aging fingerprint database of 270 scenarios that maps a measured case-temperature distribution to the aging location, the affected component, and the severity of any cooling-system degradation. For the detection layer, a deep neural network (DNN) trained only on healthy-state data provides online early warnings through its prediction residual. Experiments on a 2.2 kV/2100 A MMC sub-module platform and a solid-state DC–DC transformer platform confirm that cooling-system degradation is reliably detected and that the detection layer transfers across converter types. Even in the least sensitive aging case, the predicted case-temperature signature (0.036 °C) exceeds the 0.01 °C resolution of standard thermocouple instrumentation, which indicates that genuine device aging would be resolvable as well. The framework provides a non-invasive online health-monitoring solution that can also locate the degraded element in high-power press-pack devices. Full article

The insulated gate bipolar transistor (IGBT) is widely applied in industrial fields such as rail transit, wind power generation, smart grids, and renewable energy. The temperature distribution, stress variation patterns, thermal performance, and modeling damage in the solder layer of IGBT modules under thermal and stress loadings have rarely been studied. This study first established a three-dimensional geometric model based on the actual dimensions of the IGBT module. A finite element model was successfully constructed for thermal/mechanical multi-physics coupled simulation based on the ANSYS Workbench platform to simulate the temperature, deformation trends, and stress distribution patterns of the solder layer in the IGBT module. Secondly, the solder layer defects of the IGBT module were categorized into five major types, and 37 sets of 3D models of IGBT with damaged solder layers were designed, followed by thermal/mechanical coupled simulation analysis for each. Finally, the influence of the void positions, sizes, and distribution types in the solder layer on the module temperature, heat dissipation path, and thermal stress was simulated during thermal cycling. The results showed that the highest stress at the edge of the solder layer is 6.2504 × 10⁷ Pa, the lowest junction temperature is 70.79 °C, and the average thermal stress is 1.2388 (m/m). The highest junction temperature reached 72.562 °C under central solder layer damage states as determined by a thermal/mechanical coupled simulation analysis of four different types of solder layer defects. This research provides a theoretical basis and reliable technical support for the anti-damage and failure of IGBT modules and high-power devices. Full article

High-power-density insulated gate bipolar transistor (IGBT) modules in new energy vehicles require efficient heat dissipation and good temperature uniformity. This study proposes a tri-objective topology optimization method for a liquid-cooled heat sink using average temperature, temperature variance, and flow dissipation as the objective functions. A two-dimensional model was established in COMSOL to investigate the effects of the fluid volume fraction, inlet pressure, and optimization-weight distribution on the optimized topology and thermo-hydraulic performance. The results show that a fluid volume fraction of 0.4 and an inlet pressure of 15 Pa provide the best overall performance. Compared with the bi-objective design, introducing temperature variance as a third objective reduces temperature variance by 50.23%, with only a 1.08% increase in average temperature. Three-dimensional simulations further verify the optimized design. Compared with a conventional pin-fin heat sink, the topology-optimized structure reduces the average temperature by 10.43% and the temperature variance by 44.37%, while increasing the flow dissipation by 49.57%. These results show that tri-objective topology optimization is an effective method for improving the thermal management of high-power-density IGBT modules. Full article

Direct Torque Control (DTC) for induction motors (IMs) is an advanced method derived from Field-Oriented Control (FOC). In DTC, a voltage source inverter (VSI) is employed to directly regulate the stator flux linkage and electromagnetic torque through space vector modulation (VSM), where the optimal switching vector is selected for the VSI. Similarly to FOC, the stator flux and electromagnetic torque are independently controlled to deliver enhanced dynamic performance. However, DTC still suffers from certain drawbacks, such as slow transient response, limited dynamic performance, and high ripples in torque and flux. In this paper, an improved DTC method is proposed for a three-phase squirrel-cage induction motor. Specifically, a Type-2 fuzzy logic controller is employed to regulate both the stator flux and electromagnetic torque (T2FLC). The proposed method (FLCDTC) combines a three-level VSI with dual-band hysteresis (DBHW) switching to generate the gating signals for the insulated gate bipolar transistors (IGBTs). This approach effectively reduces the total harmonic distortion (THD) in torque and stator current, lowers the common-mode voltage (CMV), and enhances the overall motor performance. Simulation results under random noise distribution demonstrate the robustness of the proposed controller, even at low operating speeds. Finally, the effectiveness of the algorithm is validated in real-time through hardware-in-the-loop (HIL) implementation. Full article

One of the main causes of failure in Insulated Gate Bipolar Transistor (IGBT) modules used in high-power conversion applications is thermal-stress-induced degradation. In this paper, an experimental testing setup for thermal stress and real-time degradation monitoring, as well as a deep neural network (DNN)-based lifetime prediction of IGBT modules under thermo-electrically stressed inverter operation, is proposed. A two-level SVPWM inverter is implemented to create a hybrid power cycling test platform that imposes well-defined junction-temperature swings representative of real-world operation by combining controlled electrical loading and active induction heating with water cooling. Throughout the aging process, on-state voltage and module temperature are constantly monitored to identify degradation precursors associated with thermo-mechanical fatigue. A physics-based Coffin–Manson lifetime model is fitted using failure datasets to characterize temperature-dependent lifetime behavior. An offline deep neural network (DNN) is trained on degradation trajectories derived from on-state collector–emitter voltage (V_ce,on) to predict remaining useful lifetime. This approach uses partial degradation histories for accurate early-life prediction. The proposed DNN model for competitive and computationally efficient lifetime prediction is validated experimentally on several IGBT modules under different thermal stresses, and its accuracy is compared with other prediction methods. Full article

Modular multilevel converters (MMCs) for high-voltage direct current (HVDC) transmission require substantial submodule (SM) capacitance to limit capacitor voltage ripple, resulting in bulky and costly converter valves. The integrated gate-commutated thyristor (IGCT), with its higher voltage rating and lower conduction loss compared to the insulated-gate bipolar transistor (IGBT), enables a significant reduction in the number of SMs per arm, offering a pathway toward compact converter design. This paper investigates how the reduced SM count of IGCT-based MMCs affects the feasibility and benefit of operating with elevated capacitor voltage ripple to further decrease SM capacitance. An analytical framework is developed to evaluate the modulation boundary under increased ripple, explicitly accounting for the voltage ripple coupling (CVR) effect and circulating-current suppression. A ripple-tolerance coefficient κ is introduced, and its optimal value is determined by identifying the inflection point beyond which the achievable AC voltage output begins to decline. For a ±500 kV/2000 MW IGCT-MMC case study using 6.5 kV devices with 250 SMs per arm, the proposed method reduces the per-unit energy storage requirement by up to 39.4% compared with conventional-ripple operation. Simulation and prototype experimental results on a 400 V, 3 kW, 4-SM/arm test bench validate the analytical predictions and confirm the practical feasibility of the approach. Full article

This article presents an online additive fault-detection system for the speed sensor of a 200 W shunt-type direct current (DC) motor, integrated into a power module controlled by an Insulated Gate Bipolar Transistor (IGBT). The system is designed to trigger an alarm signal when an additive fault occurs by comparing the Kalman Filter (KF) residual against a predefined detection threshold. Three specific fault types in the speed sensor were analyzed: offset, disconnection, and sinusoidal noise. Experimental results demonstrate effective fault detection across a speed range of 80 to 690 rpm under no-load conditions. However, when a constant torque of 0.5 Nm is applied, both the detection threshold and the subset of reliably identifiable faults must be adjusted. The main contribution of this study is the development of a customized real-time fault detection framework and the characterization of residual variations caused by unmodeled load disturbances in actual hardware. This approach improves the monitoring and fault-diagnosis capabilities of sensor systems in DC motors by quantifying the stochastic behavior of residuals under different operating constraints. Full article

Insulated-gate bipolar transistor (IGBT) power modules suffer efficiency degradation at elevated operating junction temperatures. The thermal sensitivity of the collector–emitter saturation voltage (V_CEsat) induces thermal stress imbalance, constraining system efficiency and reliability. A multi-resistor cascade network model for carrier-storage trench-gate IGBTs (CS-IGBTs) is established. The simulation results agree with the measurements within 10% error. The model decomposes the temperature coefficient contributions of individual structural regions. Analysis reveals that the drift region resistance dominates the V_CEsat temperature coefficient. Based on this finding, a co-doping strategy is proposed through simultaneously increasing the doping concentration in the carrier-storage layer and P⁺ collector. This approach reduces the temperature sensitivity of carrier mobility in the drift region, thereby optimizing V_CEsat’s temperature sensitivity. For the fabricated 1200 V/40 A CS-IGBT, the V_CEsat temperature coefficient decreases from 2.38 mV/K to 1.76 mV/K over 300 K to 450 K, which represents a 25.4% reduction. The total switching loss at 450 K decreases from 9.32 mJ to 8.70 mJ, achieving a 6.7% improvement. This device-level optimization suppresses V_CEsat’s temperature sensitivity and switching losses, enhancing efficiency in high-temperature power module applications. Full article

The high-frequency switching noise of insulated-gate bipolar transistors (IGBTs) limits the sensitivity of online partial discharge (PD) monitoring in ultra-high-voltage flexible DC (VSC-HVDC) transmission systems. To address this challenge, this study investigates the underlying mechanisms and evolution of this interference and develops an anti-interference signal separation method. Simulation and experimental results indicate that the energy of IGBT switching noise is concentrated in the 30–180 MHz range, which significantly overlaps with the ultra-high-frequency (UHF) band used for PD detection. This research further reveals the pronounced modulation effect of device aging on the interference spectrum: bond wire aging triggers “spectral reconstruction” via altered parasitic parameters, where severe collector aging leads to an abnormal surge in turn-off interference amplitude. In contrast, gate oxide layer degradation manifests as characteristic “global spectrum attenuation” and a shift in peak frequency toward lower bands. Confronted with the challenges of strong interference and spectrum drift induced by aging, this paper proposes an adaptive signal separation method based on feature optimization of the time–frequency cumulative energy function. This method constructs novel characteristic parameters—namely, oblique intercept width and morphological gradient steepness—to effectively capture the fundamental differences in the energy accumulation process of the signals. Experimental verification demonstrates that even under conditions of varying interference characteristics, the proposed method achieves high-precision separation of PD signals from IGBT noise, outperforming traditional equivalent time–frequency and wavelet principal component analysis methods. This research provides crucial theoretical and technical support for insulation condition monitoring and device aging diagnosis in VSC-HVDC converter valves. Full article

This paper presents an open-architecture mechatronic drive platform for operating a three-phase BLDC servomotor in an industrial robotic axis. A sequential and iterative mechatronic design methodology is adopted, integrating electronic design, digital control, mechanical development, and experimental prototyping, with emphasis on open-loop operation. The electronic circuit was designed using schematics and a PCB and validated in Proteus Design Suite 8.15 (Labcenter Electronics Ltd., London, UK) to verify switching sequences and inverter behavior. The power stage is based on a six-switch insulated-gate bipolar transistor (IGBT) inverter module, complemented by an independent snubber protection board and a dedicated digital gate-drive control board. The mechanical enclosure was designed using computer-aided design (CAD), CAD software tools (Shapr3D, version 5.911.0 (9224), Shapr3D Zrt., Budapest, Hungary), and fabricated via 3D printing. Switching behavior was simulated in Octave using parameters from a real industrial BLDC servomotor (Yaskawa SGMAH series) extracted from a Motoman robotic axis. The contribution is design-oriented in a mechatronic engineering sense, emphasizing accessibility, openness, and experimental enablement of industrial drive hardware rather than control-performance optimization. An industrial Yaskawa BLDC servomotor from the Motoman robot is used to determine switching sequences and safe operating parameters. Experimental open-loop tests were conducted by directly commanding the six inverter switching sectors, resulting in the stable synchronous rotation of the motor on the developed electromechanical platform. Full article

The operational reliability of Insulated Gate Bipolar Transistor (IGBT) modules in demanding transportation applications, such as traction systems, is critically challenged by solder layer and bond wire failures under cyclic thermal stress. To address this, this paper proposes a novel health monitoring framework that innovatively synergizes micro-scale spatial thermal analysis with microsecond electrical dynamics inversion. The method requires only non-invasive temperature measurements on the module baseplate and utilizes standard electrical signals (load current, duty cycle, switching frequency, DC-link voltage) readily available from the converter’s controller, enabling simultaneous diagnosis without dedicated voltage or high-bandwidth current sensors. First, a non-invasive assessment of solder layer fatigue is achieved by correlating the normalized thermal gradient ($\nabla T_{\mathrm{P}}$) on the baseplate with the underlying thermal impedance ($Z_{\mathrm{JC}}$). Second, for bond wire aging, a cost-effective inversion algorithm estimates the on-state voltage ($V_{\mathrm{ce},\mathrm{on}}$) by calculating the total power loss from temperature, isolating the conduction loss ($P_{\mathrm{cond}}$) with the aid of a Foster-model-based junction temperature ($T_{\mathrm{J}}$) estimate, and finally computing $V_{\mathrm{ce},\mathrm{on}}$ at a unique current inflection point ($I_{\mathrm{C},\inf }$) to nullify $T_{\mathrm{J}}$ dependency. Third, the health states from both failure modes are fused for comprehensive condition evaluation. Experimental validation confirms the method’s accuracy in tracking both degradation modes. This work provides a practical and economical solution for online IGBT condition monitoring, enhancing the predictive maintenance and operational safety of transportation electrification systems. Full article

Reliable multilevel inverter IGBT modules require precise loss and heat management, particularly in severe traction applications. This paper presents a comprehensive modeling framework for three-level T-type neutral-point clamped (TNPC) inverters using a high-power Insulated Gate Bipolar Transistor (IGBT) module that combines model predictive control (MPC) with space vector pulse width modulation (SVPWM). The particle swarm optimization (PSO) algorithm is used to methodically tune the MPC cost function weights for minimization, while achieving a balance between output current tracking, stabilization of the neutral-point voltage, and, consequently, a uniform distribution of thermal stress. The proposed SVPWM-MPC algorithm selects optimal switching states, which are then utilized in a chip-level loss model coupled with a Cauer RC thermal network to predict transient chip-level junction temperatures dynamically. The proposed framework is executed in MATLAB R2024b and validated with experiments, and the SemiSel industrial thermal simulation tool, demonstrating both control effectiveness and accuracy of the electro-thermal model. The results demonstrate that the proposed control method can sustain neutral-point voltage imbalance of less than 0.45% when operating at 25% load and approximately 1% under full load working conditions, while accomplishing a uniform junction temperature profile in all inverter legs across different working conditions. Moreover, the results indicate that the proposed control and modeling structure is an effective and common-sense way to perform coordinated electrical and thermal management, effectively allowing for predesign and reliability testing of high-power TNPC inverters. Full article

The reliability and lifetime of insulated gate bipolar transistors (IGBTs) are critical to ensuring the stability and safety of power electronic systems. IGBTs are widely used in electric vehicles, renewable energy systems, and industrial automation. However, their degradation over time poses a significant risk to system performance. Therefore, this paper proposes a data-driven approach based on a Long Short-Term Memory (LSTM) network optimized by a Genetic Algorithm (GA) to predict IGBT degradation. The study examines the health monitoring of insulated gate bipolar transistors from a device physics perspective. Degradation mechanisms that alter parasitics and electro-thermal stress produce characteristic changes in the turn-off overvoltage and the on-state voltage. Using power-cycling data from packaged half-bridge modules, an LSTM-based sequence model configured by a genetic algorithm search reduces error against an identically trained baseline (RMSE = 0.0073, MAE = 0.057, MAPE = 0.726%) under the shared protocol, with the clearest advantages in the early stage of degradation. These results support predictive maintenance and health management in power-electronic systems. Full article

New energy vehicles (NEVs) rely heavily on Insulated-Gate Bipolar Transistors (IGBTs) to perform frequent battery voltage conversions for operations such as acceleration, deceleration, and hill climbing. Consequently, effective thermal management of the IGBT junction temperature is critically important. This study investigates the junction temperature of IGBT modules equipped with pin-fin heat sinks of varying spacings under diverse operating conditions. The effects of the coolant inlet flow velocity and temperature on the junction temperature were examined. Furthermore, the pin-fin heat sink structure was optimized to enhance temperature uniformity across the IGBT chips. The results indicate that (1) IGBT modules with small-spacing pin-fin heat sinks exhibit improved thermal performance and enhanced temperature uniformity under specific conditions; (2) coolant inlet flow velocity is positively correlated with both module cooling efficiency and temperature uniformity; (3) coolant inlet temperature is inversely correlated with module junction temperature and chip junction temperature uniformity; and (4) among the three optimization schemes evaluated, the dual-channel, non-uniformly spaced pin-fin heat sink delivered the optimal performance, reducing the maximum junction temperature difference between IGBT chips to approximately 0.5 °C and that between diode chips to approximately 1.0 °C. Full article

In high-power insulated gate bipolar transistor (IGBT) module thermal management, the structural design of microchannel cooling plates plays a crucial role in determining heat dissipation efficiency and temperature uniformity. This study focuses on the effects of honeycomb-structured unit dimensions and arrangements, as well as inlet/outlet configurations of the cooling plate on its thermal and flow performance. Additionally, the influence of different coolant inlet velocities and temperatures is investigated. Under constant coolant flow rate and boundary conditions, four design configurations with varying pore widths and channel spacings were evaluated numerically. The results indicate that the optimized honeycomb structure can reduce the module’s peak temperature by approximately 8.7 K while significantly improving temperature uniformity and maintaining a moderate pressure drop. Moreover, increasing the number of inlets and outlets effectively lowers the pressure drop and enhances thermal uniformity. Although increasing the coolant flow rate and reducing the inlet temperature can further improve cooling performance, these measures also lead to notable increases in energy consumption and pressure loss. Therefore, a trade-off between thermal enhancement and system energy efficiency must be considered in practical applications. The findings of this study provide practical guidance for the design optimization of high-efficiency microchannel liquid cooling systems in power electronic applications. Full article