Search Results (9)

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article

Split Gate SiC MOSFETs (SG-MOSFETs) have been demonstrated to exhibit excellent power dissipation at high operating frequencies due to their low specific reverse transfer capacitance (C_rss,sp); however, there are several reliability issues of SG-MOSFETs, including electric field crowding at the gate oxide and insufficient short-circuit (SC) robustness. In this paper, we propose a device structure to enhance the short-circuit withstand time (SCWT) of 1.2 kV SG-MOSFETs. The proposed P-shielded SG-MOSFETs (PSG-MOSFETs) feature a P-shielding region that expands the depletion region within the JFET region under both blocking mode and SC conditions. Compared to the conventional structure, this reduces the maximum electric field in the gate oxide, enabling a higher doping concentration in the JFET region, which can reduce the specific on-resistance (R_on,sp) to minimize power dissipation during device operation. The SC robustness of PSG-MOSFETs, with an R_on,sp identical to those of SG-MOSFETs, was investigated by adjusting the width of the P-shielding region (W_P). Furthermore, the C_rss,sp of PSG-MOSFETs was compared with that of SG-MOSFETs to analyze the relationship between the W_P and high-frequency figure of merit (HF-FOM), defined as R_on,sp × C_rss,sp. These results demonstrated that the PSG-MOSFET achieved an enhanced SC robustness and HF-FOM in comparison to the SG-MOSFET. Thus, the proposed PSG-MOSFET is a highly suitable candidate for high-frequency and reliable applications. Full article

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity. Full article

In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons appears because of the LBD; thus, a path that makes it easier for electrons to transfer from the N+ source to the drift region is provided, finally eliminating the bipolar degradation of the body diode. At the same time, the LBD integrated in the P-well region weakens the scattering effect of interface states on electrons. Compared with the gate p-shield trench 4H-SiC MOSFET (GPMOS), the reverse on-voltage (V_F) is reduced from 2.46 V to 1.54 V; the reverse recovery charge (Q_rr) and the gate-to-drain capacitance (C_gd) are 28% and 76% lower than those of the GPMOS, respectively. The turn-on and turn-off losses of the DT-LBDMOS are reduced by 52% and 35%. The specific on-resistance (R_ON,sp) of the DT-LBDMOS is reduced by 34% due to the weaker scattering effect of interface states on electrons. The HF-FOM (HF-FOM = R_ON,sp × C_gd) and the P-FOM (P-FOM = BV²/R_ON,sp) of the DT-LBDMOS are both improved. Using the unclamped inductive switching (UIS) test, we evaluate the avalanche energy of devices and the avalanche stability. The improved performances suggest that DT-LBDMOS can be harnessed in practical applications. Full article

A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (${\mathrm{C}}_{\mathrm{gd}}$) and reduce the specific ON-resistance (${\mathrm{R}}_{\mathrm{on},\mathrm{sp}}$) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower ${\mathrm{R}}_{\mathrm{on},\mathrm{sp}}$, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications. Full article

650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal ${\mathrm{P}}^{+}$ layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (${\mathrm{R}}_{\mathrm{on},\mathrm{sp}}$) and lowers the gate-drain capacitance (${\mathrm{C}}_{\mathrm{gd}}$). It was experimentally shown that a thinner gate oxide further reduces ${\mathrm{R}}_{\mathrm{on},\mathrm{sp}}$, although with a penalty in terms of increased ${\mathrm{C}}_{\mathrm{gd}}$. A design with 0.5 $\mathsf{\mu }$m half JFET width, enhanced JFET doping concentration of $5.5\times {10}^{16}$ cm⁻³, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices. Full article

A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (E_MOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (C_GD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET. Full article

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (C_GD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (R_ON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (C_GD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = R_ON,SP × C_GD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an E_MOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications. Full article

In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively, compared to C-UMOSFET. Since the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is superior to that of C-UMOSFET, it improves high frequency figure of merit (HF-FOM: R_ON-SP × Q_GD). The HF-FOM of DT-MOSFET and ST-MOSFET is 289 mΩ∙nC, 224 mΩ∙nC, respectively, which is improved by 26% and 42% compared to C-UMOSFET. The switching speed of DT-MOSFET and ST-MOSFET are maintained at the same level as the C-UMOSFET. The switching energy loss and power loss of the DT-MOSFET and ST-MOSFET are slightly improved compared to C-UMOSFET. Full article