Search Results (647)

This paper describes two front-end architectures developed in a 28 nm CMOS process for the readout of pixel detectors in future high-energy physics (HEP) colliders and advanced X-ray imaging instrumentation. The front-end channels have been developed in the framework of the PiHEX project, funded by the Italian Ministry of University and Research. PiHEX aims to improve the state of the art of pixel readout chip technology in high-luminosity colliders and X-ray imagers in the next generation of free electron lasers (FELs) by developing, in 28 nm CMOS technology, the fundamental microelectronic building blocks for pixel readout chips. Such blocks, also implementing innovative circuit ideas, will enable, in future applications, the integration of large-scale readout chips, meeting a set of challenging requirements, such as high spatial resolution, high signal-to-noise ratio, very wide dynamic range and the capability to withstand unprecedented radiation levels. Two different front-end channels were designed, integrated into two prototype chips, and tested. One architecture, featuring a pixel size of 25 µm × 100 µm, was optimized for tracking applications in high-energy physics experiments, like the ones that take place at CERN in the high-luminosity upgrade of the Large Hadron Collider (LHC), while the second one, featuring a pixel size of 110 µm × 55 µm, was devised for X-ray imaging applications in FELs. Full article

This paper presents a compact output-stage current-limiting architecture intended for reliable overcurrent protection in CMOS analog and mixed-signal circuits. In modern integrated systems, the output stages of blocks such as operational amplifiers, drivers, buffers, and reference circuits may be exposed to overload conditions, low-impedance loads, or short circuits that can lead to excessive power dissipation and device degradation. The proposed architecture employs scaled replicas of the output transistors together with local negative feedback to sense the delivered load current and independently limit both sinking and sourcing currents. The circuit is demonstrated by integration into a two-stage folded-cascode operational amplifier with a class-AB output stage and evaluated through circuit-level simulations in 130 nm CMOS technology. The results confirm a well-defined current limit across the supply and temperature corners that are relevant to high-reliability applications, spanning 2 V and 5 V supplies and a temperature range from −55 °C to 175 °C. The proposed current-limiting scheme constrains both pull-down and pull-up currents to approximately 9–12 mA across the investigated operating domain. Monte Carlo analysis further shows bounded dispersion and symmetric single-mode distributions, indicating predictable operation under device mismatch. These results demonstrate that the proposed architecture provides a compact and scalable solution for deterministic current limiting in reliability-critical CMOS systems. Full article

This paper presents a K-band four-channel phased array beamformer with temperature compensation in 65 nm CMOS for 5G and satellite communications. The beamformer includes a four-way power divider/combiner, four RF channels, and digital control circuits. Each RF channel comprises a receive chain, a transmit chain, and a pair of receive/transmit (TX/RX) single-pole double-throw (SPDT) switches. The receive chain consists of a low-noise amplifier (LNA), a six-bit reflective-type phase shifter (RTPS), a drive amplifier (DA), two temperature-compensation attenuators (TCAs), and a six-bit attenuator (ATT); the transmit chain integrates a power amplifier (PA), two TCAs, a six-bit RTPS, a DA, and a six-bit ATT. Measurements show the chip exhibits 0–4.5 dB gain, noise figure (NF) < 7.8 dB, root mean square (RMS) phase error < 3.5°, and RMS gain error < 0.4 dB in receive mode operating in 19–23 GHz. In transmit mode operating in 21–23 GHz, it provides 6–10 dB gain range, RMS phase error < 3.4°, RMS gain error < 0.25 dB, and output power at 1 dB compression point (OP1dB) > 6.5 dBm. In addition, the receive and transmit gain variations are within 0.8 dB and 0.4 dB, respectively, when temperature ranges from −55 °C to 85 °C. With a compact footprint of 3.5 × 4.8 mm², the beamformer consumes 110 mW (receive) and 190 mW (transmit) DC power per channel. Full article

Single-event effects (SEEs) present a significant challenge to the radiation reliability of integrated circuits. Conventional SEE analysis methods for single-photon avalanche diode (SPAD) devices primarily rely on Sentaurus Technology Computer-Aided Design (TCAD) numerical simulation, which is computationally intensive and time-consuming. In this study, we propose a generalized deep learning (DL) model, using a silicon-based SPAD device with a double-junction double-buried-layer (DJDB) structure fabricated in 180 nm CMOS process as the research subject. By incorporating key parameters that influence SEEs as model inputs, the proposed approach enables rapid prediction of critical parameter metrics, including transient current peaks and dark count rates. Experimental results show that the DL model achieves a prediction accuracy of 97.32% for transient current peaks and 99.87% for dark count rates, demonstrating extremely high prediction precision. To further validate the generalization capability of the proposed network, the model is applied to predict the detection performance of the DJDB-SPAD device. The prediction accuracies for four key performance parameters all exceed 97.5%, further confirming the accuracy and robustness of the developed model. Meanwhile, compared with the conventional Sentaurus TCAD simulation method, the proposed method achieves a 336-fold improvement in computational efficiency. Overall, this method realizes the dual advantages of high precision and high efficiency, which provides an efficient and accurate technical solution for the rapid characteristic analysis and reliability evaluation of SPAD devices under single-event effects (SEEs). Full article

This paper presents two broadband four-way power dividers based on a novel T-coil topology, operating in the 22–32 GHz band (covering the K/Ka bands). Type I adopts a cascaded power division structure, while Type II employs a direct-feed integrated architecture. The innovation lies in the introduction of isolating capacitors at the input and output ports, which significantly shortens the critical transmission line lengths in both topologies. This effectively reduces the equivalent inductance and raises the self-resonant frequency, achieving wideband response while maintaining structural simplicity, compact size, and ease of integration. Both circuits were fabricated using a standard 45 nm CMOS process. The measured core chip areas (excluding pads) are only 0.125 mm² for Type I and 0.066 mm² for Type II, demonstrating excellent integration density. Through even-mode and odd-mode theoretical analysis and full-wave electromagnetic simulation verification, both power dividers exhibit good impedance matching and port isolation across the target frequency band. Measurement results further confirm their performance: across the entire 22–32 GHz band, both power dividers achieve a return loss better than 11 dB and isolation exceeding 15 dB; the insertion loss is 1.1–1.4 dB for Type I and 0.8–1.3 dB for Type II; the amplitude imbalance is below ±0.3 dB and ±0.1 dB, respectively; and the phase imbalance is less than ±5° and ±3°, respectively. All measured data show good agreement with simulation results. In summary, Type I offers advantages in layout flexibility and isolation performance, while Type II excels in insertion loss and chip size. Both provide practical circuit solutions for broadband, high-performance, and compact power division systems. Full article

The on-chip detection of circularly polarized light is pivotal for advancing applications in quantum optics, information processing, and spectroscopic sensing. However, conventional chiral metasurfaces often suffer from complex multilayer fabrication, material incompatibility, or modest performance, hindering their integration with photonic circuits. Here, we introduce a monolithic all-silicon metasurface that overcomes these limitations through a singular structural innovation. By strategically truncating four corners of a conventional Z-shaped meta-atom, we induce a hybridization of optical modes that profoundly enhances chiral light–matter interaction. This deliberately engineered perturbation yields a colossal circular dichroism with an extinction ratio exceeding 66 dB, a performance that surpasses existing state-of-the-art designs by approximately three orders of magnitude. Furthermore, the proposed metasurface exhibits remarkable fabrication robustness, owing to its single-layer architecture and CMOS-compatible material. We demonstrate that this exceptional metasurface can be directly integrated with a Mercury Cadmium Telluride (MCT) photodetector to form a highly efficient, compact circular polarization detector. Our work provides a simple yet powerful paradigm for creating high-performance chiral photonic devices, paving the way for their widespread adoption in integrated optoelectronics. Full article

This paper presents a low-noise analog front-end (AFE) integrated circuit (IC) circuit for capacitive micro-electromechanical system (MEMS) accelerometers that can be used for optical image stabilization (OIS) in various optical imaging systems. The AFE circuit design features a fully differential chopper stabilization technique that efficiently minimizes low-frequency 1/f noise and parasitic coupling. The AFE circuit chip is fabricated in a 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology and co-packaged with an x-axis capacitive MEMS accelerometer based on a silicon-on-glass (SOG) process. The SOG accelerometer has a footprint of 1000 $\mathsf{\mu }\mathrm{m}$ $\times$ 950 $\mathsf{\mu }\mathrm{m}$. The packaged system demonstrates a sensitivity of 342 mV/g and a nonlinearity of 1.1% between −1 g and +1 g, a dynamic range of 88 dB, and an equivalent noise floor of 14 $\mathsf{\mu }\mathrm{g}/\sqrt{\mathrm{H}\mathrm{z}}$. Full article

A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration. Full article

The goal of this research is to develop a predictive model that determines how low-frequency Electromagnetic Interference (EMI) affects the leakage current behavior of CMOS transistors. Although developed and validated using NMOS devices, the modeling framework can be extended to PMOS transistors; experimental validation of PMOS devices is planned for future work. The model provides essential physical parameter-based analysis of nanoscale device EMI susceptibility during low-frequency operation. The model demonstrates high accuracy and practicality through experimental verification of test chips built with standard TSMC CMOS technology nodes. The findings highlight that modern CMOS designs must account for low-frequency EMI, which can induce leakage shifts significant enough to impact EMC compliance, functional robustness, and reliability in ultra-low-power and near-threshold applications. The research delivers a practical method for designers to evaluate and reduce EMI-induced leakage in integrated circuits. Full article

The 100 GHz-class ultrafast photonic integrated circuit (PIC) positions itself as a promising technology in the post-Moore era, when the bandwidth limit of metallic interconnections constrains current electronic integrated circuits. Nevertheless, the lack of an effective on-chip, CMOS-compatible laser source challenges the ongoing development of PIC. Germanium straintronics facilitate bandgap transformation from indirect to direct, thereby enabling effective band-to-band radiative recombination. Some parameters, such as nanowire diameters or crystalline orientation and strain direction, have a profound effect on the bandgap transformation of Ge nanowires. In this review, we will discuss changes in the fundamental physical properties of Ge nanowires under strain, including mechanical, electronic, optical, and thermal properties. Subsequently, we summarize common methods for strain engineering, as well as novel approaches that have emerged in recent years. Some notable application cases reported in the last few decades will be discussed in detail. This review may fill knowledge gaps and provide a solid background for forthcoming investigations of on-chip strained Ge lasers. Full article

Secondary power supplies are an integral part of any complex device that requires power to different circuit nodes. This includes various kinds of telecommunication equipment, the aerospace industry, battery chargers, etc. Secondary power supplies include the most common pulse converters of both the boost, buck, and buck–boost variety, as well as forward, flyback, and push–pull converters. In particular, a galvanic isolation option may be considered for push–pull types. The use of multi–channel secondary power supplies is relevant for the space industry and satellites, where it is necessary to support the operation of many related devices. The efficiency of such devices is high due to their small number of elements and their simplicity of control. PWM (pulse width modulation) controllers can be considered as the last statement. In turn, the presence of radiation-resistant CMOS technology is required in outer space conditions, which is possessed by the PWM controller considered in this paper. Also, high efficiency and small dimensions can be achieved using planar technology. Here, one such secondary power supply, based on the PWM controller 5315EU015 with a power of 10 W, is considered, as well as the proposed design of a planar transformer. A mathematical model obtained from the algebraization of differential equations method, and from the PSIM software v. 22.2 simulation results and experiments is presented. Full article

Memristors are valuable elements with very good memory and switching features. They have minimal power consumption, nano-scale sizes, and a possibility for integration with high-density Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. They are applicable in neural networks, memory crossbars, and different electronic devices. This work considers some improved and existing models for memristors, functioning at high-frequency signals with a high speed and very good effectiveness. The main parasitic parameters—series resistance, capacitance, and small-signal direct current (DC) voltage and current shifting signals—are taken into account. An additional leakage conductance is analyzed as a parasitic component. The influence of the parasitic parameters on the normal functioning of memristor-based circuits is analyzed and evaluated at hard-switching and soft-switching modes. For investigations of the main characteristics of the considered models and their applicability in memory arrays, Linear Technology Simulation Program with Integrated Circuits Emphasis (LTSPICE) library models are generated and analyzed. The considered models operate at low-, middle- and high-frequency signals, clearly demonstrating the main properties of memristors. Their appropriate operation in passive memory arrays is analyzed and established. The proposed models have a 26% enhanced accuracy in fitting experimental i-v relations. They ensure good memory and switching properties for memory arrays. This work could be a suitable step towards the design and manufacturing of ultra-high-density memristor-based integrated chips. Full article

This paper presents a novel, minimalist floating memristor emulator circuit designed for low-power biomedical analog front ends. The proposed topology requires only two dynamic threshold MOS (DTMOS) transistors and one capacitor, constituting one of the most compact memristor emulators reported. The circuit operates without static power consumption and exploits the body-effect coupling in DTMOS devices to generate a state-dependent resistance. Comprehensive simulation in a 0.18 μm CMOS process verifies core memristive characteristics: a frequency-dependent pinched hysteresis loop tunable via capacitance, non-volatile memory, and robustness across temperature and process variations. Experimental validation using a discrete CD4007-based prototype confirms the pinched hysteresis loop from 100 Hz to 800 kHz, with a maximum simulated operating frequency of 500 MHz. A comparative analysis demonstrates that the design achieves a favorable trade-off, simultaneously minimizing transistor count and power while providing floating operation and high-speed performance. These attributes make the emulator a compelling candidate for integration into adaptive, area and power constrained biomedical signal conditioning systems. Full article

This work presents a systematic design flow for the fundamental building blocks (namely, the low-noise amplifier and the down-conversion mixer) of an analog receiver for 5G backhauling systems implemented in SiGe BiCMOS technology. The proposed methodology enables the sizing and optimization of receiver blocks up to post-layout simulations, starting from the specified performance requirements. It accounts for both the parasitic effects of active devices and the distributed effects of interconnects. The design flow was applied using STMicroelectronics BiCMOS55X technology to develop low-noise amplifiers and D-band to E-band downconverters capable of covering the 130–150 GHz and 150–165 GHz sub-bands. Preliminary measurement results obtained from both the standalone LNA blocks and the complete receivers are presented and discussed. Full article

Mixers are integral components in RF circuits for frequency conversion and are present in almost all RF front-ends. The relentless advancement of mobile communication standards, particularly towards 5G-Advanced and 6G, imposes ever more stringent and multi-dimensional performance requirements on mixer design. While previous surveys have capably summarized mixer technologies, this review distinguishes itself by providing a comprehensive and critical examination of millimeter-wave and sub-THz silicon-based integrated mixers, with explicit coverage extended from core RF bands to beyond 170 GHz. We place particular emphasis on the unique challenges and trade-offs inherent to silicon (CMOS and SiGe BiCMOS) platforms at these high frequencies. This work first summarizes the structural frameworks and underlying principles of mixers, examines multiple mixer variants, and performs an in-depth analysis of their key performance characteristics, encompassing conversion gain, noise figure (with distinctions between single-sideband (SSB) and double-sideband (DSB) definitions), isolation, and related metrics. Then, it compares and discusses the design of several mixers, especially analyzing their innovative points and key technologies, while critically evaluating their inherent limitations and trade-offs. Furthermore, a dedicated section synthesizes the most recent research trends, including heterogeneous integration, AI/ML-assisted design, and mixer architectures for integrated sensing and communication (ISAC), thereby addressing a notable gap in the current literature. Finally, it concludes with an outlook on future challenges and opportunities for mixers in next-generation communication systems. Full article