Replica-Based Bidirectional Output Current Limiting for High-Reliability CMOS Class AB Stages

Abstract

This paper presents a compact output-stage current-limiting architecture intended for reliable overcurrent protection in CMOS analog and mixed-signal circuits. In modern integrated systems, the output stages of blocks such as operational amplifiers, drivers, buffers, and reference circuits may be exposed to overload conditions, low-impedance loads, or short circuits that can lead to excessive power dissipation and device degradation. The proposed architecture employs scaled replicas of the output transistors together with local negative feedback to sense the delivered load current and independently limit both sinking and sourcing currents. The circuit is demonstrated by integration into a two-stage folded-cascode operational amplifier with a class-AB output stage and evaluated through circuit-level simulations in 130 nm CMOS technology. The results confirm a well-defined current limit across the supply and temperature corners that are relevant to high-reliability applications, spanning 2 V and 5 V supplies and a temperature range from −55 °C to 175 °C. The proposed current-limiting scheme constrains both pull-down and pull-up currents to approximately 9–12 mA across the investigated operating domain. Monte Carlo analysis further shows bounded dispersion and symmetric single-mode distributions, indicating predictable operation under device mismatch. These results demonstrate that the proposed architecture provides a compact and scalable solution for deterministic current limiting in reliability-critical CMOS systems.

1. Introduction

Modern microelectronics has reached a stage where performance, energy efficiency, and reliability must be achieved simultaneously within a technological landscape defined by CMOS scaling [1], reduced supply voltages, and increasing integration density. In this context, the design of integrated analog circuits requires a careful balance between linearity, precision, stability across the full process–voltage–temperature (PVT) domain, and robust operation under diverse load conditions. In advanced mixed-signal architectures, building blocks such as high-resolution data converters, operational amplifiers, high-speed comparators, buffers, drivers, current-steering DACs (iDACs), and reference circuits with load-driving capability rely heavily on output stages that directly interact with the external load.

These stages must respond reliably to variations in the load current, which directly influence the system performance, power consumption, and long-term device reliability. This requirement becomes particularly critical in precision- and safety-critical domains such as automotive and aerospace electronics, where strict constraints are imposed on both the maximum current consumption and the fault behavior of the system. In such applications, the ability to limit the maximum output current under abnormal conditions is essential for preventing excessive power dissipation and ensuring predictable circuit operation.

In advanced CMOS technologies, transistor scaling and gate-oxide thinning increase devices’ sensitivity to high-current stress and localized self-heating effects. Without a dedicated limiting mechanism [2], the output transistor may be forced to conduct currents imposed by the external load, potentially reaching destructive levels. Situations such as low-impedance loads, short circuits, or overload events expose the output stage to these conditions, which may result in excessive power dissipation, electrical degradation, or permanent device failure. This requirement becomes particularly stringent in aerospace and automotive systems operating over extended temperature ranges, where circuits must maintain reliable behavior from −55 °C to 175 °C while remaining compliant with strict power and reliability constraints.

The temperature range from −55 °C to 175 °C was intentionally defined as a composite worst-case validation envelope for the proposed protection-oriented circuit, rather than as a single universal industry-standard operating range. More specifically, the lower bound of −55 °C reflects the severe low-temperature conditions that are commonly associated with aerospace and other high-reliability qualification frameworks, where cold-start operation, increased threshold voltages, and reduced internal voltage headroom may critically challenge the correct biasing and switching of analog building blocks. In this broader context, aerospace-oriented qualification environments are commonly associated with extended thermal windows reaching down to approximately −55 °C, with upper limits often lying around 150 °C to 155 °C depending on the target platform and qualification margin. In contrast, the upper bound of 175 °C captures the elevated junction-temperature stress that is relevant to harsh automotive power and smart-driver integrated circuits, for which local self-heating, leakage growth, mobility degradation, and bias redistribution become particularly pronounced under overload or protection-triggering conditions. Correspondingly, automotive electronics are typically evaluated from approximately −40 °C, while junction temperatures of up to 175 °C are especially relevant for harsh automotive power-, driver-, and protection-oriented integrated circuits exposed to substantial local thermal stress. Therefore, the adopted −55 °C to 175 °C interval deliberately combines the most demanding low-temperature boundary, typically associated with aerospace-oriented validation, with the high-temperature junction stress characteristic of automotive protection and power-adjacent operation. More specifically, the final simulation range was intentionally established by combining the lower bound of the aerospace-relevant thermal envelope (approximately −55 °C to 155 °C) with the upper bound of the automotive-relevant thermal envelope (approximately −40 °C to 175 °C), thereby yielding the conservative composite interval of −55 °C to 175 °C used in this work. This extended thermal sweep is especially justified here because the proposed circuit does not merely perform analog signal processing, but enforces a maximum output-current constraint; consequently, its validity must be demonstrated under the thermal extremes that most strongly affect protection-threshold stability, current-limit accuracy, and worst-case functional integrity. In the present work, both the proposed output current-limiting block and the operational amplifier used for validation were implemented and simulated in the same commercial 130 nm GlobalFoundries CMOS technology. This technology provides a well-established analog/mixed-signal platform, offering reliable device models, robust implementation conditions, and sufficient flexibility for the integration of precision analog and protection-oriented functions. Adopting a common technological framework is particularly important in this context, since the limiting mechanism must be evaluated together with the output stage under identical device characteristics, parasitic conditions, process spread, local mismatch, and extended temperature variations. This is particularly important in protection-oriented analog circuits, where the correct operation of the limiting branch depends not only on its internal biasing conditions, but also on its dynamic interaction with the output transistors during overload and short-circuit events.

The proposed architecture employs 5 V devices, as they provide the voltage headroom required by the limiting branches and the output stage, while also mitigating the stronger mismatch-related variability associated with thin-oxide low-voltage devices available in the same 130 nm process. In submicron conditions, such devices are more susceptible to larger current deviations, even under comparable transconductance conditions, due to the stronger contribution of current-factor variation (Δβ) [3]. For the present protection-oriented function, this aspect is particularly important, since these effects may directly impair the stability and predictability of the enforced maximum output current limit under severe operating conditions.

Implicit limitations arising from parasitic resistances [4], conservative device sizing, or feedback-loop constraints cannot guarantee predictable behavior under critical operating conditions. Moreover, process variations and transistor parameter dispersion can produce substantial differences between the estimated and actual maximum current levels, complicating compliance with reliability specifications across the PVT range. This issue becomes especially critical in harsh-environment applications, where circuits must remain robust under electrical stress, thermal cycling, and long-term aging. These limitations emphasize the need for a compact, integrable, and accurate mechanism that allows designers to define a robust current limit independently of load conditions and technological variations.

Within this technological and industrial context, integrating a dedicated output-stage current-limiting block becomes essential. Such a block must accurately control the maximum sourced or sunk current, providing active, scalable, and reproducible limiting behavior that passive mechanisms cannot achieve in modern CMOS technologies.

This work presents and validates a scalable output-stage overcurrent-limiting architecture that is suitable for integration into a wide range of analog building blocks. The proposed approach provides a well-defined and reproducible current clamp while maintaining a negligible impact on nominal circuit operation.

Recent advances in CMOS analog integrated-circuit design increasingly emphasize the use of mixed-voltage and mixed-device methodologies, particularly in applications where classical low-voltage optimization alone is no longer sufficient to simultaneously satisfy the requirements of voltage tolerance, output-drive capability, dynamic performance, and long-term robustness. In a conventional low-voltage amplifier design, standard MOSFETs are generally preferred because of their superior intrinsic speed, higher transconductance efficiency, and more favorable capacitance-to-current trade-offs. However, when the circuit is intended to operate in environments involving elevated node voltages, large output excursions, strong electrical overstress, or interaction with power-stage-related signals, the exclusive use of standard low-voltage devices may become restrictive from both a functional and a reliability standpoint. For this reason, a growing number of modern CMOS architectures adopt a mixed-device strategy in which standard-voltage transistors are retained in the signal-processing or gain-critical branches, while high-voltage devices are selectively introduced in stress-sensitive nodes, output interfaces, bias-protection paths, or branches exposed to large common-mode or large-signal swings.

This combined approach enables a more favorable compromise among analog performance, allowable terminal stress, voltage headroom distribution, and safe-operating margins. Such trends can be observed not only in precision analog or sensor-interface circuits, but also in the driver-oriented, protection-oriented, and mixed-signal front-end structures implemented in automotive and industrial technologies. Moreover, the recent literature on advanced CMOS amplifier design [5] also includes high-frequency and GHz-range topologies, where the optimization of bandwidth and dynamic behavior is often achieved through more elaborate architectural choices involving transistor-class partitioning, stacked or cascoded arrangements, and tailored output-stage solutions that are capable of balancing speed, efficiency, and voltage handling. Although the design targets of such GHz amplifiers differ from those of the present work, these studies still support a broader architectural conclusion that is directly relevant here: namely, that the selection and placement of standard- versus high-voltage devices should be regarded as a first-order design decision, since it directly impacts the internal stress distribution, bias robustness, headroom availability, large-signal behavior, and sensitivity to process and temperature variations [6]. This consideration becomes even more critical in protection-oriented analog circuits, where the circuit must not only preserve nominal analog functionality, but must also maintain a predictable protection threshold and a stable intervention mechanism under fault-relevant operating conditions.

From this perspective, the operational amplifier used in the present study is not intended as a GHz-optimized amplifier case study, but rather as a representative analog environment in which the proposed current-limiting block can be meaningfully evaluated under realistic output-stage stress. Consequently, the discussion is intentionally centered on the aspects that are directly relevant to the contribution of this paper: namely, the rationale for the adopted class-AB output stage, the use of 5 V devices in the protection path within the selected 130 nm GlobalFoundries CMOS process, and the resulting capability of the integrated solution to preserve stable maximum-current limitation under mismatch, extended thermal stress, and harsh operating conditions.

Although demonstrated on a two-stage folded-cascode operational amplifier (op-amp) [4,7], the proposed approach is inherently general and is intended for reliability-critical CMOS applications in which the output stage may be exposed to overload events, short-circuit-like conflict conditions, self-heating stress, and extended operating temperature ranges. In such scenarios, the design objective is not merely to enforce a current limit, but to do so in a manner that remains compatible with the normal analog operation of the amplifier and does not compromise its overall functionality.

In this context, the contribution of the present work extends beyond the current-limiting principle itself and lies in the implementation and practical validation of a dedicated output current-limiting block as an integral part of a complete operational amplifier in 130 nm GlobalFoundries CMOS technology. Rather than treating the protection circuitry as an isolated conceptual addition, the proposed solution is developed, integrated, and assessed at full-circuit level, so that both the effectiveness of the limiting action and its interaction with the surrounding amplifier architecture are explicitly captured. This aspect is particularly important in analog integrated design, where the insertion of protection circuitry may alter the biasing conditions, the dynamic behavior, or the achievable output-stage performance if they are not carefully co-designed with the main signal path.

More specifically, the proposed protection function is evaluated not only with respect to its ability to constrain the output current under severe output-conflict conditions, but also with respect to its impact on the conventional analog performance of the complete op-amp. To this end, the design is verified at both the schematic and post-layout (PEX) level, including Monte Carlo analysis, extended-temperature evaluation, and a before/after comparison of key amplifier metrics such as input-referred offset voltage, frequency-stability indicators, output-noise levels, and quiescent current. In addition, dedicated transient analyses are included to demonstrate the controlled activation of the limiting mechanism and to verify that the transition from nominal operation to the current-limited regime does not introduce sustained oscillatory behavior.

Therefore, beyond demonstrating the feasibility of the limiting concept, the present work provides a practically validated protection-oriented analog design in which output current limiting, robustness under adverse operating conditions, and preservation of the main analog performance characteristics are addressed simultaneously within the same integrated implementation. This combined emphasis on functional protection, post-layout robustness, and performance preservation constitutes the main practical contribution of the paper, with respect to previously reported current-limiting approaches.

This article is organized as follows. Section 2 introduces the proposed output current-limiting architecture and describes its integration into the operational amplifier used for validation. The operating principle of the replica-based limiting branches and their interaction with the class-AB output stage are also discussed. Section 3 presents the schematic-level simulation results and evaluates the effectiveness of the current-limiting mechanism under different supply voltages and temperatures. Monte Carlo analysis and process-corner simulations are further performed to assess statistical dispersion and robustness across the PVT domain. Section 4 details the layout implementation of the proposed current-limiting block and discusses the post-layout (PEX) simulation results. Finally, Section 5 summarizes the main conclusions of this work.

2. Proposed Current Limit Architecture

A current-limiting circuit implemented at the output of mixed-signal blocks, such as operational amplifiers, is a valuable feature, as it protects the output stage against overload by restricting the maximum current delivered to the load. In this way, damage to the output transistors is prevented in the event of a short circuit or excessive current demand, ensuring safe and reliable operation in applications where the load may vary significantly. This protection is achieved by maintaining the output current below a predefined limit, even in the presence of variations in load impedance or load voltage.

The proposed output current-limiting circuit is presented in Figure 1. The limiter comprises two quasi-symmetric branches that independently clamp the currents conducted by the nMOS and pMOS output devices.

The adopted amplifier configuration includes the gain core, the output driver interfacing the load, and the bias network [8] that generates and replicates the internal bias currents required for proper operation of both the amplifier and the limiting mechanism.

The proposed architecture is evaluated by integration into the operational amplifier shown in Figure 2, in order to verify its capability to constrain the maximum load current. The adopted amplifier follows a conventional two-stage topology with a folded-cascode first stage.

The first gain stage is formed by the input differential pair together with the folded-cascode devices, which provide increased voltage headroom for low common-mode voltages while improving the gain through the common-gate folded-cascode configuration (M₂₅–M₂₈) [9]. The second stage is implemented as a common-source output stage that provides additional voltage amplification and further increases the overall gain.

Class-AB output stages remain widely used in CMOS amplifier design, because they provide a practical trade-off between static power dissipation, output drive capability, and analog continuity at the output node. The current literature continues to confirm the relevance of class-AB solutions in both low-voltage fast-settling amplifiers and high-speed multi-stage CMOS amplifier topologies, where the balance between efficiency, slew-rate capability, and stable large-signal behavior remains a key design consideration [10,11]. In the present work, the nodes PG and NG correspond to the gate terminals of the output transistors, M35 and M36, which operate in a class-AB configuration, with both drain terminals connected to the output node. A class-AB output stage [12] was selected because it provides the most appropriate compromise between power efficiency, analog continuity, and output drive capability for the present protection-oriented architecture. In particular, a class-A solution, although highly linear, would impose unnecessary static power dissipation, which is undesirable in a circuit that is specifically intended to reduce excessive output-stage stress under overload conditions. By contrast, a class-B solution offers higher efficiency but is generally more affected by crossover-related nonlinearity and less controlled conduction around the output transition region. In the present work, where the proposed limiting block must interact predictably with the output stage during both normal operation and severe overload events, class-AB operation offers a more suitable balance between the reduced quiescent current and smooth source/sink current delivery.

This class-AB output stage improves power efficiency by enabling alternate conduction of the pull-up and pull-down devices, thereby reducing static current consumption. Since M₃₅ and M₃₆ operate in a common-source configuration, they also provide both voltage and current gain and significantly influence the dominant pole, which is mainly set by equivalent resistance and capacitance at the output node. Without compensation [13], the dominant pole can be adjusted through the load capacitance; however, an RC network placed between the output node and the gates of the output devices allows for controlled pole placement that is independent of the first two poles. Therefore, Miller compensation implemented with C₃, C₄, R₁, and R₂ is employed to improve stability by shifting the dominant pole to lower frequencies, thus avoiding the need for impractically large load capacitance compared with the second-stage gate capacitance C_gs [14].

The gain of the first stage is mainly set by the transconductance of the differential pair transistors, M₁–M₂, while the current flowing through their drains is collected by the associated active loads and then transferred to the folded cascode devices. Unlike the conventional two-stage gain architecture—where a diode-connected transistor is placed at the drain of one of the input differential transistors, imposing a minimum bias voltage of about Vth—the proposed alternative, implemented as a folded cascode, significantly reduces this minimum requirement to roughly one V_OV. This provides a larger voltage headroom, which is especially beneficial for low-supply operation.

In the configuration shown in Figure 1, transistors M₁₀ and M₁₉ are scaled replicas of the class-AB output devices M₃₆ and M₃₅, respectively, and serve to sense and regulate the output current within the proposed limiting architecture. Transistors M₅–M₈ and M₁₅–M₁₈ are low-threshold devices (approximately 300 mV), which enables a wider voltage swing at the gate of M₉ and, respectively, M₂₀. These transistors drive the internal nodes NG and PG, which define the gate voltages of the output-stage replica devices.

The branches biased by the cascoded pMOS and nMOS current mirrors (M₁–M₂ and M₁₁–M₁₂) are unbalanced with a 1:5 current ratio (1 μA through M₁ and M₁₁, and 5 μA through M₂ and M₁₂). This mismatch is preserved until the source potentials of M₅ and M₆ are equalized through output-dependent current injection via M₈, and it ensures operation of the output stage below the current-limiting threshold.

As long as the two branches set by M₇ and M₈ remain unbalanced, and M₈ requires a current five times larger than M₇ to set the same source potential for M₆ as for M₅, the source of M₁₀ (also the source of M₆) stays at a lower potential. Consequently, V_GSM6 remains higher than V_GSM₅, meaning that M₆ is stronger than M₅. This pulls the gate of M₉ towards the ground, reduces V_GSM9, and allows M₁₀ (and implicitly M₃₆) to remain normally biased, so the output current is not limited.

As the output current increases, the potential at node NG rises, which also increases V_GSM10. This requires a larger current to be injected into the drain of M₈. The resulting shift in the internal biasing reduces V_GSM6, raises the gate potential of M₉, and reduces V_GSM10 by driving NG down, until equilibrium is reached between the drain voltages of M₅ and M₆. After this equilibrium is established, the gate of M₉ is held at a quasi-constant potential, which stabilizes the current through M₁₀ and therefore clamps the output current through M₃₆.

Any attempt to force a higher output current strengthens the limiting action: additional current is injected through M₈, V_GSM6 is further reduced, the gate voltage of M₉ increases, and V_GSM10 is progressively reduced, ultimately driving M₁₀ out of conduction and enforcing the output current clamp.

A mirrored structure is used to limit the current sourced by the pMOS output device. As the sourcing current increases, the gate potential PG of the pMOS output transistor M₃₅ and of its replica M₁₉ tends to decrease. PG is defined at the drain of M₂₀ and applied to the gate of M₁₉, while the drain of M₁₉ is connected to the output.

As PG decreases, V_SGM19 increases and M₁₉ draws more current, which lowers its source potential. This reduces V_SGM16 and lowers the drain voltage of M₁₆, which is also connected to the gate of M₂₀. As a result, V_SGM20 increases, raising PG towards V_DD and reducing V_SGM19. This negative feedback continues until M₁₉ is driven out of its active region and no longer draws additional current. At that point, the internal branches reach equilibrium, and the sourced output current becomes limited.

3. Simulations and Results

In this section, the results of the proposed architecture, obtained from circuit-level analysis, are presented and discussed. Schematic-level simulations were performed in 130 nm CMOS technology to evaluate the behavior of the proposed output-stage current-limiting circuit implemented in the two-stage operational amplifier. This 130 nm technology node was selected for its robust behavior over extended temperature ranges and its suitability for long-term reliable operation. Although the operational amplifier itself is not the primary subject of this work, a brief conventional performance assessment is still warranted in order to verify that the integration of the output current-limiting block does not adversely affect the overall analog behavior of the complete circuit. To this end, the op-amp was evaluated before and after the inclusion of the limiting circuitry in terms of input-referred offset, frequency-domain stability indicators (phase margin, unity-gain bandwidth, and gain margin), output noise, and quiescent current, under different supply-voltage and temperature conditions. The corresponding results are presented in

Table 1. Conventional analog performance of the operational amplifier prior to the integration of the output current-limiting block, evaluated over supply voltage and temperature.

VDD (V)	VCM (V)	Temp. (°C)	Mean VOS (μV)	Std. Dev. VOS (μV)	Phase Margin (°)	UGBW (MHz)	Gain Margin (°)	Noise @ 1 kHz	Noise @ 10 kHz	Iq (μA)
2	0.7	−55	−4.67	238.54	51.11	3.64	27.73	20.24	13.13	−148.4
		25	−7.04	254.25	54.58	3.82	28.75	22.45	15.1	−211.5
		150	−15.83	282.76	56.16	3.75	30.71	26.17	17.92	−308.9
		175	−19.91	289.09	56.21	3.72	31.08	26.9	18.46	−328
5	2.5	−55	−0.14	235.98	62.23	5.23	23.07	20.05	12.97	−202
		25	−3.4	250	64.42	5.03	24.79	22.13	14.83	−268.5
		150	−10.34	276.09	64.82	4.56	27.22	25.63	17.49	−369.2
		175	−13.02	281.89	64.64	4.49	27.63	26.31	17.99	−388.8

and

Table 2. Conventional analog performance of the operational amplifier after the integration of the output current-limiting block, evaluated over supply voltage and temperature.

VDD (V)	VCM (V)	Temp. (°C)	Mean VOS (μV)	Std. Dev. VOS (μV)	Phase Margin (°)	UGBW (MHz)	Gain Margin (°)	Noise @ 1 kHz	Noise @ 10 kHz	Iq (μA)
2	0.7	−55	−5.64	231.44	49.12	3.61	27.69	20.24	13.13	−151.3
		25	−8.04	245.65	52.77	3.8	29.09	22.45	15.1	−215.6
		150	−16.54	271.39	54.65	3.73	31.24	26.17	17.92	−314.8
		175	−19.90	277.19	54.75	3.7	31.61	26.9	18.46	−334.2
5	2.5	−55	−0.97	229.52	59.53	5.22	23.5	20.05	12.97	−205
		25	−4.22	242.38	62.16	5.02	25.33	22.13	14.83	−272.7
		150	−10.86	266.13	63.1	4.55	27.81	25.63	17.49	−375.2
		175	−12.83	271.44	62.99	4.47	28.22	26.31	17.99	−395.1

.

A comparison of Table 1 and Table 2 indicates that the integration of the output current-limiting block has only a limited impact on the conventional analog performance of the complete operational amplifier. In particular, the frequency-stability indicators, namely phase margin, unity-gain bandwidth (UGBW), and gain margin, remain within comparable ranges before and after integration, which suggests that the overall dynamic behavior of the amplifier is well-preserved despite the additional output-stage circuitry. The input-referred offset voltage V_OS is likewise preserved, with only minor changes in its mean value and a slight but consistent reduction in its standard deviation across all investigated operating conditions. The output-noise levels at 1 kHz and 10 kHz remain unchanged after integration. Only small variations in the quiescent current are observed, which are consistent with the inclusion of the additional current-limiting circuitry. Overall, the results show that the intended protection function is achieved while preserving the main analog performance characteristics of the op-amp.

The amplifier output was loaded with a 10 kΩ resistive load and a 100 pF capacitive load in order to emulate representative nominal operating conditions. These loading values were used as the baseline configuration for evaluating the current-limiting behavior and its associated statistical dispersion under consistent external loading conditions. For the dedicated validation of the protection function, the testbench shown in Figure 3 employs selectively activated 1 Ω branches to emulate severe overload conditions. In this way, the reported results distinguish between the statistical assessment performed under fixed nominal loading and the functional verification of the proposed limiter under controlled worst-case stress conditions, allowing for a meaningful comparison between the limiting behaviors associated with the pMOS and nMOS output devices.

The testbench shown in Figure 3 was developed to validate the proposed output current-limiting architecture under controlled overload conditions applied on both output transitions of the operational amplifier. The non-inverting input, INP, is biased at a constant reference level equal to V_DD/2 by source E₂, while the inverting input, INN, is driven above or below this reference in order to force the output stage alternately toward the negative or positive supply rail. This allows the limiting action to be evaluated for both conduction paths of the class-AB output stage.

The overload condition is established by ideal switches that selectively connect 1 Ω resistors in the corresponding branches. Owing to their low resistance, these elements dominate the respective conduction paths and create, under a 5 V supply, an equivalent severe-load condition corresponding to approximately 5 A. This enables a direct evaluation of the proposed protection mechanism under high-current stress. In this manner, the testbench reproduces a controlled worst-case operating scenario, allowing the limiting behavior to be assessed under conditions that are representative of short-circuit or low-impedance loading. It also provides a consistent framework for comparing the limiting action under both polarities of the output transition, ensuring that the protection function is verified symmetrically for the two output devices.

For INN > INP, the output is driven toward the negative rail and the nMOS output transistor becomes active, while the pMOS device remains off; in this case, the upper branch is forced into the overload condition in order to validate the limiting action on the falling transition. Conversely, for INP > INN, the output is driven toward the positive rail and the pMOS transistor becomes active, while the lower branch is forced into the corresponding overload condition to validate the limiting action on the rising transition. In both operating cases, the proposed architecture successfully limits the output current, reducing the equivalent overload demand from approximately 5 A to about 10 mA.

The output current-limiting block prevents uncontrolled and potentially destructive power consumption while ensuring protection of the final-stage transistors under overcurrent conditions.

In a particular operating scenario, when the amplifier is configured as a comparator, rapid switching events induced by input noise may cause oscillations around the switching threshold, leading to increased current consumption in the output stage, where power dissipation is maximal. Under such conditions, the proposed limiting mechanism reduces the risk of excessive self-heating, mitigates electrical overstress, and improves the robustness and long-term reliability of the overall circuit.

The transistor sizes and the corresponding values of the other components forming the proposed architecture are provided in

Table 3. Design parameters for presented output current-limiting circuit.

Parameter	Value
(W/L) M1–M2	18/3 μm/μm
(W/L) M3–M4, M13–M14	20/1 μm/μm
(W/L) M5–M6	6/1 μm/μm
(W/L) M7–M17, M8–M18	4/4, 20/4 μm/μm
(W/L) M9	4/0.6 μm/μm
(W/L) M10	1.32/4.13 μm/μm
(W/L) M11–M12	8/4 μm/μm
(W/L) M15–M16	18/1 μm/μm
(W/L) M19	1.32/1.36 μm/μm
(W/L) M20	4/1 μm/μm
C1, C2	214.74 fF

.

To assess the effectiveness of the proposed output-current-limiting circuit, two comparative analyses were conducted. The results are summarized in

Table 4. Output stage maximum current consumption results without the proposed current-limiting circuit.

Operating Conditions		IDM36 (mA)	IDM35 (mA)
VDD (V)	T (°C)
2	−55	17.64	24.92
2	25	15.2	19.15
2	135	13.02	14.71
2	175	12.42	13.58
5	−55	96.46	157.1
5	25	83.21	129
5	135	69.39	107
5	175	65.28	102

and

Table 5. Output stage maximum current consumption results with the proposed current-limiting circuit.

Operating Conditions		IDM36 (mA)	IDM35 (mA)
VDD (V)	T (°C)
2	−55	9.47	8.51
2	25	9.29	8.95
2	135	9.52	10.17
2	175	9.66	10.69
5	−55	10.32	9.58
5	25	10.01	10
5	135	10.16	11.26
5	175	10.28	11.82

, which present the current values flowing through each transistor of the class AB output stage, before and after the implementation of the limiting circuitry. The reported data were obtained through simulations performed under a supply voltage of 2 V and 5 V and temperature corner conditions (−55 °C, 25 °C, 125 °C, 175 °C) to evaluate robustness and performance.

A comparative analysis of the output stage current distribution indicates a consistent imbalance between the pMOS and nMOS transistors across the investigated operating conditions. The pMOS device conducts a higher current in all cases.

At V_DD = 2 V, the current difference between I_DM36 and I_DM35 ranges from 1.16 mA (at 175 °C) to 7.28 mA (at −55 °C), corresponding to a relative deviation between 9.3% and 41.3%, with respect to the nMOS current. The mismatch decreases as the temperature increases, indicating a partial thermal compensation effect at a lower supply voltage. In contrast, at V_DD = 5 V, the imbalance becomes significantly more pronounced. The absolute difference varies between 36.72 mA and 60.64 mA (at −55 °C), corresponding to a relative deviation of approximately 54–63%.

Following the implementation of the current-limiting circuit, the drain currents of M₃₅ and M₃₆ were stabilized within the ranges of 8.51–11.82 mA and 9.26–10.32 mA, respectively, across the entire analyzed temperature and power supply domain. These intervals correspond to an approximate current variation of ±16% around the mean value for the pMOS device and ±5% for the nMOS device.

To evaluate the statistical distribution of the maximum limited output current achieved by the proposed current-limiting circuit, 500-point Monte Carlo simulations [15] were performed at T = 25 °C, V_DD = 2 V and V_DD = 5 V, resulting in the histograms shown in Figure 4. This work adopts a ±6σ criterion (99.9999998% coverage), targeting high-reliability applications such as automotive and aerospace systems.

The ±6σ interval was intentionally adopted because the proposed current-limiting block is aimed at high-precision and high-reliability integration scenarios, especially those expected to maintain stable operation under significant process dispersion, mismatch effects, wide temperature excursions, and other severe operating conditions. In such applications, the design emphasis is placed on robustness, conservative statistical margins, and predictable behavior under worst-case variability, rather than solely on nominal performance. This reliability-oriented design philosophy is particularly relevant in demanding fields such as automotive and aerospace electronics, where stringent robustness requirements are typically imposed.

At V_DD = 2 V, both output-stage transistors exhibit near-Gaussian distributions [16]. For the nMOS device (Figure 4a), the mean current is μ ≃ 9.40 mA with σ ≃ 1.36 mA, corresponding to a 6σ interval of [1.25 mA, 17.55 mA]. For the pMOS device (Figure 4b), μ ≃ 9.02 mA and σ ≃ 0.915 mA, yielding a 6σ interval of [3.52 mA, 14.51 mA], indicating reduced dispersion compared to the nMOS case.

At V_DD = 5 V (Figure 4c,d), the distributions preserve their Gaussian shape and symmetry. The nMOS device exhibits μ ≃ 10.15 mA and σ ≃ 1.49 mA (6σ interval ≃ [1.21 mA, 19.08 mA]), while the pMOS device shows μ ≃ 10.07 mA and σ ≃ 1.02 mA (6σ interval ≃ [3.94 mA, 16.21 mA]).

In the proposed output-stage current-limiting circuit of the two-stage operational amplifier, the pMOS transistor exhibits a lower standard deviation than the nMOS transistor, indicating a reduced statistical spread of the corresponding current-limiting parameter. This observation suggests that the pMOS branch is less sensitive to local process-induced variations and mismatch effects in the investigated CMOS implementation. More specifically, the parameter distribution associated with the pMOS device remains more tightly clustered around its mean value, leading to the improved consistency of the limiting behavior under statistical analysis.

In general, the variability of MOS devices is governed by several physical mechanisms, including random dopant fluctuations, interface-related effects, carrier mobility variations, and other local technological nonuniformities introduced during fabrication. In the present case, these mechanisms appear to affect the nMOS device more strongly, resulting in a wider statistical distribution.

By contrast, the pMOS device exhibits a narrower distribution, which translates into a lower extracted standard deviation and, consequently, an improved parametric consistency [3].

Overall, the symmetric Gaussian profiles, single-mode distributions, and bounded standard deviations confirm robust and predictable output-stage behavior, with ±6σ compliance supporting high-reliability operation [17].

Corner simulations were performed over temperature for the three main process conditions (Typical, Slow, and Fast) to characterize the temperature dependence of the limited output current.

The maximum output current was extracted for both operating modes of the class-AB output stage: sinking and sourcing, corresponding to the dominant conduction of the nMOS and pMOS output devices, respectively. The results are illustrated in Figure 5a,b, showing the spread of the current clamp across PVT and confirming a bounded, well-defined limiting behavior over the full temperature range.

The trends in Figure 5a,b are consistent with the numerical results in Table 3. The limited sinking current through the nMOS output device (I_DM36) shows only a small temperature dependence, while the sourcing current through the pMOS device (I_DM35) increases more noticeably with the temperature for both V_DD = 2 V and V_DD = 5 V, confirming a bounded and well-defined current clamp across the operating conditions.

In order to further assess the dynamic stability of the proposed current-limiting loop, a dedicated transient simulation was carried out to explicitly capture the transition from nominal output-stage operation to the current-limited regime. This analysis is particularly relevant for verifying that the activation of the limiter does not induce undesired oscillatory behavior at the output. As evidenced by the waveforms presented below in Figure 6a,b, the transition remains well-controlled, exhibiting only a brief transient excursion before reaching a stable limited-current condition, with no sustained ringing or instability.

At the beginning of the transient, when INN = INP, the differential input stage is in a balanced condition and therefore does not strongly favor either branch of the output stage. As a result, the output is not yet driven toward a well-defined logic state, and V_OUT settles temporarily at an intermediate level determined by the internal offset, bias conditions, and the external loading applied in the testbench.

When INN > INP, the internal control of the operational amplifier enables the nMOS pull-down branch of the output stage, thereby establishing the condition required to discharge the output node and drive V_OUT toward the low logic level. Under nominal operation, as the output voltage approaches the ground, the drain-to-source voltage of the pull-down transistor progressively decreases, which inherently reduces its conduction capability. Consequently, although the device remains electrically enabled by the internal control path, the current that it can sustain in a steady state becomes negligible once the output node settles near the source potential.

A proper assessment of the maximum sink-current condition, however, cannot be performed in this nominal regime, since the output transistor is no longer subjected to significant voltage stress. Instead, the relevant verification condition arises when the internal state of the amplifier still commands a low output level (INN > INP), while the output node is maintained externally at a high potential, close to V_DD. Such a condition is of practical interest, as the amplifier output may interact with external loads or surrounding circuitry that are capable of temporarily opposing the internally established switching state.

Under these circumstances, the pull-down nMOS remains activated by the internal control loop while the drain node is held near the positive supply rail. The device is therefore simultaneously exposed to a large gate-to-source voltage and a large drain-to-source voltage, which corresponds to the most severe operating condition from the standpoint of current sinking. In the absence of any dedicated protection mechanism, this state would allow the output transistor to conduct an excessive current, limited primarily by its intrinsic transconductance and by the external electrical constraints.

For this reason, this operating condition constitutes the appropriate framework for validating the proposed current-limiting function. Even when the nMOS pull-down device is commanded into conduction and the output node is externally constrained near V_DD, the protection loop prevents an uncontrolled current increase by regulating node NG, thereby reducing the effective overdrive applied to the output transistor. As a result, the sink current is no longer determined by the unrestricted drive capability of the pull-down branch, but is instead confined to a well-defined maximum value imposed by the limiting circuitry.

The waveforms provide a direct validation of the operating principle discussed above. The upper plot shows the differential input excitation, the middle plot the corresponding output response V_OUT, and the lower plot the current associated with the output node. When INN < INP, the amplifier drives the output toward the high state, and V_OUT settles accordingly, with only a small steady-state output current. A more relevant situation for current-limit verification is observed when INN > INP, when the internal logic activates the nMOS pull-down branch, while V_OUT is nevertheless maintained near V_DD by the external test condition. In this interval, the output nMOS remains enabled under simultaneously large V_GS and V_DS, which corresponds to the critical sink-current condition. The bottom waveform shows that, after a short transient peak, the output current does not increase uncontrollably, but settles into a well-defined plateau of a few milliamperes, which directly confirms the action of the current-limiting loop through node NG. A complementary behavior is observed in the subsequent interval, where the output node is constrained against the internally commanded state in the opposite direction, producing a current plateau of the opposite sign. Therefore, the waveforms demonstrate that, under externally imposed output conflict conditions, the output-stage current is effectively limited, rather than being determined solely by the intrinsic strength of the final transistors.

4. Layout Implementation

This section presents the layout implementation of the proposed output current-limiting block, illustrated in Figure 7, and discusses the main layout design considerations adopted to ensure correct circuit operation and robustness against parasitic effects. Particular attention was given to device placement, routing symmetry [18,19], and compliance with the technology design rules in order to preserve the behavior predicted at a schematic level.

The layout was implemented with a clear separation between nMOS and pMOS devices to reduce unwanted coupling [20] and to enable a more controlled routing of critical nodes. The native nMOS and pMOS transistors are located on the right-hand side of the layout. Compared to standard 5 V devices, these native transistors are subject to additional design-rule constraints: most notably, the requirement that their associated DNWELL regions must be kept at a minimum distance of 2 μm from any other DNWELL region.

The native devices were clustered according to their bulk connection potential, such that transistors sharing the same well/substrate bias were placed within the same isolation region. Dedicated guard rings and well/substrate taps were implemented for each group, following the PDK recommendations, and the minimum spacing requirements between P+ and N+ doped regions were satisfied. This approach ensures proper bulk biasing, reduces substrate noise sensitivity, and improves latch-up robustness.

The MOM capacitors C₁ and C₂, located at the top of the layout, are used to compensate the internal feedback loop. For current mirrors and cascode devices, matching was enhanced through symmetry and a balanced placement strategy, aiming to minimize the impact of the process and temperature gradients. Additionally, the symmetry and equalization of the routing lengths of critical interconnects were considered in order to achieve a balanced electrical response.

Interconnect routing was performed mainly on metal 3 and metal 4, taking advantage of their lower sheet resistance and reduced parasitic capacitances compared to lower metal layers. The estimated active area of the block is approximately 0.003 mm², making it suitable for integration into complex systems in which improved energy efficiency is required.

The proposed layout implementation was validated through full design-rule checking (DRC) and layout-versus-schematic (LVS) verification, confirming compliance with the technology constraints and schematic consistency. Furthermore, post-layout extraction (PEX) was performed in order to accurately capture interconnect and device parasitics, enabling a realistic evaluation of circuit performance under post-layout conditions. The results obtained from the PEX analysis are summarized in

Table 6. Post-layout (PEX) simulation results.

Operating Conditions		IDM36 (mA)			IDM35 (mA)
		Corner			Corner
VDD (V)	T (°C)	SS	Typ	FF	SS	Typ	FF
2	−55	11.78	9.84	7.57	10.58	8.95	7.64
2	25	10.77	9.54	8.02	10.51	9.40	9.01
2	135	9.29	9.65	9.01	11.05	10.51	10.85
2	175	8.76	9.78	9.72	10.24	11.15	11.82
5	−55	12.54	10.70	8.56	11.76	10.07	8.76
5	25	11.52	10.27	8.92	11.61	10.49	10.22
5	135	11.03	10.29	9.87	12.15	11.63	12.20
5	175	10.94	10.40	10.59	12.59	12.34	13.27

.

Post-layout simulations were carried out by performing RCC parasitic extraction exclusively on the proposed current-limiting block, while the operational amplifier remained at the schematic level.

A comparison between schematic-level and post-layout (Typical corner) results indicates a minor increase in the limited output current after parasitic extraction. Across the entire temperature range (−55 °C to 175 °C) and for both supply voltages (2 V and 5 V), the deviation between schematic and PEX Typical results remains below 5%, with a maximum absolute difference of approximately 0.5 mA.

The temperature-dependent evolution of the limited current remains consistent after parasitic extraction, with no significant modification of the overall variation profile. Furthermore, the current symmetry between the pull-up and pull-down devices is maintained, confirming that the inclusion of layout-induced resistive and capacitive parasitics does not significantly alter the current-limiting behavior.

5. Conclusions

This paper presented a replica-based bidirectional output current-limiting architecture intended to provide deterministic overcurrent protection in CMOS class-AB output stages. The proposed approach establishes a well-defined current clamp for both sinking and sourcing operation, independent of load impedance and robustness, with respect to process–voltage–temperature (PVT) variations. In contrast to the implicit current constraints resulting from device sizing or parasitic resistances, the proposed solution enables the controlled and reproducible limitation of the output-stage current through an explicit sensing and feedback mechanism.

The simulation results indicate a substantial reduction in excessive current levels under overload conditions. In the absence of the limiting mechanism, the output-stage current may exceed 100 mA at a 5 V supply. When the proposed architecture is employed, both pull-down and pull-up currents are constrained within a relatively narrow interval of approximately 9–12 mA across the entire temperature range from −55 °C to 175 °C. Process-corner simulations further confirm bounded variations across the SS, Typical, and FF conditions, while a 500-point Monte Carlo analysis reveals single-mode Gaussian distributions with controlled dispersion, supporting the ±6σ reliability targets that are typically required in safety-critical electronic systems.

Post-layout simulations based on RCC parasitic extraction show less than 5% deviation from schematic-level results, indicating that layout-induced parasitic effects have a limited impact on the current-limiting behavior and that the defined current clamp is preserved after physical implementation.

Overall, the obtained results demonstrate that the proposed architecture represents a compact and robust solution for output-stage current limitation in CMOS analog circuits. By ensuring controlled current levels under overload conditions while maintaining a negligible impact on nominal circuit operation, the presented approach is well-suited for reliability-critical applications operating over extended temperature ranges, including automotive and aerospace electronic systems.