Search Results (246)

As the deep integration of the Internet of Things (IoT) and artificial intelligence (AI) technologies has rendered traditional encryption techniques increasingly inadequate in terms of security strength, the implementation of hardware-level security solutions has been identified as a critical issue in the design of information systems. Memristors, as passive circuit components with their intrinsic stochastic switching behavior, multistate storage capability, and low power consumption, have been exploited to provide a viable approach for the construction of hardware security primitives, including true random number generators (TRNGs) and physically unclonable functions (PUFs). In this review, the latest research advances in memristor-based hardware security technologies were systematically surveyed from three perspectives, namely TRNGs, PUFs and other security schemes. With regard to TRNGs and PUFs, respectively, we have systematically summarized their characteristics, including throughput, power consumption and randomness quality, as well as uniqueness, reliability and methods, with particular attention paid to the types of entropy sources and bit-generation strategies. In addition, the potential application of other memristor-based hardware security solutions in information hiding, encrypted transmission and authentication was also analyzed. Subsequently, the principal challenges impeding the transition from laboratory research to mass production were summarized, encompassing synergistic integration with advanced CMOS processes, the balance between reliability and stochasticity, and the absence of design methodologies that integrate hardware and software. Future development trajectories were further delineated, including cross-layer optimization across devices, circuits, and systems, the design of high-security chips resistant to machine learning attacks, CMOS-compatible stable implementation schemes, and the on-chip integration of TRNGs, PUFs, and encryption engines. The present review is intended to serve as a systematic reference for the design of novel hardware security systems, thereby paving the way for the practical deployment of memristor-based security technologies. Full article

Resistive random-access memory (RRAM) has emerged as one of the most promising device platforms for neuromorphic, in-memory computing because its two-terminal metal–insulator–metal (MIM) structure can reproduce the weight-update behavior of biological synapses while remaining compatible with mainstream CMOS processing. This review summarizes the current state of RRAM-based neuromorphic technology from four complementary perspectives: device physics, materials, fabrication processes, and packaging. We first describe the operating principles of filamentary and interface-type RRAM, including the forming/set/reset switching sequence, and the two dominant analytical frameworks used to describe the reset transition—the ion-migration model and the thermally driven filament-dissolution model. We then review the switching-layer and electrode materials that have been most widely investigated such as HfO_x, TiO_x, TaO_x, ZnO, ZrO₂, and Cu/Ag-based conductive-bridge systems, together with representative bilayer and doped architectures reported for synaptic devices. The biological functions that RRAM can emulate are discussed alongside the non-ideal characteristics that currently limit on-chip training accuracy, with emphasis on separating device-to-device from cycle-to-cycle variability and on the workload-dependent nature of endurance and retention requirements. We further summarize the process technologies used to integrate RRAM into large-scale, CMOS-compatible arrays, including atomic layer deposition, interfacial oxygen-reservoir engineering, low-thermal-budget back-end-of-line integration, and three-dimensional vertical RRAM patterning, and discuss the advanced packaging strategies such as 2.5D/3D heterogeneous integration, chiplet architectures, thermal-interface materials, and nanostructured underfills required to manage the power density and interconnect demands of large synaptic arrays, distinguishing solutions that have been demonstrated specifically for RRAM neuromorphic arrays from those that remain general advanced-packaging concepts. Finally, RRAM is benchmarked against competing emerging non-volatile memories, and the key research directions such as three-terminal memtransistor architectures, three-dimensional integration with high-performance selectors, and hardware–algorithm co-design that will determine whether RRAM-based neuromorphic hardware can move from laboratory demonstrations to on-device AI, autonomous systems, and large-scale artificial-neural-network accelerators are outlined. Relative to prior reviews that focus primarily on RRAM device physics or on switching-layer materials in isolation, the distinctive contribution of this review is an explicit, cross-layer synthesis that connects device-level non-idealities to their consequences for wafer-scale process integration and for advanced 2.5D/3D packaging—a combination that, to our knowledge, has not been jointly treated in the recent review literature on RRAM-based neuromorphic hardware. Full article

A complementary metal oxide semiconductor (CMOS)-compatible z-axis magnetic field sensor incorporating an additional collector is proposed to enhance magnetic sensing performance. The sensor consists of four identical magnetic sensing elements arranged in a cross-shaped configuration, while shallow trench isolation (STI) and a post-CMOS cavity structure are employed to suppress substrate leakage current and improve electrical isolation. The sensing characteristics were investigated using three-dimensional TCAD simulations to analyze carrier transport and current density distributions under different magnetic fields. The simulation results confirmed that the structure effectively enhances the differential output response and magnetic sensitivity. The device was fabricated using a commercial CMOS process followed by a simple post-CMOS micromachining process. Optical microscope and scanning electron microscope observations verified the successful formation of the sensing structure and the cavity beneath the sensing elements. The sensor was experimentally characterized under magnetic fields ranging from −300 to 300 mT. The measured results exhibited excellent linearity over the entire measurement range. The sensor achieved a measured sensitivity of 120 mV/T. Owing to its high sensitivity, simple fabrication process, and full compatibility with standard CMOS technology, the magnetic field sensor is promising for integrated microsystems, industrial monitoring, and intelligent sensing applications. Full article

Micromachined ultrasonic transducers (MUTs) represent a notable advance in miniaturized sensing, enabling compact, low-power, and complementary metal-oxide-semiconductor (CMOS)-integrated platforms that extend ultrasonic capabilities into wearable, implantable, and edge-computing domains. The integration of artificial intelligence (AI) has introduced new approaches for signal interpretation, adaptive control, and data-driven optimization, enhancing performance in specific areas such as compressed sensing, neural beamforming, and learned image enhancement that complement conventional signal processing. Meanwhile, sensor fusion strategies that combine ultrasonic data with complementary modalities have improved robustness, contextual awareness, and diagnostic accuracy across applications ranging from industrial monitoring to clinical diagnostics. This review provides a comprehensive analysis of this active research area, systematically covering transducer hardware platforms, design methodologies, and intelligent signal processing frameworks. While traditional bulk piezoelectric transducers remain the benchmark for high-power applications, capacitive and piezoelectric micromachined variants offer superior acoustic impedance matching and monolithic CMOS compatibility essential for portable systems. We examine the evolution from deterministic analytical and numerical modeling toward AI-powered inverse design, which enables the discovery of non-intuitive, high-performance geometries beyond human intuition. Furthermore, the integration of machine learning (ML) for signal recovery, image enhancement, and multi-modal sensor fusion is discussed as a pathway to compensate for hardware constraints such as limited aperture, sparse sampling, and low signal-to-noise ratio (SNR), while pointing out that AI technology cannot overcome fundamental physical limits including acoustic attenuation, thermal noise floors, and transduction efficiency boundaries. By synthesizing recent advancements, this review demonstrates how the convergence of classical acoustic physics and data-driven intelligence is guiding the development of of intelligent ultrasonic systems. Full article

Data movement has become a dominant bottleneck in modern artificial intelligence hardware, making in-memory computing a critical direction for energy-efficient and memory-centric architectures. Ferroelectric hafnium oxide provides a distinctive materials platform for this transition because field-driven polarization switching, non-volatility, CMOS compatibility, and nanoscale thickness scalability can be combined within a process-relevant oxide system. This review establishes a device-to-system perspective on HfO₂-based and Hf_0.5Zr_0.5O₂-based ferroelectric memories for in-memory computing. Instead of treating ferroelectric materials, memory devices, circuit primitives, and computing architectures as separate research topics, we examine how their mutual constraints define the achievable efficiency, precision, reliability, and scalability of hafnia-based computing systems. The discussion connects polarization engineering and defect control with charge-domain computation, threshold-state logic, associative search, analog weight representation, neuromorphic plasticity, and sensor-side processing. Particular emphasis is placed on the translation of ferroelectric functionality from individual devices to arrays, macros, and system-level accelerators. We identify variability, fatigue, charge trapping, multilevel-state uncertainty, peripheral overhead, and benchmarking inconsistency as the central barriers that prevent device-level advantages from directly becoming system-level gains. Finally, we outline a cross-layer roadmap in which ferroelectric stack engineering, variability-tolerant arrays, precision-scalable architectures, and SoC-level integration are co-optimized to enable reliable HZO-based memory-centric computing. Full article

This article reviews the reactive magnetron sputtering of piezoelectric Aluminium Nitride (AlN) thin films, with a focus on process parameter optimisation and system-level deposition challenges. AlN is a leading material for MEMS and RF applications owing to its c-axis (002) orientation, high acoustic velocity, wide bandgap (∼6.2 eV), and CMOS compatibility. We review the influence of sputtering power, nitrogen flow ratio, substrate temperature, and target-to-substrate distance on crystallographic quality and document practical hardware challenges, including vacuum leakage, grounding faults, target erosion, and mass flow controller drift, that critically affect reproducibility but are systematically underreported in the literature. A perspective is provided on emerging application domains where optimised AlN films address current performance gaps, including next-generation RF/telecom systems towards 6G and Future Networks, harsh environment sensing and actuation, biomedical ultrasound, and IoT energy harvesting. The complementarity between AlN and Silicon Carbide (SiC) is discussed for high-temperature, high-power, and radiation-hard MEMS, where AlN/SiC heterostructures combine the piezoelectric activity of AlN with the mechanical and chemical robustness of SiC. It also incorporates a discussion of dopant- and heteroepitaxy-based AlN engineering, AlN deposition on a wider range of substrates, the role of seed and electrode underlayers, and pulsed-DC sputtering as a third power supply mode alongside RF and conventional DC. Full article

We report a CMOS-compatible ferroelectric memristor based on a TiN/AlScN/n⁺ Si metal ferroelectric semiconductor (MFS) structure, fabricated entirely via low-temperature sputtering processes. The ultrathin AlScN film exhibits robust ferroelectricity with a high remanent polarization (2P_r ≈ 80.91 μC/cm²) and excellent endurance over 10⁵ cycles, while maintaining uniform switching across cells. Notably, the use of a heavily doped silicon bottom electrode enables full compatibility with conventional back-end-of-line (BEOL) CMOS processes and facilitates integration with silicon-based circuits. Beyond stable memory performance, the device demonstrates volatile short-term memory (STM) behavior originating from depolarization field-induced polarization relaxation, which is essential for neuromorphic dynamics. Leveraging this STM feature, the device was implemented as a physical reservoir in a reservoir computing (RC) framework, achieving 97.64% classification accuracy on the MNIST dataset using temporally coded inputs. These results highlight the potential of AlScN-based ferroelectric memristors as dynamic CMOS-compatible building blocks for in-memory and neuromorphic computing. Full article

Hall-effect sensors are pervasive in magnetic-field measurement applications, including current sensing and position detection, owing to their excellent compatibility with standard CMOS processes. However, the inherent offset and temperature drift of silicon-based Hall elements remain a paramount obstacle to achieve high precision. This paper presents a fully integrated angle sensor chip that addresses this challenge. Implemented in a 0.35 μm CMOS process, the sensor incorporates four cross-shaped Hall elements arranged in an orthogonal array as a non-contact Hall-permanent magnet configuration, which enables absolute angular encoding across a full 0–360° range. Experimental characterisation demonstrates a low noise floor of 0.087° (3σ), validating the effectiveness of the proposed architecture for high-accuracy angular measurement. Full article

Magnetoresistive random-access memory (MRAM), as a promising non-volatile memory technology, has attracted extensive research interest owing to its unique combination of high operating speed, exceptional endurance, low standby power consumption, and CMOS process compatibility. In this review, we provide a comprehensive overview of the technological evolution of MRAM, spanning from Toggle-MRAM to spin-transfer torque (STT)-MRAM and then to spin–orbit torque (SOT)-MRAM. The working mechanisms, performance trade-offs, and integration potential of each generation are systematically summarized. Furthermore, the diverse applications of MRAM—including embedded systems-on-chip (SoCs), edge computing, aerospace and automotive electronics, artificial intelligence accelerators, neuromorphic computing, and hardware-level security—are thoroughly discussed. We also identify key challenges hindering large-scale commercialization, such as the trade-off between write energy and speed, process complexity, storage density constraints, and cost competitiveness. Finally, emerging research directions are proposed, emphasizing short-term priorities such as write current reduction and yield improvement, as well as long-term development strategies focusing on material–device–algorithm co-optimization and ecosystem establishment. Full article

Combinatorial optimization problems (COPs) are challenging for conventional computers because their solution spaces grow exponentially. To reduce exhaustive-search burden, hardware approaches have explored stochastic traversal of energy landscapes, including quantum annealers, CMOS Ising solvers, and probabilistic computing systems. However, quantum annealers require cryogenic operation, while CMOS Ising solvers typically rely on pseudorandom bitstreams or shared random pulses. A CMOS-compatible probabilistic bit with a physical random source is attractive for scalable optimization hardware. We present a CMOS p-bit that generates stochastic states from transistor device noise. The p-bit combines a transistor-noise random source, a correlated double sampling circuit, a calibrated comparator, and a 5-bit probability controller to convert local-field inputs into digitally tunable output probabilities. Because the random source is local to each p-bit and does not require PRNG state or seed assignment, the local random-source circuit in each p-bit does not need to grow larger as the number of p-bits increases, while system-level scaling is still governed by the p-bit count, weighted-sum logic, and interconnects. Prototype p-bit chips fabricated in a 180 nm CMOS process show 32-level output-probability control, pass the NIST Statistical Test Suite, and achieve 50 MHz updates with 6.95 pJ/bit at 50% output probability under a 1.8 V supply. Interfaced with FPGA-based weighted-sum logic, the prototype probabilistic circuit demonstrates invertible Boolean operation using a clamped gate network and performs integer factorization. Full article

The field of infrared (IR) photodetection is undergoing rapid development through the emergence of solution-processable nanoparticle (NP)-based materials and fabrication strategies. This review critically examines recent advances in fabrication approaches for NP-based IR detectors, emphasizing the relationship between synthesis, surface engineering, deposition processes, and device architecture in determining detector performance. Representative material platforms are discussed, including colloidal quantum dots (CQDs) such as PbS and HgTe, which enable tunable operation from the near-infrared (NIR) and short-wave infrared (SWIR) to selected mid-wave (MWIR), long-wave (LWIR), and emerging very-long-wave infrared (VLWIR) regimes depending on material composition and operating conditions. Further platforms including plasmonic metal NPs, black phosphorus, and topological nanomaterials are evaluated for their unique mechanisms of optical enhancement and broadband response. Fabrication approaches including continuous-flow synthesis, ligand exchange, blade coating, inkjet printing, electrophoretic deposition, and other scalable solution-processing methods are analyzed with respect to their influence on film quality, charge transport, interface engineering, and integration compatibility. The review further compares major device architectures, including photoconductors, photodiodes, plasmonic absorbers, and phototransistors, using key performance metrics such as specific detectivity (D*), responsivity (R), response speed, and operating temperature, while emphasizing the importance of measurement conditions in cross-platform comparisons. Critical challenges including dark-current generation, 1/f noise, transport limitations associated with ligand chemistry, environmental instability of narrow-bandgap materials, manufacturability constraints, and toxicity considerations are also discussed. Emerging directions such as neuromorphic sensing, CMOS-compatible integration, and sustainable lead-free nanomaterials are highlighted. By linking nanoscale material design and fabrication processes to device-level performance, this review provides a framework for advancing NP-based IR technologies toward scalable and application-relevant sensing systems. Full article

A dual-mode variable gain amplifier (VGA) with a wide-dynamic-range is proposed in this paper. The VGA is designed in a 0.18 μm CMOS process, and it has a body-driven variable load cell and binary gain array structure to implement both the digitally stepped programmable gain amplifier (PGA) mode and the analog-controlled VGA mode. This design removes additional digital conversion modules when integrated into an automatic gain control (AGC) loop, which simplifies the whole system architecture significantly. The design is also able to address several limitations of conventional VGAs, such as a single control mode, low AGC compatibility, and a narrow gain range. The simulation results after post-layout indicate that at PGA mode, the design has an ultra-wide gain band of −0.03 to 126.9 dB with a constant gain step of 1 dB. And in VGA mode, it allows smooth, continuous gain adjustment over a large range of −25.3 dB to 187.4 dB. The bandwidth of −3 dB is more than 45 MHz in both modes. The whole VGA uses 1.026 mW and has a core size of 0.011 mm². The output 1-dB compression point (OP1dB) was −1.57 dBm at minimum gain in the PGA mode and −4.02 dBm in the VGA mode. Besides, PVT analysis, Monte Carlo simulations and AGC system-level verification are evident enough to prove that the suggested VGA has high immunity to PVT (Process, Voltage, Temperature) variations, stable processes and high practicality in engineering applications. Full article

With the continuous advancement of display technology and advanced integrated circuits, oxide thin-film transistors (TFTs) have become core devices due to their high mobility, low leakage current and excellent large-area uniformity. To achieve low power consumption, high performance and high reliability, the introduction of high-k gate insulating layers is crucial. Among the numerous high-k materials, hafnium oxide (HfO₂) has attracted significant attention due to its excellent dielectric properties and good compatibility with CMOS processes. In this paper, uniform and dense HfO₂ films were successfully fabricated using the sol–gel method to serve as insulating layers for TFT devices. Through experimental analysis, 400 °C was determined to be the optimal annealing temperature. At this temperature, the effects of replacing SiO₂ with HfO₂ as the insulating layer, as well as the impact of reducing film thickness, on TFT devices were investigated. Ultimately, at an annealing temperature of 400 °C, an 85 nm-thick HfO₂ film achieved the highest on/off current ratio (I_on/off = 1.11 × 10⁶), the lowest subthreshold swing (SS = 0.53 V/dec), the lowest threshold voltage (Vth = −1.1 V) and the lowest off-current ratio (I_off = 2.5 × 10⁻¹² A). It was confirmed that replacing SiO₂ with HfO₂ as the insulating layer is a viable approach for reducing the volume of TFT devices. Full article

Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm² are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing. Full article

This article examines hazardous ground irregularities that remain undetectable by the white cane used by visually impaired individuals. Additionally, the development of a multi-beam laser ranging system is described. Integrated into the cane handle, this system is designed to provide comprehensive ground awareness and sufficient anticipation at a walking speed of 1 m/s. The system employs a near-infrared multi-beam laser sensor with a holographic grating generating four diamond-shaped beams, in conjunction with a high-resolution CMOS sensor. Through optical triangulation and real-time processing, the device estimates the height of obstacles or drop-offs relative to the walking surface. Vibrotactile feedback informs the user of detected hazards, with distinct vibration patterns differentiating between elevation changes and drop-offs. Preliminary trials with blind participants in controlled environments demonstrate that the system is feasible, responsive, energy-efficient, and fully compatible with conventional white cane use. Full article