Search Results (68)

With the rapid advancement of silicon carbide technology, device reliability has emerged as a critical concern for high-performance power electronics applications. Among various reliability challenges, the limited short-circuit withstand time (SCWT) of SiC MOSFETs, coupled with significant device-to-device variation, poses a serious risk, as it can lead to catastrophic field failures. In addition, established short-circuit screening technique utilizes high-voltage and high-stress condition that may degrade the long-term reliability of otherwise good devices. Hence, this work proposes a novel short-circuit screening methodology employing lower voltages and verifies it using commercial 1.2 kV 4H-SiC MOSFETs. The proposed approach can remove devices with lower SCWT while minimizing electrical and thermal overstress during screening. The results indicate that the proposed low-voltage screening technique offers a safe, repeatable, and reliable alternative to conventional short-circuit screening method, making it well suited for practical manufacturing, leading to system-level reliability enhancement in SiC-based power electronics applications. Full article

Silicon carbide (SiC) MOSFETs, as one of the representative power electronic devices, have faced reliability challenges due to threshold voltage (V_th) instability under dynamic gate stress. To explore the underlying mechanisms, this work investigates 4H-SiC MOS structures (P-MOS and N-MOS) under AC bias temperature instability (AC BTI) stress, utilizing a laser to generate minority carriers and simulate realistic switching conditions. Through combined capacitance–voltage (C-V) and gate current–voltage (J_g-V_g) characterizations on P-MOS and N-MOS devices before and after degradation at different temperatures, we reveal a critical temperature dependence in defect interactions. At room temperature, degradation is dominated by electron trapping in shallow interface states and near-interface traps (NITs). In contrast, high-temperature stress activates charge exchange with deep-level, slow states. Notably, a positive V_FB shift is consistently observed in both N-MOS and P-MOS devices under AC stress, confirming that electron trapping is the dominant cause of the commonly observed positive V_th shift in SiC MOSFETs. These findings clarify the distinct defect-mediated mechanisms governing dynamic V_th instability in SiC devices, providing fundamental insights for interface engineering and reliability assessment. Full article

Bidirectional switches are highly required power electronics units for the design of power converters, especially for direct matrix converters. This article presents the design and implementation of a compact bidirectional switch based on SiC-MOSFET technology, aimed at high-efficiency, high-density power electronics applications. The proposed architecture employs surface-mount components, optimizing both the occupied area and electrical performance. The selected switching device is the IMBG120R053M2H from Infineon, a SiC-MOSFET known for its low on-resistance, high reverse-voltage blocking capability, and excellent switching speed. To drive the power devices, the UCC21521 gate driver integrates two independent isolated outputs in a single package, enabling precise control and reduced electromagnetic interference (EMI). The developed design supports bidirectional current conduction and voltage blocking, offering a robust and scalable solution for next-generation power converters. Design criteria, simulation results, and experimental validations are discussed. Full article

This work presents a highly compact and scalable 1.2-kV SiC MOSFET half-bridge building-block module enabled by a die-integrated 3D PCB packaging technology. Compared with conventional DBC-based or TO-247-based SiC half-bridge modules, the proposed design reduces the physical volume and weight by more than 90% while maintaining full compatibility with standard PCB manufacturing processes. The vertically laminated DC+/DC− conductors and symmetric PCB–die–PCB stack establish a tightly confined commutation loop, resulting in a measured power-loop inductance of 2.2 nH and a 3.8 nH gate-loop inductance—representing up to 94% and 89% reduction relative to discrete device implementations. Because the parasitic parameters are intrinsically well-balanced across replicated units and the mutual inductance between adjacent modules remains extremely small, the structure naturally supports current sharing during parallel operation. Thermal and insulation evaluations further confirm the suitability of copper filling via high-Tg laminated PCB substrates for high-power SiC applications, achieving withstand voltages exceeding twice the rated bus voltage. The proposed module is experimentally validated through finite-element parasitic extraction and 950 V double-pulse testing, demonstrating controlled dv/dt behavior and robust switching performance. This work establishes a manufacturable and parallel-friendly packaging approach for high-density SiC power conversion systems. Full article

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work. Full article

This work investigates bias-temperature instability (BTI) in 1700 V 4H-SiC MOSFETs under realistic 1 MHz switching conditions with simultaneous gate and drain stress. Threshold-voltage measurements reveal that the degradation does not follow the classical Reaction–Diffusion behavior typically assumed for silicon devices. Instead, the power-law exponent n shows a clear increase at the largest negative gate bias (−10 V), indicating a field-driven trap-generation mechanism. Temperature-dependent stress tests further show a negative activation energy (−0.466 eV), consistent with degradation accelerating at lower temperatures due to suppressed detrapping. The results demonstrate that conventional silicon BTI models cannot be directly applied to SiC technologies and that fixed-n lifetime extrapolation leads to significant errors. A bias-dependent, field-driven framework for estimating time-to-failure is proposed, offering more accurate and practical reliability prediction for high-power SiC converter applications. Full article

Silicon carbide (SiC) MOSFETs with voltage ratings above 3.3 kV are emerging as key enablers for next-generation medium-voltage (MV) power conversion systems, offering superior blocking capabilities, faster switching speeds, and an improved thermal performance compared to conventional silicon IGBTs. However, the practical deployment of 10 kV SiC devices remains constrained by the immaturity of high-voltage chip and packaging technologies. Current development is often limited to engineering samples provided by a few suppliers and custom packaging solutions evaluated only in laboratory settings. To advance the commercialization of 10 kV SiC power modules, this paper presents the design and characterization of a 10 kV, 60 A half-bridge module employing the XHP housing and newly developed SiC MOSFET chips from China Electronics Technology Group Corporation (CETC). Electro-thermal simulations based on a finite element analysis were conducted to extract key performance parameters, with a measured parasitic inductance of 24 nH and a thermal resistance of 0.0948 K/W. To further validate the packaging concept, a double-pulse test platform was implemented. The dynamic switching behavior of the module was experimentally verified under a 6 kV DC-link voltage, demonstrating the feasibility competitiveness of this approach and paving the way for the industrial adoption of 10 kV SiC technology in MV applications. Full article

This article presents a method for detecting the temperature distribution of two parallelized Silicon Carbide (SiC) MOSFETs. Two thermally sensitive electrical parameters (TSEPs), namely the on-state resistance ($R_{dson}$) and the threshold voltage ($V_{th}$), are introduced. A comparison of the temperatures interpolated by $V_{th}$ and $R_{dson}$ shows disparity, enabling the detection of individual junction temperatures. $V_{th}$ instability and its measurement are discussed for SiC devices. Experimental results show that, depending on the instability of the $V_{th}$ and the sensitivity of the two TSEPs at certain temperatures, a combination of different TSEPs could be a solution for extracting the maximum junction temperature of parallelized devices. Full article

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics. Full article

This study investigates the degradation mechanisms of 1200 V SiC MOSFETs during High-temperature Reverse Bias (HTRB) reliability testing, focusing on breakdown voltage (BV) reduction. Experimental results reveal that trapped charges at the SiC/SiO₂ interface in the termination region alter electric field distribution, leading to premature breakdown. To address this issue, an optimized termination structure is proposed, incorporating reduced spacing between adjacent field rings and additional outer rings. TCAD simulations and experimental validation demonstrate that the improved design stabilizes BV within 2% deviation during 1000 h HTRB testing, which significantly enhances termination robustness. Full article

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article

In this study, we propose an optimized shield gate trench 4H-SiC structure with effective gate oxide protection. The proposed device has a split trench with a P+ shield region, and the P+ shield is grounded by the middle deep trench. Our simulation results show that the peak electric field near the gate oxide is almost completely suppressed. Compared with a conventional P+ shield device, our proposed structure achieves a 78% reduction in the Q_gd and a 108% increase in the FoM (figure of merit) simultaneously. Additionally, it is estimated that the device cell pitch can be reduced to 1.8 μm with a R_on below 0.94 mΩ·cm², in theory. These demonstrated device performance metrics, as well as its simple structure and good compatibility, make our proposed SiC MOSFET highly attractive for future high-performance applications. Full article

This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation. Full article

This work introduces a novel temperature-triggered threshold voltage shift (T3VS) method to study the energy-dependent $D_{it}$ distribution close to the conduction band edge in commercial 1.2 kV 4H-SiC MOSFETs with planar and trench gate structures. Traditional $D_{it}$ extraction methodologies are complicated and require sophisticated instrumentation, complex analysis, and/or prior information related to the device design and fabrication, which is generally unavailable to the consumers of commercial devices. This methodology merely utilizes the transfer characteristics of the device and is straightforward to implement. The $D_{it}$ analysis using the T3VS method shows that trench devices have significantly lower $D_{it}$ in comparison to the planar devices, making them more reliable and efficient in practical applications. Furthermore, this study examines the impact of a novel room temperature gate oxide screening methodology called screening with adjustment pulse (SWAP) on the $D_{it}$ distribution in commercial planar MOSFETs, utilizing the proposed T3VS method. The result demonstrates that the SWAP technique is aggressive in nature and can introduce new defect states close to the conduction band edge. Hence, additional care is needed during screening optimization to ensure the reliability and usability of the screened devices in the consequent applications. Full article

A 4H-silicon carbide (SiC) trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) with dual integrated Schottky barrier diodes (SBDs) was characterized using numerical simulations. The advantage of three-dimensional stacked integration is that it allows the proposed structure to obtain an electric field of below 0.6 MV/cm in the gate oxide and SBD contacts and achieve ~10% lower forward voltage of SBDs than the planar gate SBD-integrated MOSFET (PSI-MOS) and the trench gate structure with three p-type-protecting layers (TPL-MOS). The dual-SBD-integrated MOSFET (DSI-MOS) also highlights the better influences of the more than 70% reduction in the miller charge, as well as the over 50% reduction in switching loss compared to the others. Furthermore, the short-circuit (SC) robustness of the three devices was identified. The DSI-MOS attains the critical energy and the aluminum melting point in a longer SC time interval than the TPL-MOS. The p-shield layers in the DSI-MOS are demonstrated to yield the huge benefit of improving the reliability of the contacts when SC reliability is considered. Full article