Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs

Abstract

This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.

1. Introduction

Silicon carbide (SiC) is a wide-bandgap material gaining widespread traction in industrial and power applications due to its high critical electric field, thermal conductivity, and saturation velocity [1]. In particular, many manufacturers in the electric vehicle (EV) industry are turning to 4H-SiC power MOSFETs to replace current Si IGBTs in order to reap benefits such as lower on-state resistance and reduced switching losses [2,3]. Due to the stringent safety requirements for these applications, the reliability of the SiC MOSFETs is paramount. One major area of concern for the SiC MOSFET is the gate oxide reliability, particularly the high rate of early oxide failures in the field due to the high density of extrinsic defects [4,5,6,7,8].

These extrinsic defects can be due to contamination in the oxide, defects at the SiC/SiO₂ interface, and/or defects within the oxide itself, such as pits, voids, porous oxide, etc., as shown in Figure 1a [6,8,9]. This is defined by the oxide thinning model, where defects in the oxide are treated as local points of thin oxide. Therefore, at a given gate voltage, the gate oxide around these defects experiences a locally high oxide electric field (E_ox) which causes the devices to break down sooner compared to an oxide without defects, seen in the Weibull plot extrinsic tail in Figure 1b [7,9,10]. This means that there is a screening voltage that is above the breakdown voltage of some oxide defects but below the breakdown voltage of the bulk oxide. By increasing the screening voltage, it is possible to break down more devices with defects with the added risk of device characteristic shift or reduced intrinsic lifetime for non-defected devices. However, most device manufacturers do not follow a sufficiently aggressive screening regime to fully filter out devices with extrinsic defects, causing early failures in the field.

The efficiency of a screening process can be defined as

$$\eta ={\displaystyle \frac{V_{screen}}{V_{use}}}$$

(1)

where $\eta$ is the screening efficiency, V_screen is the screening voltage, and V_use is the operational gate voltage, usually around 20 V [6,12]. In other words, the higher the ratio between the screening voltage and operational voltage, the more efficient the process will be at removing devices with extrinsic gate oxide defects.

Generally, a gate oxide screening process applies a high gate voltage pulse with the goal of removing devices with extrinsic defects while maintaining intrinsic lifetime and electrical characteristics of healthy devices [13]. Recent approaches have led to the introduction of higher field screening (E_ox < 9 MV/cm) [14] for short durations. The screening field and duration are limited by the downwards threshold voltage (V_th) shift at higher oxide electric fields. The main cause for this threshold voltage shifting is the hole injection and charge trapping in the oxide at high oxide electric fields. At such fields, holes are generated in the polysilicon due to impact ionization and then are trapped in the oxide [14,15,16]. This causes the net charge in the oxide to increase positively, decreasing the V_th. In this case, the screening efficiency of the technique is limited by the threshold voltage shift, which is dictated by the charge trapping in the oxide. The efficiency can be further improved by increasing either the screening time, temperature, or voltage; however, care must be taken to make sure that the healthy device characteristics and intrinsic lifetimes do not significantly degrade.

In order to improve screening efficiency while maintaining current device electrical characteristics, the screening with adjustment pulse (SWAP) technique is investigated [11]. This room-temperature method applies an extremely high gate voltage pulse (corresponding to E_ox ≥ 9 MV/cm) for a longer period of time (≥1 s), which purposefully shifts the threshold voltage down. A lower field pulse is then applied to recover the threshold voltage shifts. This adjustment pulse can also be thought of as an additional low-field screening pulse. In the proposed SWAP method, the screening efficiency is improved as a higher screening voltage can be applied without degrading the device’s electrical characteristics, reducing the field failure rate of the screened devices. The screening procedure is performed at room temperature in order to facilitate the high throughput of devices through the process. Industrial manufacturers may need to screen thousands of devices for gate oxide defects before the MOSFETs can enter into application use. By performing SWAP at room temperature, the need for a high temperature screening setup is negated, and the total turnaround time is reduced, lowering costs. Additionally, the screening efficiency mainly depends on the screening voltage, and temperature plays a much smaller role [6]. Therefore, it is beneficial to trade off the high screening temperature for higher screening voltage as is undertaken in SWAP.

In this work, the effects of the SWAP screening technique are investigated on commercial 1.2 kV 4H-SiC MOSFETs with planar and trench gate structures. The effects of SWAP on the device V_th, on-resistance (R_ds-on), and density of interface traps (D_it) are presented and discussed. Finally, constant-voltage time-dependent dielectric breakdown (CV-TDDB) measurements are performed to monitor the device’s intrinsic lifetime. By screening at higher gate voltages and durations, the SWAP technique aims to improve the industry screening efficiency, reducing field failure rates, and enhancing the reliability of the SiC MOSFETs in operation.

2. Materials and Methods

The details of the 1.2 kV commercial SiC MOSFETs from Vendors F, D, and B used in this work are shown in

Table 1. Details of the DUTs from Vendor F, D, and B.

Vendor	Vendor F	Vendor D	Vendor B
Structure	Planar	Planar	Asymmetric Trench
Voltage Rating	1200 V	1200 V	1200 V
Current Rating	7.6 A	20 A	4.7 A
Average Oxide Vbr @ 150 °C	42 V	54.3 V	62.8 V
Estimated tox	38.2 nm	49.4 nm	57.1 nm

. The devices from Vendor F and Vendor D are both planar, while the devices from Vendor B are asymmetric trench devices. A schematic for the planar and asymmetric trench MOSFETs are shown in Figure 2a,b, respectively. Prior to screening, the oxide thickness (t_ox) of each vendor is estimated by performing a gate ramp-to-breakdown measurement at 150 °C. A sample of devices from each vendor has the drain and source shorted to ground, while the gate is ramped until the oxide breaks down. An average breakdown voltage is taken, and then divided by the critical electric field of SiO₂ (taken to be ~11 MV/cm [5]) to estimate the t_ox for each vendor.

All measurements and procedures were performed at room temperature on a Keysight B1506A parametric analyzer. The threshold voltages were measured by the constant current method, as defined in the vendor datasheet, where the gate and drain are tied and ramped together until a target drain current of 1 mA is measured. Additionally, the R_ds-on for each device was measured with 20 V on the gate at the rated drain current. Sub-threshold measurements were also performed in order to estimate the device D_it by measuring the drain current of the transfer characteristics at subthreshold region while holding the drain voltage at 100 mV [17].

To calculate the D_it, we first have to understand the subthreshold drain current equation given as

$$I_{ds}=I_0{e}^{{\displaystyle \frac{q{V}_{gs}}{nkT}}}\left(1-e^{-{\displaystyle \frac{q{V}_{ds}}{kT}}}\right)$$

(2)

where I₀ is the drain current with no gate voltage, T (K) is the temperature, k is the Boltzmann constant (eV/K), and n is the ideality factor [17]. n is given by

$$n=1+{\displaystyle \frac{C_D+C_{it}}{C_{ox}}}$$

(3)

where C_d is the depletion capacitance, C_it is the interface trap capacitance per unit area, and C_ox is the oxide capacitance calculated by dividing the permittivity of SiO₂ by the estimated thickness of the oxide [17]. From the C_it, the D_it with respect to the surface potential ϕ_s can be calculated as

$$D_{it}\left({\varphi }_s\right)={\displaystyle \frac{C_{it}}{q}}.$$

(4)

To obtain D_it with respect to the trap level, we have to calculate the energy difference of the conduction band at the interface (E_C) and the trap energy level (E_T) as a function of surface potential defined as

$$E_C-E_T={\displaystyle \frac{E_g}{2}}-q\left[{\varphi }_F-{\displaystyle \frac{2.3kT}{q}}\log \left({\displaystyle \frac{I_{ds}\left(2{\varphi }_F\right)}{I_{ds}\left({\varphi }_s\right)}}\right)\right]$$

(5)

where E_g is the bandgap of SiC (~3.26 eV), and ϕ_F is the Fermi level [17]. With Equations (4) and (5), the energy dependent D_it profile with respect to the trap level position compared to the conduction band edge at the surface can be plotted, allowing us to see how the interface trap density changes as we apply the screening conditions [17].

Figure 3 shows the step-by-step testing procedure of the SWAP methodology. First, prescreen threshold voltage (V_th-pre), on-resistance (R_ds-on-pre), and sub-threshold (ST_pre) measurements are conducted. Then, the initial oxide screening pulse with voltage V_screen for duration t_screen is applied and the gate leakage current is monitored. An intermediate threshold voltage V_th-screen is measured before the adjustment pulse with voltage V_adj for duration t_adj is applied. Then, a post-adjustment threshold voltage V_th-adj is measured before a 48 h recovery period. Both the initial screening pulse and the adjustment pulse voltage magnitudes are set by multiplying a desired oxide field (E_screen and E_adj respectively) by the estimated device oxide thickness. Finally, post-recovery threshold voltage (V_th-final), on-resistance (R_ds-on-final), and sub-threshold (ST_final) are measured.

In order to normalize the screening conditions to account for different oxide thicknesses, most of the analysis is performed with regard to the applied oxide field rather than an absolute voltage. To quantify the shift in electrical characteristics, the change in device parameters is defined as the difference between the post-recovery values and the pre-screen values. In other words, the V_th shift for a given device is defined as

$$∆V_{th}=V_{th-final}-V_{th-pre}$$

(6)

and the R_ds-on shift is defined as

$$∆R_{ds-on}=R_{ds-on-pre}-R_{ds-on-final}.$$

(7)

Since there are variations in the V_th that are intrinsic to the devices (as shown in Figure 4 for Vendors F, D, and B used in this work), rather than using just the total shift in voltage, a percentage shift relative to the original pre-screen threshold voltage for each device is calculated. To normalize the amount shifted to the original values, the percent ∆V_th is given by

$$∆V_{th}\left(\%\right)={\displaystyle \frac{∆V_{th}}{V_{th-pre}}}\times 100\%$$

(8)

and the percent ΔR_ds-on by

$$∆R_{ds-on}\left(\%\right)={\displaystyle \frac{∆R_{ds-on}}{R_{ds-on-pre}}}\times 100\%.$$

(9)

To ensure that device characteristics are not shifting dramatically due to the screening process, the targeted percent shift in the V_th and R_ds-on is ±5%. The high voltage screening can potentially introduce new traps in the interface, so it is essential to look into the D_it profile at E_C–E_T ~0.1 eV. To check the intrinsic lifetime of the devices after screening, CV-TDDB measurements are conducted at 150 °C for both screened and unscreened devices, and the resulting Weibull plots are compared. For this measurement, 10 devices per screening condition are placed in parallel in a high temperature chamber with their drains and sources shorted to ground, while a constant high voltage stress is applied to the gates [5]. Time-to-failure is measured for each device, and a Weibull plot is generated for each screening condition. If the intrinsic lifetime is minimally affected by the SWAP procedure, then the Weibull plots from the unscreened and screened devices should be very close to each other.

3. Results

This section discusses the SWAP calibration process and covers the results of the SWAP experiments on the DUTs from Vendors F, D, and B. In order to calibrate the SWAP screening process, first a ∆V_th with respect to screening time and field with no adjustment pulse is measured. Then, an appropriate screening field and time are chosen where a significant negative shift in the threshold voltage is seen. Then, an appropriate adjustment pulse field and duration are calibrated through trial and error until the ∆V_th is brough back within acceptable values. Once both the screening and adjustment pulse have been calibrated, then a larger sample can be screened at those conditions. At this point, the ΔR_ds-on, D_it, and change in intrinsic lifetime can be measured. If all are within acceptable limits, then the calibrated pulses can be applied for any device from that specific device design or part number. This process is shown in the following subsection.

3.1. Calibration and Results for Vendor F1

The first step to calibrate the SWAP procedure is to see how the threshold voltage shifts without any adjustment pulse post-screening as a baseline measurement. To do this, each device is screened at room temperature at a single E_screen ranging from 7.5 MV/cm to 10 MV/cm with a 0.5 MV/cm step for a single t_screen from 1 s to 10 s, with V_th measurements performed before and after the screen, and after a 48 h recovery period. The baseline screening results from Vendor F are shown in Figure 5, where each datapoint is an individual DUT. The effects of hole trapping can be clearly seen as the V_th drops off steeply at around E_screen of 9 MV/cm. Additionally, as t_screen increases from 1 s to 10 s, it is apparent that hole trapping is dominant even at fields as low as 7 MV/cm due to the higher negative magnitude of ∆V_th. In order to maximize the screening efficiency, the SWAP t_screen was held at 10 s and the E_screen was set at 9 MV/cm, 9.5 MV/cm, and 10 MV/cm. Then, the adjustment pulse was calibrated. In this case, an E_adj of 8 MV/cm was chosen based on the baseline measurements to prevent hole trapping, and t_adj of 1 s, 1.5 s, and 2 s were tested, with the ΔV_th measurements shown in Figure 6. By comparing the ∆V_th of the devices that were exposed to the adjustment pulse to the baseline measurements, it can be seen that the adjustment pulse can effectively reduce the magnitude of the ∆V_th to acceptable levels. Based on these results, the t_adj for this vendor was set to 2 s.

Table 2. SWAP conditions for Vendor F.

Escreen (MV/cm)	tscreen (s)	Eadj (MV/cm)	tadj (s)
9	10	8	2
9.5	10	8	2
10	10	8	2

summarizes the final SWAP conditions for the devices from Vendor F.

Once the SWAP conditions had been set from the calibration measurements, a set of 10 devices was screened under each condition to fully understand its effects on the V_th, R_ds-on, D_it, and intrinsic lifetime. Figure 7a,b shows the distribution of ΔV_th and ΔR_ds-on for each screening condition, respectively. It can be seen that the distribution for the ΔV_th is roughly within the acceptable ±5% range for all SWAP conditions, and notably all of the ΔR_ds-on is tightly within ±1%. The changes in R_ds-on are most likely due to the changes in the V_th rather than changes in the actual resistance, as the ΔR_ds-on mirrors the ΔV_th for each screening condition. There are two main points to draw from this. One is that we are able to massively increase the screening efficiency by increasing the E_screen and t_screen. The second point is that we can prevent the dramatic decrease in the V_th due to hole trapping in the oxide from the high initial E_screen by applying a follow-up adjustment pulse without effecting the R_ds-on significantly.

Figure 8 presents the Weibull plots and fit lines comparing the lifetimes of the screened DUTs from each condition to those of a set of unscreened devices at 150 °C and at a gate oxide electric field of 8.9 MV/cm or roughly 34 V. The sample size for each condition was 10 devices. It can be seen that the fitted intrinsic lifetimes of the screened DUTs are actually longer than those of the unscreened DUTs. This is due to the device-to-device variation and natural variability in oxide lifetime under the same stress conditions and is not a concern. What should be noted, however, is that the intrinsic lifetime of all devices, screened or unscreened, is roughly the same. Therefore, for the three set SWAP conditions for Vendor F, none of them reduced the intrinsic lifetime of the DUTs.

Figure 9a–c shows a representative sample of the energy-dependent D_it distribution before and after the SWAP procedure for the three screening conditions (9 MV/cm, 9.5 MV/cm, and 10 MV/cm, respectively) for Vendor F from E_C–E_T of 0.1 eV to 0.4 eV. It can be seen that as the E_screen increases, so does the D_it close to the conduction band edge. However, as seen from Figure 7, this increase in D_it due to the SWAP process does not significantly affect the device R_ds-on or the device V_th. Therefore, this D_it increase is negligible in the application use of the DUT after screening and does not negatively affect the device’s intrinsic lifetime, as seen from Figure 8.

By combining the results from Figure 7, Figure 8 and Figure 9, it is obvious that the SWAP conditions listed in Table 2 applied to the devices from Vendor F do not significantly affect the DUTs for V_th, R_ds-on, D_it, and lifetime. Although no devices failed during these conditions, it is worth noting that these screening procedures were applied on top of the screening or burn-in that was carried out at the vendor fabrication facility. This means that manufacturers purchasing SiC MOSFETs from this vendor can safely apply these conditions to the devices without changing device parameters or lifetime. This leads to increased screening efficiency and improved safety and reliability of the SiC MOSFETs once they enter the field.

3.2. Results for Vendor D

The baseline screening results in terms of ΔV_th with respect to E_screen and t_screen are shown in Figure 10. While the hole trapping effects are obvious due to the drop-off of ΔV_th starting around E_ox of 9.5 MV/cm, the field required is slightly higher than the devices from Vendor F.

Table 3. SWAP conditions for Vendor D.

Escreen (MV/cm)	tscreen (s)	Eadj (MV/cm)	tadj (s)
9.5	10	8	5
10	10	8.5	200

shows the selected SWAP conditions for the devices from Vendor D. Notably, the time needed to adjust the V_th to within the acceptable ranges is longer for Vendor D than Vendor F, even with the same initial screening pulse conditions, and especially so for E_screen of 10 MV/cm.

Figure 11a,b show the distribution of ΔV_th and ΔR_ds-on for each screening condition, respectively, for Vendor D. While the ΔR_ds-on is within the ±5% desired range, the ΔV_th at E_screen = 9.5 MV/cm has some values that fall outside. Additionally, from Figure 12, both conditions end up degrading the device’s intrinsic lifetime as seen by the leftward shift in the Weibull plots of the screened DUTs relative to the unscreened one. However, there is no significant D_it increase associated with either condition, as shown with a representative sample in Figure 13a,b. Figure 11 and Figure 12 show that care must be taken in order to prevent significant device parameter shift or degradation, either by reducing E_screen or t_screen. Hence, a well calibrated SWAP process is essential to capture the benefits of the higher screening efficiency (due to higher E_screen) while preventing undesired ΔV_th, ΔR_ds-on, and lifetime degradation.

To this end, new SWAP tests were recalibrated to the conditions shown in

Table 4. New SWAP conditions for Vendor D.

Escreen (MV/cm)	tscreen (s)	Eadj (MV/cm)	tadj (s)
9.5	5	8	2

. Results shown in Figure 14a–c show acceptable ΔV_th, ΔR_ds-on, and D_it shift in a representative sample. The current results are promising with ΔV_th and ΔR_ds-on tightly within the ±5% range and no increase in the D_it. With the addition of the adjustment pulse, the number of variables for the screening treatment of the gate oxide doubles due to the extra pulse compared to single pulse gate screening. While this complicates the calibration significantly, the SWAP screening process can achieve more effective screening due to its higher E_screen in the initial screening pulse, making the calibration procedure rewarding in the long run from the decrease in extrinsic failures in the field.

3.3. Results for Vendor B

Figure 15 shows the baseline screening ΔV_th results from Vendor B, which show the effects of hole trapping in the oxide starting around an E_screen of 8.5 MV/cm, with a significant drop at 9 MV/cm for t_screen of 10 s. As seen from

Table 5. Attempted SWAP conditions for Vendor B.

Escreen (MV/cm)	tscreen (s)	Eadj (MV/cm)	tadj (s)	ΔVth (%)
8.5	10	8	2	−7.7
8.5	10	8	4	−8.4
9	10	8	2	−44
9	10	8	10	−37
9	5	8	10	−27
9	5	7.5	10	−30
9.5	10	8	2	−32
9.5	1	8	10	−42

, which shows the results of multiple SWAP calibration attempts, it is much harder to adjust the ΔV_th after screening for Vendor B compared to the DUTs from Vendor D and especially compared to Vendor F, even with less aggressive SWAP conditions. Similar to Vendor D, this could be due to the higher screening voltages applied from the manufacturer due its higher oxide thickness. The devices from Vendor B have the thickest gate oxide out of all three vendors, and these devices proved to be the hardest to calibrate for the SWAP technique. Additionally, the gate oxides of the DUTs from Vendor B are deposited, rather than thermally grown as in the devices from Vendor D and Vendor F. It is known that SiC trench MOSFETs tend to have higher D_it due to the trench wall etching process and lower quality gate oxide. This increase in the interface traps leads to more charge trapping, which can cause the ΔV_th to increase [18,19,20]. For all SWAP conditions tested, none stayed within the desired ±5% ΔV_th range.

Figure 16 shows the effects of each step in the SWAP process on the device ΔV_th for a given t_screen of 10 s, E_adj of 8, and t_adj of 2 s. As shown, it is apparent that the effects of the adjustment pulse are only very effective for devices screened at higher fields. For E_screen at 8.5 MV/cm, the adjustment pulse has almost no effect on the ΔV_th, and so there is no point is setting E_screen lower for SWAP. For E_screen of 9 MV/cm and 9.5 MV/cm, the effects of the adjustment pulse are more apparent; however, even though more of the V_th can be recovered at higher E_screen, the significant ΔV_th from hole injection in the oxide from the screening pulse completely negates the beneficial effects of the adjustment pulse. Therefore, similar to the devices from Vendor D, care must be taken to reduce either the E_screen or t_screen in order to preserve the device characteristics.

4. Discussion

The methodology of the adjustment pulse after screening is based on the charge trapping phenomenon in the SiC MOSFET gate oxide during the screening process [14,15,21]. At high oxide electric fields (E_ox > ~9 MV/cm), the electrons from the SiC tunnel through the oxide due to the high field, causing impact ionization in the polysilicon gate of the SiC MOSFET as shown in Figure 17a [5,22]. During impact ionization, the electrons are swept out of the device, while the holes are injected into the oxide due to the high E_ox in a process known as anode hole injection, with some holes trapped near the interface in the oxide. This net positive charge in the gate oxide causes the threshold voltage to decrease. On the other hand, at lower oxide electric fields (E_ox < ~9 MV/cm), the electrons from the SiC do not have the energy to cause impact ionization in the gate, and so more electrons than holes are trapped in the gate oxide due to the elimination of anode hole injection, as shown in Figure 17b [14]. This causes a net negative charge in the gate oxide, which increases the threshold voltage.

During the initial screening pulse of SWAP, the E_screen is high enough to cause impact ionization and anode hole injection. This causes the initial V_th to shift down after the screening pulse, as shown in Figure 17a. Then, the adjustment pulse is applied, which only injects electrons. This secondary pulse also causes some of the trapped holes to detrap from the oxide. The combined effects of this cause the threshold voltage to increase again, as shown in Figure 17b. By balancing the effects of electron and hole trapping within the oxide, the screening and adjustment pulses can be tuned in order to reduce the total ΔV_th during the screening process [11]. Proper calibration by tweaking the initial E_screen and t_screen is needed to prevent significant shift in device characteristics (ΔV_th, ΔR_ds-on, D_it, and lifetime). By reaching for the maximum possible screening field and time, the overall screening efficiency is improved, and the risk of extrinsic failure in the field for the SiC MOSFETs is reduced.

In order to confirm that the gate oxide of the DUTs is not locally damaged during the SWAP process, a pre-screen and post-recovery gate leakage current measurement at V_gs = 20 V is performed and compared for Vendors F and D, as shown in Figure 18a,b, respectively. If possible damage to the gate oxide would not be observable by measuring the V_th, R_ds-on, and intrinsic lifetime, any damage to the oxide may be observable via a gate leakage current measurement [23]. Although this is not considered a calibration step, this measurement was performed in order to ensure that the post-recovery gate oxide is relatively healthy. As shown, there is no change in the gate leakage currents for both vendors for all testing conditions. If any significant damage to the gate happened during the SWAP process, then the leakage current after the screening and recovery process would be increased post-recovery [23]. However, there was no change in the device leakage currents, meaning that such damage did not occur.

Due to the random nature of extrinsic defects, a direct comparison between SWAP and other screening techniques based on screen-out performance will be very difficult without a very large sample size [24]. Compared to the traditional short high-voltage screening method, the SWAP method allows manufacturers to apply a higher screening voltage for a specific gate oxide thickness but reducing the amount of threshold voltage shift due to hole injection, which in turn increases the screening efficiency [6,14]. Compared to the long-term burn-in method, the SWAP method firstly applies a much higher screening voltage, while also being a much shorter process to complete (~5 s for SWAP versus many minutes to hours for burn-in) [6,24]. This allows manufacturers to increase the throughput of their device screening processes while also maintaining a high level of screening efficiency.

5. Conclusions

In this paper, the effects of the gate oxide screening with adjustment pulse (SWAP) procedure on the devices from Vendors F, D, and B are presented. Based on the results, with a well calibrated process such as that carried out for Vendor F, the ΔV_th caused by gate oxide screening at high E_ox (>~9 MV/cm) can be adjusted to within acceptable values. Additionally, it should not significantly degrade the device R_ds-on or D_it, or reduce the device’s intrinsic lifetime. Improperly calibrated SWAP screening can lead to unwanted changes in device characteristics and lifetime that cannot be outweighed by the benefits of higher E_screen, so care must be taken to ensure that the SWAP conditions are determined carefully. While no universal optimization method for multiple SiC MOSFET technologies is presented, this work shows that it is possible to reduce the ΔV_th due to high field oxide screening by properly calibrating the SWAP conditions for a set of devices. Although the initial calibration of the screening method is much more rigorous than a single pulse screening process, by accounting for some of the negative V_th shift with the adjustment pulse, SWAP allows manufacturers to screen at higher E_screen than before, increasing the screening efficiency. This leads to a reduction in devices with extrinsic defects entering the field, reducing the failure rate of the SiC MOSFETs in operation.