A Novel Low-Voltage-Based Methodology for Short-Circuit Withstand Time Screening of Commercial 4H-SiC MOSFETs

Abstract

With the rapid advancement of silicon carbide technology, device reliability has emerged as a critical concern for high-performance power electronics applications. Among various reliability challenges, the limited short-circuit withstand time (SCWT) of SiC MOSFETs, coupled with significant device-to-device variation, poses a serious risk, as it can lead to catastrophic field failures. In addition, established short-circuit screening technique utilizes high-voltage and high-stress condition that may degrade the long-term reliability of otherwise good devices. Hence, this work proposes a novel short-circuit screening methodology employing lower voltages and verifies it using commercial 1.2 kV 4H-SiC MOSFETs. The proposed approach can remove devices with lower SCWT while minimizing electrical and thermal overstress during screening. The results indicate that the proposed low-voltage screening technique offers a safe, repeatable, and reliable alternative to conventional short-circuit screening method, making it well suited for practical manufacturing, leading to system-level reliability enhancement in SiC-based power electronics applications.

1. Introduction

Short-circuit withstand time (SCWT) is a critical reliability benchmark for power semiconductor devices, as insufficient short-circuit (SC) ruggedness can result in catastrophic failures during operation [1]. With the rapid adoption of silicon carbide (SiC) technology, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) have increasingly replaced conventional silicon IGBTs in high-performance power electronics systems. This transition is driven by the superior material properties of 4H-SiC, including its wide bandgap, high thermal conductivity, and high critical electric field. These characteristics enable higher switching frequencies, increased power density, and improved efficiency [2]. These advantages are particularly attractive in industrial, automotive, and traction applications such as electric vehicle (EV) power converters and traction inverters where reliability and long-term ruggedness are of paramount importance.

Despite these benefits, the SC robustness of commercial 4H-SiC MOSFETs remains a major reliability concern. The inherently smaller chip area and higher power density of SiC devices result in severe thermal stress, leading to rapid thermal runaway, accompanied by gate oxide degradation and eventual gate failure, thereby severely limiting the SCWT of the device [3,4,5,6].

Significant research efforts have been directed toward improving device-level short-circuit reliability [7,8,9,10,11,12,13,14] and detailed investigations have been carried out to understand short-circuit failure mechanisms under different gate and drain voltage conditions for both planar and trench MOSFETs [4,5,15,16,17,18,19,20,21,22,23,24,25,26,27,28]. Nevertheless, commercially available state-of-the-art SiC MOSFETs typically exhibit SCWTs in the range of 2-7 μs, which further degrade at elevated voltages and temperatures [26]. In addition, considerable device-to-device variation in SCWT, often approaching 1 μs even within a small batch of devices, has been reported [29]. This variability is primarily attributed to the minor process-induced differences in device structure during fabrication. The combination of limited SCWT, large device-to-device variability, and the high-frequency switching capability of SiC MOSFETs poses serious challenges for protection circuit design. As highlighted in prior studies, the fast switching speed of SiC devices necessitates enhanced noise suppression, which often compromises the response time of SC protection circuits [30], thereby increases system-level vulnerability.

To address these challenges, it is essential to screen commercial SiC MOSFETs for short-circuit capability and selectively eliminate devices with inferior SCWT before deployment without compromising the reliability of robust devices. The conventional high-voltage short-circuit screening approach known as Peak Transient Drain Current Methodology (PTDM) [29] suffers from several limitations, although effective in specific cases. This method applies high drain voltage for a short period of time, which may reduce device lifetime and adversely affect the long-term reliability of otherwise healthy devices. Moreover, the reported technique is limited to planar MOSFET structure and is prone to false rejection, thereby reducing manufacturing yield.

In this work, a novel low-voltage SCWT screening methodology for commercial 1.2 kV 4H-SiC MOSFETs is proposed and experimentally validated using both planar and trench gate devices. The proposed approach, termed Low-Voltage Short-Circuit Energy Evaluation (LVSCEE), utilizes controlled low-voltage stress to accurately differentiate devices with lower SCWT from reliable ones while minimizing degradation of the screened devices. Unlike high-voltage screening technique, the proposed method significantly reduces electrical and thermal overstress, enabling safe and repeatable screening, applicable to both planar and trench commercial SiC MOSFETs. Furthermore, key electrical parameters are extracted and analyzed before and after screening to assess potential performance degradation. The results demonstrate that the proposed methodology achieves consistent SCWT screening with negligible impact on device characteristics, making it a practical and reliable solution for improving system-level robustness in SiC power electronics applications.

2. Experimental Methodology

2.1. Device Details

Commercial 1.2 kV SiC MOSFETs with planar gate and reinforced double-trench gate structures from Vendor F and Vendor G2, respectively, were utilized in this study. The typical device structures are shown in Figure 1. The device parameters are presented in

Table 1. 1.2 kV Commercial devices details.

Vendor	Vendor F	Vendor G2
Device Type	Planar	Reinforced Double-Trench
Rated Voltage (kV)	1.2	1.2
Rated Current (A)	7.6	26
Typical Threshold Voltage (V)	2.5	2.8
Typical On-Resistance (mΩ)	350	62
Number of Devices Tested	18	25

. Before SC measurement, each device underwent typical electrical characterizations using a Keysight B1506A Power Device Analyzer (Keysight Technologies, Colorado Springs, CO, USA) to obtain threshold voltage (V_th) and on-resistance (R_on). V_th of these devices were extracted using the linear extrapolation method [31] at drain-to-source voltage (V_ds) of 100 mV, whereas R_on was calculated at gate-to-source voltage (V_gs) of 20 V and V_ds = 1.5 V.

2.2. Short-Circuit Evaluation

SC evaluation of commercial 4H-SiC MOSFETs was carried out using a typical SC setup, as shown in Figure 2 [29]. The setup contained three 100 μF thick film capacitors to stabilize the DC source voltage, along with a 1 μF decoupling capacitor with low ESL (equivalent serial inductance) and ESR (equivalent serial resistance), guaranteeing high frequency switching conditions. A 10 Ω gate resistor was used to ensure controlled turn-on and turn-off of the device under test (DUT). Drain-to-source transient current during SC evaluation (I_ds) was measured using a 10 mV/A sensitive PEM CWT3 Rogowski coil with a rated peak current of 600 A. For enhanced safety of the setup, 5 kΩ current-limiting resistors along with 66 kΩ bleeding resistors were provided. The SC measurements were carried out at varying V_ds = 200 V, 400 V, 600 V, and 800 V under V_gs = 20 V. Depending on the condition, the gate turn-on pulse width was varied to ensure minimum heating effect. To evaluate the SCWT of the DUT, V_gs = 20 V and V_ds = 800 V condition was selected where the starting pulse was kept at 0.5 μs, which was then increased by a step of 0.1 μs until failure was observed. Sufficient cooling time was provided in between two consecutive pulses to guarantee minimum heating effect. The time of failure (or the pulse width) was termed as the SCWT of the DUT. The setup was kept unchanged throughout the experiments to ensure consistent results.

3. Low-Voltage Short-Circuit Energy Evaluation (LVSCEE)

3.1. Variation in SCWT

1.2 kV 4H-SiC MOSFETs from Vendor F and Vendor G2 underwent SCWT measurement at V_gs = 20 V and V_ds = 800 V, and the results are shown in Figure 3. DUTs were carefully selected from same batch and lot to ensure consistency among devices. The results show a 0.6 μs SCWT variation for both vendors.

3.2. Peak Transient Drain Current Methodology and False Rejection Rate

$$P_{TDM}={\displaystyle \frac{I_{peak}}{slope}}$$

(1)

$$slope={\displaystyle \frac{\left(I_{peak}-I_{min}\right)}{\left(t_{screen}-t_{peak}\right)}}$$

(2)

where I_peak, I_min, t_screen, and t_peak are peak drain current, turn-off drain current at t_screen, screening pulse width, and time at which drain current achieves I_peak, respectively.

The high-voltage PTDM [29] has been proposed to selectively screen out devices with lower SCWT without damaging reliable devices. First, a SCWT screening parameter P_TDM is calibrated using Equations (1) and (2) with a preliminary set of devices. This is performed by measuring the SCWT of the preliminary set at V_ds = 800 V and V_gs = 20 V while the gate pulse duration t_screen is incremented in 0.1 μs steps until the device fails. Depending on the minimum SCWT requirement, a permissible range of P_TDM can be established for devices from the same vendor and production lot. Once the P_TDM range is defined, only a single pulse of t_screen duration is needed to remove devices with inferior SCWT, without destroying reliable ones.

The variation in P_TDM is influenced by several device design and process parameters, such as die area, die volume, channel design, active area design, gate oxide thickness and quality, interface defect state density, doping profile, temperature diffusion process, etc. [32,33,34]. Consequently, both the manufacturers and the end users must experimentally determine P_TDM ranges for different vendors and process flows. However, a major concern of PTDM is the possibility of incorrectly rejecting reliable devices during the screening process, as illustrated in Figure 4 for Vendor F devices. This phenomenon is referred to as false rejection.

The false rejection rate (FRR) can be defined as follows:

$$FRR=\left({\displaystyle \frac{Number of reliable devices falsely screened out }{Total number of devices}}\right) \times 100\%$$

(3)

Using this definition, an FRR of 8.69% is observed for Vendor F devices (number of devices tested are 23) at P_TDM ≥ 2.4 s. Such a level of false rejection is undesirable, as it adversely affects device yield and overall manufacturing efficiency.

3.3. Proposed LVSCEE Method

Fundamentally, the proposed LVSCEE method is based on the SC energy during different applied V_ds under a particular gate pulse width (t_pulse). Mathematically, SC energy at a particular pulse (E_pulse) can be defined as follows:

$$E_{pulse}={\int }_0^{t_{pulse}}{V}_{ds}{I}_{ds}dt$$

(4)

During the event of SC, the DUT experiences lattice heating [26], which eventually causes the failure of the device. This effect of heating is directly correlated to the transient energy E_pulse at each time frame. Hence, a correlation between E_pulse and SCWT can be established. The proposed LVSCEE method is graphically shown in Figure 5.

For successful screening, the key factors include determining the appropriate E_pulse under a certain V_ds and pulse width (t_pulse) as well as setting the minimum SCWT threshold to effectively screen out weaker devices, while maintaining an extremely low false rejection rate. Furthermore, the effect of the screening on the devices needs to be examined using static characteristics and interface defect analysis pre- and post-screening to ensure no degradation. Upon establishing the E_pulse window needed for the reliable devices, this methodology can be used in thousands of devices just by applying a low-voltage single pulse to remove the weaker devices without damaging the reliable ones. Moreover, as this methodology relies solely on the dissipation energy under a given V_ds and t_pulse, it enables the applicability of this technique irrespective of screening or operating voltage level, and cross-voltage correlation can be established.

3.3.1. Drain Current Behaviour Under Different Drain Voltages

The first part of this work aims to understand the behaviour of the drain current under different applied drain voltages. Figure 6 shows the I_ds vs. transient time characteristics of a representative Vendor F device under t_pulse = 1.5 μs for V_ds = 200 V, 400 V, 600 V, and 800 V. It can be clearly seen that under a fixed t_pulse, with the increase in V_ds level from 200 V to 800 V, the peak drain current (I_ds,peak) enhances significantly, indicating more heat generation.

3.3.2. Determining Screening Pulse Energy, Pulse Width, and SC Screening

Using Equation (4), the screening pulse energy (E_pulse) under different V_ds and t_pulse = 1.5 μs was calculated and is shown in Figure 7 for the Vendor F devices. SCWT at different drain voltage levels is also plotted in Figure 7. It is evident that as V_ds increases, E_pulse under the same t_pulse increases and SCWT decreases. Under V_ds = 400 V, the representative device can withstand ~9 μs, after which SC occurs.

Another critical aspect of effective short-circuit screening is the optimization of the t_pulse to minimize FRR. Figure 8 illustrates the SCWT measured at V_ds = 800 V as a function of E_pulse calculated at V_ds = 400 V for different t_pulse values using Vendor F devices. The pulses are varied from 2.5 μs to 4.0 μs in steps of 0.5 μs. It can be clearly seen that, under t_pulse = 3.0 μs (Figure 8b) and t_pulse = 3.5 μs (Figure 8c), no device was falsely rejected.

To further assess the impact of screening conditions on devices’ thermal integrity, additional electro-thermal simulations were performed using LTspice to estimate the junction temperature (T_j) of a typical Vendor F device under t_pulse corresponding to an extremely low FRR. T_j has been evaluated using a Cauer thermal network model [35], as shown in Figure 9a. This model utilizes an equivalent RC network, where the input is the instantaneous power dissipation (V_ds × I_ds) as a function of transient time. The equivalent RC parameters are listed in

Table 2. RC parameter values of Cauer thermal network model.

Parameter	Values
R1	406 mΩ
R2	1.088 Ω
R3	481 mΩ
R4	341 mΩ
C1	238 μF
C2	1.15 mF
C3	5.86 mF
C4	90.1 mF

.

The simulation result (Figure 9b) indicates that, under the optimized conditions (V_ds = 400 V, t_pulse = 3 μs, and 3.5 μs), maximum junction temperature (T_j,max) remains below one-third of the value observed during convention SCWT measurement at V_ds = 800 V. Based on this analysis, in this work, we considered V_ds = 400 V with optimized pulse width (t_{pulse,optimized}) of 3 μs for screening of Vendor F devices, to assure no thermal damage occurs while maintaining reliable screening output.

Figure 10a shows the SCWT as a function of optimized E_pulse at t_{pulse,optimized} = 3.0 μs for Vendor F devices. Although the E_pulse is calculated at a lower drain voltage level of 400 V, to maintain consistency, SCWT is determined at V_ds = 800 V for the same devices. It is apparent that to remove devices with SCWT lower than or equal to 1.8 μs at V_ds = 800 V, E_pulse should be less than 0.05 J. Similar analysis was performed on Vendor G2 devices, considering t_{pulse,optimized} = 5.0 μs at V_ds = 400 V, and is shown in Figure 10b. To successfully remove devices with SCWT less than or equal to 3.4 μs at V_ds = 800 V, E_pulse should be less than 0.24 J.

It is evident that devices with lower E_pulse indicate lower heat generation and hence lower thermal effect, leading to higher SCWT. The t_pulse and V_ds need to be optimized for different vendors to ensure optimal screening. The analysis further shows that this methodology is independent of device design parameters or fabrication process flow and can be implemented easily without any prior device knowledge.

3.3.3. Effect of Short-Circuit Screening Process

The effect of the LVSCEE method on the devices’ characteristics was studied by measuring and comparing V_th, R_on, and gate leakage current (I_gss) on a batch of devices from each vendor before and after applying the E_pulse. The V_th of these devices was extracted using the linear extrapolation method [31] at V_ds = 100 mV, whereas the R_on was calculated at V_gs = 20 V and V_ds = 1.5 V. I_gss is measured at V_gs = 30 V. The results are consolidated in

Table 3. Key electrical parameters variations pre- and post-screening.

Vendor	Threshold Voltage (V)		On-Resistance (mΩ)		Gate Leakage Current (nA)
	Pretest	Post-Screening	Pretest	Post-Screening	Pretest	Post-Screening
F	6.11	6.09	313.9	300.01	25.8	25.6
G2	6.03	6	51.96	51.68	4201.71	4201.89

. All results are representative in nature.

Moreover, the effect of screening on the interface is determined by utilizing the subthreshold method [36] at room temperature. The mathematical model of this technique is briefly discussed below.

The drain current at subthreshold region is defined as

$$I_{ds}=I_0{e}^{{\displaystyle \frac{q{V}_{gs}}{nkT}}}\left(1-e^{{\displaystyle \frac{q{V}_{ds}}{kT}}}\right)$$

(5)

where the ideality factor n is given as

$$n={\displaystyle \frac{q}{2.3kT}}{\left({\displaystyle \frac{\mathsf{\partial }log{I}_{DS}}{\mathsf{\partial }{V}_{gs}}}\right)}^{-1}=1+{\displaystyle \frac{C_D+C_{it}}{C_{ox}}}$$

(6)

where $C_{\mathrm{D}}$ is depletion capacitance, $C_{\mathrm{o}\mathrm{x}}$ is oxide capacitance, and $C_{\mathrm{i}\mathrm{t}}$ is the interface trap capacitance per unit area.

The energy-dependent interface trap density is given as

$$D_{it}({\phi }_s)={\displaystyle \frac{C_{it}}{q}}$$

(7)

and the energy distribution of the trap level ${(E}_{\mathrm{c}\mathrm{s}}-E_{\mathrm{T}})$

$$E_{cs}-E_T={\displaystyle \frac{E_g}{2}}-q\left({\phi }_F-{\displaystyle \frac{2.3kT}{q}}\log \left[{\displaystyle \frac{I_{DS}\left(2{\phi }_F\right)}{I_{DS}\left({\phi }_s\right)}}\right]\right)$$

(8)

where surface potential (${\phi }_{\mathrm{s}}$) is in the range ${\phi }_{\mathrm{F}}$< ${\phi }_{\mathrm{s}}$ < ${2\phi }_{\mathrm{F}}$ and ${\phi }_{\mathrm{F}}$ is the Fermi potential.

Using Equations (7) and (8), $D_{\mathrm{i}\mathrm{t}}\left({\phi }_{\mathrm{s}}\right)$ of the representative devices from Vendor F and Vendor G2 were extracted before and after applying screening pulse, and the results are shown in Figure 11. It can be clearly seen that no significant degradation occurred due to the screening, and hence this methodology can be safely applied to remove devices with lower SCWT from a batch of devices without harming the reliable ones.

4. Conclusions

This paper presents a novel low-voltage short-circuit screening methodology, termed as LVSCEE, aimed to address the reliability challenges associated with poor SCWT and large device-to-device variability in commercial 1.2 kV 4H-SiC MOSFETs. Unlike the conventional high-voltage Peak Transient Drain Current Methodology, the proposed approach utilizes a lower screening voltage, and thus significantly reduces electrical and thermal overstress during screening. This minimizes the risk of latent damage and long-term reliability degradation. Experimental validation on both planar and trench gate SiC MOSFETs confirms that the LVSCEE method effectively removes devices with inferior SCWT while preserving the electrical integrity of robust devices. The analysis of key electrical parameters before and after screening indicates negligible performance degradation, highlighting the suitability of the proposed technique for practical manufacturing and qualification environments.

Overall, the LVSCEE methodology provides a reliable, repeatable, and structure-independent solution for SCWT screening of SiC MOSFETs. By enabling early elimination of weak devices without compromising healthy ones, the proposed approach contributes to enhanced system-level robustness and increased reliability of next-generation SiC-based power electronics applications.