Submit to Special Issue Submit Abstract to Special Issue Review for Symmetry Edit a Special Issue

Journal Menu

Journal Browser

Special Issue "Advances in Micro-Electronics with Symmetry/Asymmetry"

Special Issue Editors
Special Issue Information
Keywords
Published Papers

A special issue of Symmetry (ISSN 2073-8994). This special issue belongs to the section "Computer Science and Symmetry/Asymmetry".

Deadline for manuscript submissions: 31 March 2023 | Viewed by 3302

Share This Special Issue

Special Issue Editors

Dr. Dongdong Chen

E-Mail Website
Guest Editor

School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: intelligent design of piezoelectric devices; integrated circuits; 3D integrated microsystem; intelligent optimization algorithms and its applications
Special Issues, Collections and Topics in MDPI journals

Dr. Tianlong Zhao

E-Mail Website
Guest Editor

School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: 2D semiconductor materials and devices; first-principles calculations; semiconductor device reliability; piezoelectric materials and devices
Special Issues, Collections and Topics in MDPI journals

Dr. Di Li

E-Mail Website
Guest Editor

School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: integrated circuits design; RFIC design; mixed signal IC design and data converters
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In this Special Issue on “Advances in Microelectronics with Symmetry/Asymmetry”, we will focus on advances in the area of microelectronics with symmetry/asymmetry. Microelectronic technology is an advanced technology based on integrated circuits (ICs) and semiconductor devices. Due to its advantages of small size, low mass, and low power consumption, etc., microelectronic technology has been widely used in the information communication, industrial production, aerospace, transportation, and medicine industries, among others. In the modeling, design, and fabrication of ICs, materials, microdevices, and microsystems, the symmetry/asymmetry structures and situations are common, which can affect the performance, reliability, research and development cycle, and cost of chips and microsystems.

In our Special Issue, we welcome novel works reporting on mathematical models, high-efficiency/-precision numerical solution methods, intelligent design methods, and advanced processes for ICs, materials, microdevices, and microsystems with symmetry/asymmetry.

All interested researchers are kindly invited to contribute to this Special Issue with their original research articles, short communications, and review articles. Please note that all submitted papers must be within the general scope of the Symmetry journal.

Prof. Dr. Dongdong Chen
Dr. Tianlong Zhao
Dr. Di Li
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Symmetry is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

microelectronics
integrated circuits
2D semiconductor materials and devices
chips
microsystems
numerical algorithms
equivalent circuit models
machine learning
intelligent design
advanced processes

Published Papers (5 papers)

Download All Papers

Research

Jump to: Review

Open AccessArticle

A Machine Learning Mapping Algorithm for NoC Optimization

and

Symmetry 2023, 15(3), 593; https://doi.org/10.3390/sym15030593 - 25 Feb 2023

Viewed by 321

Abstract

Network on chip (NoC) is a promising solution to the challenge of multi-core System-on-Chip (SoC) communication design. Application mapping is the first and most important step in the NoC synthesis flow, which determines most of the NoC design performance. NoC mapping has been confirmed as an NP-hard (Non-Polynomial hard) problem, which could not be solved in polynomial time. Various heuristic mapping algorithms have been applied to the mapping problem. However, the heuristic algorithm easily falls into a local optimal solution which causes performance loss. Additionally, regular topologies of NoC, such as the ring, torus, etc., may generate symmetric solutions in the NoC mapping process, which increase the performance loss. Machine learning involves data-driven methods to analyze trends, find relationships, and develop models to predict things based on datasets. In this paper, an NoC machine learning mapping algorithm is proposed to solve a mapping problem. A Low-complexity and no symmetry NoC mapping dataset is defined, and a data augmentation approach is proposed to build dataset. With the dataset defined, a multi-label machine learning is established. The simulation results have confirmed that the machine learning mapping algorithm is proposed have at least 99.6% model accuracy and an average of 96.3% mapping accuracy. Full article

(This article belongs to the Special Issue Advances in Micro-Electronics with Symmetry/Asymmetry)

► Show Figures

Figure 1

Open AccessArticle

Thermal-Stress Coupling Optimization for Coaxial through Silicon Via

and

Symmetry 2023, 15(2), 264; https://doi.org/10.3390/sym15020264 - 17 Jan 2023

Viewed by 417

Abstract

In this paper, a thermal-stress coupling optimization strategy for coaxial through silicon via (TSV) is developed based on the finite element method (FEM), artificial neural network (ANN) model and particle swarm optimization (PSO) algorithm. In order to analyze the effect of design parameters on the thermal-stress distribution of coaxial TSV, the FEM simulations of coaxial TSV are conducted by COMSOL Multiphysics. The structure of coaxial TSV is symmetric. The mapping relationships between the design parameters and performance indexes are described by ANN models based on the simulation data of FEM. In addition, the multi-objective optimization function is formulated based on the desired performance indexes, and then the design parameters are optimized by the modified PSO algorithm. Based on the optimized design parameters, the effectiveness of the developed method is validated by FEM simulations. The simulated performance indexes agree well with the desired ones, which implies that the design parameters of coaxial TSV can be optimized to control the thermal-stress distribution. Therefore, the thermal-stress coupling optimization of coaxial TSV can achieve thermal-stress management to improve its reliability. Full article

(This article belongs to the Special Issue Advances in Micro-Electronics with Symmetry/Asymmetry)

► Show Figures

Figure 1

Open AccessArticle

Direct Training via Backpropagation for Ultra-Low-Latency Spiking Neural Networks with Multi-Threshold

and

Symmetry 2022, 14(9), 1933; https://doi.org/10.3390/sym14091933 - 16 Sep 2022

Cited by 2 | Viewed by 697

Abstract

Spiking neural networks (SNNs) can utilize spatio-temporal information and have the characteristic of energy efficiency, being a good alternative to deep neural networks (DNNs). The event-driven information processing means that SNNs can reduce the expensive computation of DNNs and save a great deal of energy consumption. However, high training and inference latency is a limitation of the development of deeper SNNs. SNNs usually need tens or even hundreds of time steps during the training and inference process, which causes not only an increase in latency but also excessive energy consumption. To overcome this problem, we propose a novel training method based on backpropagation (BP) for ultra-low-latency (1–2 time steps) SNNs with multi-threshold. In order to increase the information capacity of each spike, we introduce the multi-threshold Leaky Integrate and Fired (LIF) model. The experimental results show that our proposed method achieves average accuracy of 99.56%, 93.08%, and 87.90% on MNIST, FashionMNIST, and CIFAR10, respectively, with only two time steps. For the CIFAR10 dataset, our proposed method achieves 1.12% accuracy improvement over the previously reported directly trained SNNs with fewer time steps. Full article

(This article belongs to the Special Issue Advances in Micro-Electronics with Symmetry/Asymmetry)

► Show Figures

Figure 1

Open AccessArticle

Optimization Strategy of Regular NoC Mapping Using Genetic-Based Hyper-Heuristic Algorithm

and

Symmetry 2022, 14(8), 1637; https://doi.org/10.3390/sym14081637 - 09 Aug 2022

Viewed by 587

Abstract

Mapping optimization of network-on-chips (NoCs) for specific applications has become one of the most important keys of the SoC top-level design. However, the topology of NoC applied is usually regular topology, such as mesh, torus, etc., which may generate a large number of isomorphic solutions during the process of NoC mapping, which may reduce the convergence speed of mapping algorithms. In this paper, we proposed a generic-based hyper-heuristic algorithm named IRC-GHH for NoC mapping. To reduce the influence of isomorphic solutions, we analyzed the symmetry of NoC topology and proposed crossover operators based on the isomorphic solution to optimize the algorithm. We studied the situation of invalid crossovers and eliminated invalid iterations by adopting an isomorphic replacement crossover (IRC) strategy. To prevent the algorithm from falling into evolutionary stagnation in the late iteration, we introduce an adaptive mechanism to increase the usage frequency of the IRC operator automatically. Compared with GHH without IRC, the GHH with IRC can achieve, on average 15.25% communication energy reduction and 7.84% communication delay reduction. Full article

(This article belongs to the Special Issue Advances in Micro-Electronics with Symmetry/Asymmetry)

► Show Figures

Figure 1

Review

Jump to: Research

Open AccessReview

The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System

and

Symmetry 2023, 15(2), 418; https://doi.org/10.3390/sym15020418 - 04 Feb 2023

Viewed by 472

Abstract

In order to meet the requirements of high performance, miniaturization, low cost, low power consumption and multi-function, three-dimensional (3D) integrated technology has gradually become a core technology. With the development of 3D integrated technology, it has been used in imaging sensors, optical integrated microsystems, inertial sensor microsystems, radio-frequency microsystems, biological microsystems and logic microsystems, etc. Through silicon via (TSV) is the core technology of a 3D integrated system, which can achieve vertical interconnection between stacked chips. In this paper, the development and progress of multi-physics simulation design for TSV-based 3D integrated systems are reviewed. Firstly, the electrical simulation design of TSV in a 3D integrated system is presented, including the lumped parameters model-based design and numerical computation model-based design. Secondly, the thermal simulation design of TSV in a 3D integrated system is presented based on the analytical model or numerical computation model. Thirdly, the multi-physics co-simulation design of TSV in a 3D integrated system is presented, including the thermal stress and electron thermal coupling simulation design. Finally, this paper is concluded, and the future perspectives of 3D integrated systems are presented, including the advanced integrated microsystems, the crossed and reconfigurable architecture design technology and the standardized and intelligent design technology. Full article

(This article belongs to the Special Issue Advances in Micro-Electronics with Symmetry/Asymmetry)

► Show Figures