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A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Communications".

Deadline for manuscript submissions: 20 November 2025 | Viewed by 13940

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Special Issue Editor

Dr. Nicola Lusardi

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Guest Editor

Department of Electronics, Information and Bioengineering, Politecnico di Milano, Milano, Italy
Interests: digital electronic; time-to-digital converter; digital-to-time converter; field programmable gate array; system-on-chip
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Special Issue Information

Dear Colleagues,

The development of intelligent sensor technology with the capacity for integrated processing intelligence is crucial for a variety of reasons. It enables immediate digitization of sensor-detected information, avoiding losses or alterations during transmission, and facilitates rapid data analysis and real-time response. This proximity between the sensor and intelligence optimizes systems, reducing latency and communication overhead. The use of programmable parallel processing units such as field-programmable gate arrays (FPGAs) provides the capability of executing operations in parallel, allowing for increased speed and channel capacity. Furthermore, the reprogrammability offered by FPGA solutions makes these sensors more flexible and quicker to design than fully integrated solutions. Moreover, through processing time-mode techniques, it is sometimes possible to completely eliminate the fragile, sensitive, and often poorly integrable read-out electronics that separates the sensor from the FPGA, resulting in a more compact and cost-effective system.

The purpose of Sensor is to promote the scientific dissemination of intelligent and cutting-edge sensing technology. Therefore, a sensor that integrates processing units, especially if they are programmable and parallel such as field-programmable gate arrays (FPGAs), precisely pushes in this direction.

Dr. Nicola Lusardi
Guest Editor

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Keywords

integrated processing intelligence
digitization of sensor data
real-time processing
latency reduction
communication overhead
programmable parallel processing
field-programmable gate arrays (FPGAs)
time-mode

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Published Papers (6 papers)

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Research

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17 pages, 23351 KiB

Open AccessArticle

FPGA Readout for Frequency-Multiplexed Array of Micromechanical Resonators for Sub-Terahertz Imaging

by Leonardo Gregorat, Marco Cautero, Alessandro Pitanti, Leonardo Vicarelli, Monica La Mura, Alvise Bagolini, Rudi Sergo, Sergio Carrato and Giuseppe Cautero

Sensors 2024, 24(22), 7276; https://doi.org/10.3390/s24227276 - 14 Nov 2024

Viewed by 2028

Abstract

Field programmable gate arrays (FPGAs) have not only enhanced traditional sensing methods, such as pixel detection (CCD and CMOS), but also enabled the development of innovative approaches with significant potential for particle detection. This is particularly relevant in terahertz (THz) ray detection, where microbolometer-based focal plane arrays (FPAs) using microelectromechanical (MEMS) resonators are among the most promising solutions. Designing high-performance, high-pixel-density sensors is challenging without FPGAs, which are crucial for deterministic parallel processing, fast ADC/DAC control, and handling large data throughput. This paper presents a MEMS-resonator detector, fully managed via an FPGA, capable of controlling pixel excitation and tracking resonance-frequency shifts due to radiation using parallel digital lock-in amplifiers. The innovative FPGA architecture, based on a lock-in matrix, enhances the open-loop readout technique by a factor of 32. Measurements were performed on a frequency-multiplexed, 256-pixel sensor designed for imaging applications. Full article

(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)

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19 pages, 11477 KiB

Open AccessArticle

Design of an FPGA-Based Controller for Fast Scanning Probe Microscopy

by Leonardo Gregorat, Marco Cautero, Sergio Carrato, Dario Giuressi, Mirco Panighel, Giuseppe Cautero and Friedrich Esch

Sensors 2024, 24(18), 6108; https://doi.org/10.3390/s24186108 - 21 Sep 2024

Viewed by 1187

Abstract

Atomic-scale imaging using scanning probe microscopy is a pivotal method for investigating the morphology and physico-chemical properties of nanostructured surfaces. Time resolution represents a significant limitation of this technique, as typical image acquisition times are on the order of several seconds or even a few minutes, while dynamic processes—such as surface restructuring or particle sintering, to be observed upon external stimuli such as changes in gas atmosphere or electrochemical potential—often occur within timescales shorter than a second. In this article, we present a fully redesigned field programmable gate array (FPGA)-based instrument that can be integrated into most commercially available standard scanning probe microscopes. This instrument not only significantly accelerates the acquisition of atomic-scale images by orders of magnitude but also enables the tracking of moving features such as adatoms, vacancies, or clusters across the surface (“atom tracking”) due to the parallel execution of sophisticated control and acquisition algorithms and the fast exchange of data with an external processor. Each of these measurement modes requires a complex series of operations within the FPGA that are explained in detail. Full article

(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)

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18 pages, 17232 KiB

Open AccessArticle

High Spatial Resolution Detector System Based on Reconfigurable Dual-FPGA Approach for Coincidence Measurements

by Marco Cautero, Fabio Garzetti, Nicola Lusardi, Rudi Sergo, Luigi Stebel, Andrea Costa, Gabriele Bonanno, Enrico Ronconi, Angelo Geraci, Igor Píš, Elena Magnano, Maddalena Pedio and Giuseppe Cautero

Sensors 2024, 24(16), 5233; https://doi.org/10.3390/s24165233 - 13 Aug 2024

Viewed by 1249

Abstract

Time-resolved spectroscopic and electron–ion coincidence techniques are essential to study dynamic processes in materials or chemical compounds. For this type of analysis, it is necessary to have detectors capable of providing, in addition to image-related information, the time of arrival for each individual detected particle (“x, y, time”). The electronics capable of handling such sensors must meet requirements achievable only with time-to-digital converters (TDC) with a resolution on the order of tens of picoseconds and the use of a field-programmable gate array (FPGA) to manage data acquisition and transmission. This study introduces the design and implementation of an innovative TDC based on two FPGAs working symbiotically with different tasks: the first (AMD/Xilinx Artix^® 7) directly implements a TDC, aiming for a temporal precision of 12 picoseconds, while the second (Intel Cyclone^® 10) manages the acquisition and connectivity with the external world. The TDC has been optimized to operate on eight channels (+ sync) simultaneously but is potentially extendable to a greater number of channels, making it particularly suitable for coincidence measurements where it is necessary to temporally correlate multiple pieces of information from various measurement systems. Full article

(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)

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10 pages, 2235 KiB

Open AccessCommunication

FFT-Based Simultaneous Calculations of Very Long Signal Multi-Resolution Spectra for Ultra-Wideband Digital Radio Frequency Receiver and Other Digital Sensor Applications

by Chen Wu and Michael Low

Sensors 2024, 24(4), 1207; https://doi.org/10.3390/s24041207 - 13 Feb 2024

Cited by 2 | Viewed by 1646

Abstract

The discrete Fourier transform (DFT) is the most commonly used signal processing method in modern digital sensor design for signal study and analysis. It is often implemented in hardware, such as a field programmable gate array (FPGA), using the fast Fourier transform (FFT) algorithm. The frequency resolution (i.e., frequency bin size) is determined by the number of time samples used in the DFT, when the digital sensor’s bandwidth is fixed. One can vary the sensitivity of a radio frequency receiver by changing the number of time samples used in the DFT. As the number of samples increases, the frequency bin width decreases, and the digital receiver sensitivity increases. In some applications, it is useful to compute an ensemble of FFT lengths; e.g.,

2^{P - j}

for

j = 0, 1, 2, \dots, J

, where

j

is defined as the spectrum level with frequency resolution

2^{j} \cdot Δ f

. Here

Δ f

is the frequency resolution at

j = 0

. However, calculating all of these spectra one by one using the conventional FFT method would be prohibitively time-consuming, even on a modern FPGA. This is especially true for large values of

P

; e.g.,

P \geq 20

. The goal of this communication is to introduce a new method that can produce multi-resolution spectrum lines corresponding to sample lengths

2^{P - j}

for all

J + 1

levels, concurrently, while one long

2^{P}

-length FFT is being calculated. That is, the lower resolution spectra are generated naturally as by-products during the computation of the

2^{P}

-length FFT, so there is no need to perform additional calculations in order to obtain them. Full article

(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)

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15 pages, 4217 KiB

Open AccessArticle

Design of A High-Precision Component-Type Vertical Pendulum Tiltmeter Based on FPGA

by Xin Xu, Zheng Chen, Hong Li, Shigui Ma, Liheng Wu, Wenbo Wang, Yunkai Dong and Weiwei Zhan

Sensors 2023, 23(18), 7998; https://doi.org/10.3390/s23187998 - 20 Sep 2023

Cited by 4 | Viewed by 1713

Abstract

This paper presents a high-precision component-type vertical pendulum tiltmeter based on an FPGA (Field Programmable Gate Array) that improves the utility and reliability of geophysical field tilt observation instruments. The system is designed for rapid deployment and offers flexible and efficient adaptability. It comprises a pendulum body, a triangular platform, a locking motor and sealing cover, a ratiometric measurement bridge, a high-speed ADC, and an FPGA embedded system. The pendulum body is a plumb-bob-type single-suspension wire vertical pendulum capable of measuring ground tilt in two orthogonal directions simultaneously. It is installed on a triangular platform, sealed as a whole, and equipped with a locking motor to withstand a free-fall impact of 2 m. The system utilizes a differential capacitance ratio bridge in the measurement circuit, replacing analog circuits with high-speed AD sampling and FPGA digital signal processing technology. This approach reduces hardware expenses and interferences from active devices. The system also features online compilation functionality for flexible measurement parameter settings, high reliability, ease of use, and rapid deployment without the need for professional technical personnel. The proposed tiltmeter holds significant importance for further research in geophysics. Full article

(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)

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Review

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32 pages, 6429 KiB

Open AccessReview

Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons

by Yuanxin Su, Kah Phooi Seng, Li Minn Ang and Jeremy Smith

Sensors 2023, 23(22), 9254; https://doi.org/10.3390/s23229254 - 17 Nov 2023

Cited by 4 | Viewed by 5063

Abstract

Binary neural networks (BNNs) are variations of artificial/deep neural network (ANN/DNN) architectures that constrain the real values of weights to the binary set of numbers {−1,1}. By using binary values, BNNs can convert matrix multiplications into bitwise operations, which accelerates both training and inference and reduces hardware complexity and model sizes for implementation. Compared to traditional deep learning architectures, BNNs are a good choice for implementation in resource-constrained devices like FPGAs and ASICs. However, BNNs have the disadvantage of reduced performance and accuracy because of the tradeoff due to binarization. Over the years, this has attracted the attention of the research community to overcome the performance gap of BNNs, and several architectures have been proposed. In this paper, we provide a comprehensive review of BNNs for implementation in FPGA hardware. The survey covers different aspects, such as BNN architectures and variants, design and tool flows for FPGAs, and various applications for BNNs. The final part of the paper gives some benchmark works and design tools for implementing BNNs in FPGAs based on established datasets used by the research community. Full article

(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)

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