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Energies
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Safety Design and Management of Power Devices including Gate-Drivers
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Safety Design and Management of Power Devices including Gate-Drivers

A special issue of Energies (ISSN 1996-1073). This special issue belongs to the section "F: Electrical Engineering".

Deadline for manuscript submissions: closed (15 April 2023) | Viewed by 11758

Special Issue Editor

Dr. Frédéric Richardeau

E-Mail Website
Guest Editor
Energy Conversion and Plasma Laboratory, University of Toulouse III, 31071 Toulouse, France
Interests: robustness and failure mode analysis of power devices; diagnosis and smart gate-driver management; hybrid and monolithic integration; safety design and management of power devices and topologies; fault handling and reconfiguration; fail-safe topologies; fault-tolerant topologies including new redundant structures

Special Issue Information

Dear Colleagues,

Power devices play a major role in power converter performance. However, most of them are typically not tolerant against accidental short-circuit and overvoltage events. The same applies to long-term or cyclic electrical and thermal overloads. Yet, robustness is an essential feature to be addressed in an increasing number of applications.

There are multiple solutions that tackle both the structure of the power device itself (extreme operation capabilities, fail-safe mode) and its surrounding environment (fast detection, offline/online embedded diagnosis/health monitoring and gate-driver management) as well as its circuit environment (ultimate fail-safe disconnection or bypass).

The aim of this Special Issue is to gather a selection of the best papers on the topic. Priority will be given to contributions dealing with wide bandgap technologies (SiC BJT/JFET/MOSFET devices and GaN HEMT devices) as well as advanced or innovative silicon structures.

Dr. Frédéric Richardeau
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Energies is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • increased short-circuit capability
  • increased avalanche capability
  • increased robustness
  • health monitoring and diagnosis (offline/online)
  • aging real-time prognostics (offline/online)
  • safe failure mode
  • fast and robust short-circuit detection
  • smart gate-driver management
  • passive integrated fuse (monolithic and hybrid technologies)
  • active fuse (monolithic and hybrid technologies)

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Published Papers (3 papers)

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Research

12 pages, 7075 KiB  
Article
Gate Current in p-GaN Gate HEMTs as a Channel Temperature Sensitive Parameter: A Comparative Study between Schottky- and Ohmic-Gate GaN HEMTs
by Alessandro Borghese, Alessandro Di Costanzo, Michele Riccio, Luca Maresca, Giovanni Breglio and Andrea Irace
Energies 2021, 14(23), 8055; https://doi.org/10.3390/en14238055 - 2 Dec 2021
Cited by 10 | Viewed by 5158
Abstract
In this work, a comparison between the gate-driving requirements of p-GaN HEMTs with gate contact of Schottky and Ohmic type is presented. Furthermore, the presence of a gate current of different magnitude is experimentally verified for both types of devices. Successively, the possibility [...] Read more.
In this work, a comparison between the gate-driving requirements of p-GaN HEMTs with gate contact of Schottky and Ohmic type is presented. Furthermore, the presence of a gate current of different magnitude is experimentally verified for both types of devices. Successively, the possibility of using the gate current as a temperature-sensitive parameter and its monitoring during real circuit operation is proposed. The viability of monitoring the gate current without introducing additional complexity in the gate driver is examined through experimental measurements on commercially available p-GaN HEMTs. Full article
(This article belongs to the Special Issue Safety Design and Management of Power Devices including Gate-Drivers)
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18 pages, 7082 KiB  
Article
VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode
by Yazan Barazi, Frédéric Richardeau, Wadia Jouha and Jean-Michel Reynes
Energies 2021, 14(23), 7960; https://doi.org/10.3390/en14237960 - 29 Nov 2021
Cited by 4 | Viewed by 3095
Abstract
This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either [...] Read more.
This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON. Full article
(This article belongs to the Special Issue Safety Design and Management of Power Devices including Gate-Drivers)
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27 pages, 11023 KiB  
Article
Cascaded Smart Gate Drivers for Modular Multilevel Converters Control: A Decentralized Voltage Balancing Algorithm
by Corentin Darbas, Jean-Christophe Olivier, Nicolas Ginot, Frédéric Poitiers and Christophe Batard
Energies 2021, 14(12), 3589; https://doi.org/10.3390/en14123589 - 16 Jun 2021
Cited by 5 | Viewed by 2636
Abstract
Recent Modular Multilevel Converter (MMC) topology allows for drastic improvements in power electronic conversion such as higher energy quality, lower power semiconductors electrical stress, decreased Electro-Magnetic Interferences (EMI), and reduced switching losses. MMC is widely used in High Voltage Direct-Current (HVDC) transmissions as [...] Read more.
Recent Modular Multilevel Converter (MMC) topology allows for drastic improvements in power electronic conversion such as higher energy quality, lower power semiconductors electrical stress, decreased Electro-Magnetic Interferences (EMI), and reduced switching losses. MMC is widely used in High Voltage Direct-Current (HVDC) transmissions as it offers, theoretically, no voltage limit. However, its control electronic structure is not modular itself. Especially, the insulation voltage between the submodule gate drivers’ primaries and secondaries depends on the number of submodules. The converter voltage levels cannot be increased without designing all gate driver isolations again. To solve that issue, the novel concept of distributed galvanic insulation is introduced for multilevel converters. The submodule’s gate drivers are daisy-chained, which naturally reduces the insulation voltage to the submodule capacitor voltage, regardless of the number of submodules. The MMC becomes truly modular as the number of submodules can be increased without impacting on the previous control electronic circuit. Such an innovative control structure weakens the link between the main control unit and the gate drivers. This inherent structural problem can be solved through the use of Smart-Gate Drivers (SGD), as they are often equipped with fast and bidirectional communication channels, while highly increasing the converter reliability. The innovation proposed in that work is the involvement of smart gate drivers in the distributed galvanic insulation-based MMC control and monitoring. First, the numerous benefits of smart gate drivers are discussed. Then, an innovative Voltage Balancing Algorithm directly integrated on the chained gate drivers is proposed and detailed. It features a tunable parameter, offering a trade-off between accurate voltage balancing and execution time. The proposed embedded algorithm features a low execution time due to simultaneous voltage comparisons. Such an algorithm is executed by the gate drivers themselves, relieving the main control unit in an original decentralized control scheme. A simulation model of a multi-megawatts three-phase grid-tied MMC inverter is realized, allowing validation of the proposed algorithm. Matlab/Simulink logic blocs allow us to simulate a typical CPLD/FPGA component, often embedded on smart gate drivers. The converter with the proposed embedded algorithm is simulated in steady-state and during load impact. The controlled delay and slew rate inferred by the algorithm do not disturb the converter behavior, allowing its conceptual validation. Full article
(This article belongs to the Special Issue Safety Design and Management of Power Devices including Gate-Drivers)
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