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Recent Advances in Programmable Networks: Challenges and Opportunities

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Networks".

Deadline for manuscript submissions: closed (31 December 2022) | Viewed by 9743

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Special Issue Editors

Dr. Elisa Rojas

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Guest Editor

Information and Communication Technologies engineering, University of Alcala, Alcalá de Henares Madrid, Madrid, Spain
Interests: SDN; NFV; routing; Ethernet; IoT; 5G; data center networks

Dr. Sándor Laki

E-Mail Website
Guest Editor

ELTE, Eötvös Loránd University, Budapest, Hungary
Interests: SDN; programmable data-planes; P4; in-network computing; QoS; resource sharing

Dr. Christian Esteve Rothenberg

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Guest Editor

Department of Computer Engineering and Automation, University of Campinas, Albert Einstein - 400, Cidade Universitária Zeferino Vaz CEP: 13083-852, Campinas, SP, Brazil
Interests: network architectures; SDN; NFV; P4; machine learning
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

During the last decade, recent paradigms and technologies, like software-defined networking (SDN), network function virtualization (NFV), and P4, have boosted network programmability, hence fostering the development of new network services and functions, many of which are core pillars in next-generation networks (like 5G and beyond).

The main aim of this Special Issue is to seek high-quality submissions related to recent advances, challenges, and/or opportunities in the field of programmable networks. Topics of interest include, but are not limited to, the following:

New services and functionality developed for SDN/NFV environments
Network design with P4 or XDP
Network programmability towards 5G and beyond
Hybrid SDN networks
Programmable network (e.g., SDN, NFV, and P4) security
Use cases, testbeds, and demonstrators based on network programmability
Challenges and opportunities of programmable networks
Surveys about particular areas of programmable networks

Technical Program Committee Members:

1. Doctor Rashid Amin University of Engineering and Technology
2. Mr. A. S. M. Asadujjaman CIISE, Concordia University, Montreal, QC Canada

Dr. Elisa Rojas
Dr. Sándor Laki
Dr. Christian Esteve Rothenberg
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

Programmability
Programmable networks
SDN
NFV
P4
XDP
Hybrid networks
5G
NGN

Published Papers (5 papers)

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Research

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22 pages, 1240 KiB

Open AccessArticle

Application-Aware Flow Forwarding Service for SDN-Based Data Centers

by Jose E. Lozano-Rizk, Jose E. Gonzalez-Trejo, Raul Rivera-Rodriguez, Andrei Tchernykh, Salvador Villarreal-Reyes and Alejandro Galaviz-Mosqueda

Electronics 2022, 11(23), 3882; https://doi.org/10.3390/electronics11233882 - 24 Nov 2022

Viewed by 1155

Abstract

Security and Quality of Service (QoS) in communication networks are critical factors supporting end-to-end dataflows in data centers. On the other hand, it is essential to provide mechanisms that enable different treatments for applications requiring sensitive data transfer. Both applications’ requirements can vary according to their particular needs. To achieve their goals, it is necessary to provide services so that each application can request both the quality of service and security services dynamically and on demand. This article presents QoSS, an API web service to provide both Quality of Service and Security for applications through software-defined networks. We developed a prototype to conduct a case study to provide QoS and security. QoSS finds the optimal end-to-end path according to four optimization rules: bandwidth-aware, delay-aware, security-aware, and application requirements (considering the bandwidth, delay, packet loss, jitter, and security level of network nodes). Simulation results showed that our proposal improved end-to-end application data transfer by an average of 45%. Besides, it supports the dynamic end-to-end path configuration according to the application requirements. QoSS also logs each application’s data transfer events to enable further analysis. Full article

(This article belongs to the Special Issue Recent Advances in Programmable Networks: Challenges and Opportunities)

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15 pages, 1840 KiB

Open AccessArticle

A Programmable SRv6 Processor for SFC

by Zhongpei Liu, Gaofeng Lv, Jichang Wang and Xiangrui Yang

Electronics 2022, 11(18), 2920; https://doi.org/10.3390/electronics11182920 - 15 Sep 2022

Viewed by 1518

Abstract

A reconfigurable match table (RMT) is a programmable pipeline architecture for packet processing. In order to enable the programmable data plane to support segment routing IPv6 (SRv6) and other network protocols, this paper extends the deparser based on RMT. The paper uses the extended deparser and two RMT pipelines to build a protocol-independent network slice programmable data plane model named as the programmable SRv6 processor. We design it primarily for segment identifier (SID) processing of SRv6. We have proved that it can support SRv6, multiple semantics for SIDs, micro segment ID, multi-protocol label switching, and a service function chain (SFC). This architecture has broad application prospects. Experimental results on an FPGA showed that the extended deparser could achieve 100 Gbps throughput for 512B packets with few resources. Full article

(This article belongs to the Special Issue Recent Advances in Programmable Networks: Challenges and Opportunities)

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27 pages, 1032 KiB

Open AccessArticle

Model Checking-Based Performance Prediction for P4

by Dániel Lukács, Gergely Pongrácz and Máté Tejfel

Electronics 2022, 11(14), 2117; https://doi.org/10.3390/electronics11142117 - 6 Jul 2022

Cited by 1 | Viewed by 1344

Abstract

Next-generation networks focus on scale and scope at the price of increasing complexity, leading to difficulties in network design and planning. As a result, anticipating all hardware- and software-related factors of network performance requires time-consuming and expensive benchmarking. This work presents a framework and software tool for automatically inferring the performance of P4 programmable network switches based on the P4 source code and probabilistic models of the execution environment with the hope of eliminating the requirement of the costly set-up of networked hardware and conducting benchmarks. We designed the framework using a top-down approach. First, we transform high-level P4 programs into a representation that can be refined incrementally by adding probabilistic environment models of increasing levels of complexity in order to improve the estimation precision. Then, we use the PRISM probabilistic model checker to perform the heavy weight calculations involved in static performance prediction. We present a formalization of the performance estimation problem, detail our solution, and illustrate its usage and validation through a case study conducted using a small P4 program and the P4C-BM reference switch. We show that the framework is already capable of performing estimation, and it can be extended with more concrete information to yield better estimates. Full article

(This article belongs to the Special Issue Recent Advances in Programmable Networks: Challenges and Opportunities)

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16 pages, 910 KiB

Open AccessArticle

Reliability Aware Multiple Path Installation in Software-Defined Networking

by Syed Mohsan Raza, Shohreh Ahvar, Rashid Amin and Mudassar Hussain

Electronics 2021, 10(22), 2820; https://doi.org/10.3390/electronics10222820 - 17 Nov 2021

Cited by 4 | Viewed by 1992

Abstract

Link failures frequently occur in communication networks, which negatively impacts network services delivery. Compared to traditional distributed networks, Software-Defined Networking (SDN) provides numerous benefits for link robustness to avoid services unavailability. To cope with link failures, the existing SDN approaches compute multiple paths and install corresponding flow rules at network switches without considering the reliability value of the primary computed path. This increases computation time, traffic overhead and end-to-end packets delay. This paper proposes a new approach called Reliability Aware Multiple Path Flow Rule (RAF) that calculates links reliability and installs minimum flow rules for multiple paths based on the reliability value of the primary path. RAF has been simulated, evaluated and compared with the existing approaches. The simulation results show that RAF performs better than the existing approaches in terms of computation overhead at the controller and reduces end-to-end packet delay and traffic overhead for flow rules installation. Full article

(This article belongs to the Special Issue Recent Advances in Programmable Networks: Challenges and Opportunities)

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Review

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24 pages, 529 KiB

Open AccessReview

A Comprehensive Survey of In-Band Control in SDN: Challenges and Opportunities

by David Carrascal, Elisa Rojas, Jose M. Arco, Diego Lopez-Pajares, Joaquin Alvarez-Horcajo and Juan Antonio Carral

Electronics 2023, 12(6), 1265; https://doi.org/10.3390/electronics12061265 - 7 Mar 2023

Cited by 3 | Viewed by 2429

Abstract

Software-Defined Networking (SDN) is a thriving networking architecture that has gained popularity in recent years, particularly as an enabling technology to foster paradigms like edge computing. SDN separates the control and data planes, which are later on synchronised via a control protocol such as OpenFlow. In-band control is a type of SDN control plane deployment in which the control and data planes share the same physical network. It poses several challenges, such as security vulnerabilities, network congestion, or data loss. Nevertheless, despite these challenges, in-band control also presents significant opportunities, including improved network flexibility and programmability, reduced costs, and increased reliability. Benefiting from the previous advantages, diverse in-band control designs exist in the literature, with the objective of improving the operation of SDN networks. This paper surveys the different approaches that have been proposed so far towards the advance in in-band SDN control, based on four main categories: automatic routing, fast failure recovery, network bootstrapping, and distributed control. Across these categories, detailed summary tables and comparisons are presented, followed by a discussion on current trends a challenges in the field. Our conclusion is that the use of in-band control in SDN networks is expected to drive innovation and growth in the networking industry, but efforts for holistic and full-fledged proposals are still needed. Full article

(This article belongs to the Special Issue Recent Advances in Programmable Networks: Challenges and Opportunities)

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