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Electronics
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Advanced High-Performance Integrated Circuits for Sensing Technologies and IoT Applications
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Advanced High-Performance Integrated Circuits for Sensing Technologies and IoT Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 July 2024) | Viewed by 3468

Special Issue Editor

Dr. Alireza Saberkari

E-Mail Website
Guest Editor
Department of Electrical Engineering, Linköping University, 581 83 Linköping, Sweden
Interests: analog/RF microelectronics; low-power microsystems; on-chip power management; energy harvesting; wireless energy/power transfer; low-power transceivers

Special Issue Information

Dear Colleagues,

Today, sensing technologies and sensor-enabled devices are gaining attention, with a wide range of potential applications, ranging from internet of things (IoT), intelligent transportation systems (ITS) to personalized mobile healthcare. These tasks are mostly through wireless connections. Power dissipation, bandwidth efficiency, design flexibility, and scalability are important factors for these systems. However, there are still many challenges that must be addressed. Examples of such challenges in these technologies include effect of size constraints on the performance in many applications, mW-level power consumption of electronic circuits which limits the sensory systems' lifetime, compatibility with existing communication protocols, etc.

Within this framework, the aim of this Special Issue is to encourage researchers to submit their original research and reviews, addressing the latest developments, innovations, and challenges related to the design of advanced high-performance integrated circuits for sensing technologies and IoT applications.

Topics of interest for this Special Issue include, but are not limited to, the following areas:

  • Ultra-low power wireless communication circuits enabling IoT applications
  • High efficient load modulation techniques and backscattering solutions
  • Energy harvesting and power management solutions for IoT devices
  • Integrated circuits with wireless power transfer capability
  • Ultra-low power sensor readout circuits and systems
  • High-performance heterogeneous solutions for emerging technologies
  • Multi-sensor miniaturized circuits and systems

Dr. Alireza Saberkari
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • energy harvesting
  • ultra-low-power IoT
  • wakeup receivers
  • ultra-low power transceivers
  • backscattering
  • load modulation
  • sensing technologies
  • sensor readout circuits
  • low power integrated circuits

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Published Papers (4 papers)

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8 pages, 2255 KiB  
Article
System-Level Implementation of a Parallel-Path Hybrid Switched-Capacitor Amplifier with an Embedded Successive Approximation Register for IoT Applications
by Javad Bagheri Asli, Alireza Saberkari and Atila Alvandpour
Electronics 2024, 13(17), 3447; https://doi.org/10.3390/electronics13173447 - 30 Aug 2024
Viewed by 314
Abstract
A system-level implementation of a parallel-path hybrid switched-capacitor amplifier is presented in this paper. The proposed parallel-path amplifier incorporates a gain and slew rate-boosting switching path in parallel with an embedded assisted SAR path, aiming for IoT applications. As an alternative concept to [...] Read more.
A system-level implementation of a parallel-path hybrid switched-capacitor amplifier is presented in this paper. The proposed parallel-path amplifier incorporates a gain and slew rate-boosting switching path in parallel with an embedded assisted SAR path, aiming for IoT applications. As an alternative concept to the conventional analog topologies, the proposed amplifier combines nonlinear and linear paths to provide coarse and fine amplifications. In the coarse amplification, a high current is provided through a switching path for a fraction of time, which improves the slew rate and open-loop DC gain without adding significant static current. Moreover, high accuracy is achieved through the embedded assisted SAR path, which provides a resolution of 1/2N. In addition, each extra bit of the embedded SAR path improves the total open-loop DC gain by 6 dB. The theory of operation is performed to study how the switching and assisted SAR paths can enhance the amplifier’s settling error. In addition, an existence trade-off between the coarse amplification error and the capacitive digital-to-analog converter’s number of bits is investigated. The theory and system-level simulation show that the gain and slewing restrictions of the conventional topologies, especially in advanced CMOS technology, can be handled much easier by this parallel combination, where the switching path and assisted SAR path combination provides a high slewing capability and high DC open-loop gain. Full article
(This article belongs to the Special Issue Advanced High-Performance Integrated Circuits for Sensing Technologies and IoT Applications)
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24 pages, 13367 KiB  
Article
Compact Walsh–Hadamard Transform-Driven S-Box Design for ASIC Implementations
by Omer Tariq, Muhammad Bilal Akram Dastagir and Dongsoo Han
Electronics 2024, 13(16), 3148; https://doi.org/10.3390/electronics13163148 - 9 Aug 2024
Viewed by 697
Abstract
With the exponential growth of the Internet of Things (IoT), ensuring robust end-to-end encryption is paramount. Current cryptographic accelerators often struggle with balancing security, area efficiency, and power consumption, which are critical for compact IoT devices and system-on-chips (SoCs). This work presents a [...] Read more.
With the exponential growth of the Internet of Things (IoT), ensuring robust end-to-end encryption is paramount. Current cryptographic accelerators often struggle with balancing security, area efficiency, and power consumption, which are critical for compact IoT devices and system-on-chips (SoCs). This work presents a novel approach to designing substitution boxes (S-boxes) for Advanced Encryption Standard (AES) encryption, leveraging dual quad-bit structures to enhance cryptographic security and hardware efficiency. By utilizing Algebraic Normal Forms (ANFs) and Walsh–Hadamard Transforms, the proposed Register Transfer Level (RTL) circuitry ensures optimal non-linearity, low differential uniformity, and bijectiveness, making it a robust and efficient solution for ASIC implementations. Implemented on 65 nm CMOS technology, our design undergoes rigorous statistical analysis to validate its security strength, followed by hardware implementation and functional verification on a ZedBoard. Leveraging Cadence EDA tools, the ASIC implementation achieves a central circuit area of approximately 199 μm2. The design incurs a hardware cost of roughly 80 gate equivalents and exhibits a maximum path delay of 0.38 ns. Power dissipation is measured at approximately 28.622 μW with a supply voltage of 0.72 V. According to the ASIC implementation on the TSMC 65 nm process, the proposed design achieves the best area efficiency, approximately 66.46% better than state-of-the-art designs. Full article
(This article belongs to the Special Issue Advanced High-Performance Integrated Circuits for Sensing Technologies and IoT Applications)
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17 pages, 2456 KiB  
Article
Spatial Transformation Accelerator with Parallel Data Access Scheme for Sample Reconstruction
by Rihards Novickis, Edgars Lielāmurs, Daniels Jānis Justs, Andrejs Cvetkovs and Kaspars Ozols
Electronics 2024, 13(5), 922; https://doi.org/10.3390/electronics13050922 - 28 Feb 2024
Viewed by 677
Abstract
Spatial image transformation is a commonly used component in many image processing pipelines. It enables the correction of optical distortions, image registration onto a common reference plane, electronic image stabilisation, digital zoom, video mosaicking, etc. With the growing tendency to embed image processing [...] Read more.
Spatial image transformation is a commonly used component in many image processing pipelines. It enables the correction of optical distortions, image registration onto a common reference plane, electronic image stabilisation, digital zoom, video mosaicking, etc. With the growing tendency to embed image processing in low-power devices, attaining an efficient transformation solution becomes increasingly decisive. Furthermore, interpolation is the key operation in achieving the high quality of the transformed data from the original data. Fortunately, different implementations have already seen several efficiency improvements in recent years. However, interpolation relies on sampling a set of neighbouring points from memory, which has yet to be addressed efficiently for smaller computational platforms with limited memory resources. In this work, we derive a generic mathematical model and circuit design principles for the spatial transformation accelerator design for N-dimensional data. Furthermore, we present an efficient simultaneous access scheme for high-quality signal reconstruction. Finally, the introduced ideas are verified in field programmable gate arrays using one-dimensional and two-dimensional data transformation use cases. The presented solution is able to transform images with sizes ranging from 256 × 256 to 8192 × 8192 and achieves a transfer rate of 275 frames per second with 512 × 512 images. Full article
(This article belongs to the Special Issue Advanced High-Performance Integrated Circuits for Sensing Technologies and IoT Applications)
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21 pages, 5758 KiB  
Article
CMOS Wireless Hybrid Transceiver Powered by Integrated Photodiodes for Ultra-Low-Power IoT Applications
by Sasan Nikseresht, Daniel Fernández, Jordi Cosp-Vilella, Irina Selin-Lorenzo and Jordi Madrenas
Electronics 2024, 13(1), 28; https://doi.org/10.3390/electronics13010028 - 20 Dec 2023
Viewed by 1112
Abstract
In this article, a communication platform for a self-powered integrated light energy harvester based on a wireless hybrid transceiver is proposed. It consists of an optical receiver and a reconfigurable radio frequency (RF) transmitter. The hybrid optical/RF communication approach improves load balancing, energy [...] Read more.
In this article, a communication platform for a self-powered integrated light energy harvester based on a wireless hybrid transceiver is proposed. It consists of an optical receiver and a reconfigurable radio frequency (RF) transmitter. The hybrid optical/RF communication approach improves load balancing, energy efficiency, security, and interference reduction. A light beam for communication in the downlink, coupled with a 1 MHz radio frequency signal for the uplink, offers a small area and ultra-low-power consumption design for Smart Dust/IoT applications. The optical receiver employs a new charge-pump-based technique for the automatic acquisition of a reference voltage, enabling compensation for comparator offset errors and variations in DC-level illumination. On the uplink side, the reconfigurable transmitter supports OOK/FSK/BPSK data modulation. Electronic components and the energy harvester, including integrated photodiodes, have been designed, fabricated, and experimentally tested in a 0.18 µm triple-well CMOS technology in a 1.5 × 1.3 mm2 chip area. Experiments show the correct system behavior for general and pseudo-random stream input data, with a minimum pulse width of 50 µs and a data transmission rate of 20 kb/s for the optical receiver and 1 MHz carrier frequency. The maximum measured power of the signal received from the transmitter is approximately −18.65 dBm when using a light-harvested power supply. Full article
(This article belongs to the Special Issue Advanced High-Performance Integrated Circuits for Sensing Technologies and IoT Applications)
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