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Electronics
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Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges
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Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 January 2022) | Viewed by 6355

Special Issue Editors

Dr. Sang-Woo Jun

E-Mail Website
Guest Editor
Computer Science Department, Donald Bren School of Information and Computer Sciences, University of California, Irvine, CA 92697, USA
Interests: systems; FPGA; storage system; big data
Prof. Dr. Yeseong Kim

E-Mail Website
Guest Editor
Department of Information and Communication Engineering, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu 42988, Korea
Interests: computer software; computer programming; embedded systems; computer architecture
Dr. Jisung Park

E-Mail Website
Guest Editor
Department of Information Technology and Electrical Engineering (D-ITET), ETH Zürich, Gloriastrasse 35, 8092 Zürich, Switzerland
Interests: computer architecture; memory systems; storage systems; system security

Special Issue Information

Dear Colleagues,

Reconfigurable hardware accelerators such as FPGAs are seeing big changes in their role and importance in the computing landscape, evolving beyond mere prototyping platforms for ASICs and becoming a prominent technology enabling continued performance scaling.

The strength of reconfigurable hardware acceleration comes from its high performance and power efficiency relative to general-purpose architectures, as well as the ability to quickly adapt its components according to application requirements after deployment.

There is a wide range of pressing, critical research topics spanning from application-specific accelerator design, design methodologies, to programming models, abstractions, and runtime environments to make reconfigurable accelerators available and manageable.

This call seeks various software/hardware solutions for reconfigurable accelerators, including traditional FPGA designs for edge and high-performance computing, as well as revolutionary technology, e.g., programmable processing in-memory architectures.

Dr. Sang-Woo Jun
Prof. Dr. Yeseong Kim
Dr. Jisung Park
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • reconfigurable hardware accelerators
  • novel system architectures with reconfigurable acceleration
  • trends and future projections
  • role of reconfigurable hardware accelerators in important applications

Published Papers (2 papers)

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Research

17 pages, 1025 KiB  
Article
Efficient Architectures for Full Hardware Scrypt-Based Block Hashing System
by Duc Khai Lam, Vu Trung Duong Le and Thi Hong Tran
Electronics 2022, 11(7), 1068; https://doi.org/10.3390/electronics11071068 - 28 Mar 2022
Cited by 5 | Viewed by 3289
Abstract
The password-based key derivation function Scrypt has been employed for many services and applications due to its protection ability. It has also been employed as a proof-of-work algorithm in blockchain implementations. Although this cryptographic hash function provides very high security, the processing speed [...] Read more.
The password-based key derivation function Scrypt has been employed for many services and applications due to its protection ability. It has also been employed as a proof-of-work algorithm in blockchain implementations. Although this cryptographic hash function provides very high security, the processing speed and power consumption to generate a hashed block for the blockchain network are low-performance. In this paper, a high-speed and low-power hardware architecture of the Scrypt function is proposed to generate blocks for the Scrypt-based blockchain network. This architecture minimizes the number of main computational blocks to reduce the power consumption of the system. In addition, the proposed sharing resources and pipelined architectures make the calculation speed increase significantly while the hardware cost is reduced by half compared to the parallel non-pipelined architecture. The full hardware system is designed and implemented on Xilinx Virtex-7 and Aveo U280 FPGA platforms. The hash rate of the proposed system reaches 229.1 kHash/s. Its hash rate, hardware and energy efficiencies are much higher than those of the other works implemented on FPGA and GPU hardware platforms. The proposed hardware architecture is also successfully implemented in an ASIC design using ROHM 180 nm CMOS technology. Full article
(This article belongs to the Special Issue Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges)
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18 pages, 768 KiB  
Article
MobileNets Can Be Lossily Compressed: Neural Network Compression for Embedded Accelerators
by Se-Min Lim and Sang-Woo Jun
Electronics 2022, 11(6), 858; https://doi.org/10.3390/electronics11060858 - 9 Mar 2022
Cited by 3 | Viewed by 2389
Abstract
Although neural network quantization is an imperative technology for the computation and memory efficiency of embedded neural network accelerators, simple post-training quantization incurs unacceptable levels of accuracy degradation on some important models targeting embedded systems, such as MobileNets. While explicit quantization-aware training or [...] Read more.
Although neural network quantization is an imperative technology for the computation and memory efficiency of embedded neural network accelerators, simple post-training quantization incurs unacceptable levels of accuracy degradation on some important models targeting embedded systems, such as MobileNets. While explicit quantization-aware training or re-training after quantization can often reclaim lost accuracy, this is not always possible or convenient. We present an alternative approach to compressing such difficult neural networks, using a novel variant of the ZFP lossy floating-point compression algorithm to compress both model weights and inter-layer activations and demonstrate that it can be efficiently implemented on an embedded FPGA platform. Our ZFP variant, which we call ZFPe, is designed for efficient implementation on embedded accelerators, such as FPGAs, requiring a fraction of chip resources per bandwidth compared to state-of-the-art lossy compression accelerators. ZFPe-compressing the MobileNet V2 model with an 8-bit budget per weight and activation results in significantly higher accuracy compared to 8-bit integer post-training quantization and shows no loss of accuracy, compared to an uncompressed model when given a 12-bit budget per floating-point value. To demonstrate the benefits of our approach, we implement an embedded neural network accelerator on a realistic embedded acceleration platform equipped with the low-power Lattice ECP5-85F FPGA and a 32 MB SDRAM chip. Each ZFPe module consumes less than 6% of LUTs while compressing or decompressing one value per cycle, requiring a fraction of the resources compared to state-of-the-art compression accelerators while completely removing the memory bottleneck of our accelerator. Full article
(This article belongs to the Special Issue Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges)
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