Special Issue "Advances in System-on-Chip Design"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 15 June 2021.

Special Issue Editor

Dr. Christian Pilato
E-Mail Website
Guest Editor
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy
Interests: high-level synthesis, reconfigurable systems, and system-on-chip architectures, with emphasis on memory and security aspects

Special Issue Information

Dear Colleagues,

The increasing complexity of modern system-on-chip (SoC) architectures is limited by several contrasting factors such as limited power budgets, design costs, and security concerns. On one hand, the end of Dennard’s scaling limits the number of transistors that can be active at the same time. Thus, designers are promoting specialization, resulting in heterogeneous architectures composed of several processing elements (e.g., general-purpose processors and dedicated hardware accelerators). On the other hand, the scalability of interconnection systems may limit the number of processing elements that can be integrated. Therefore, designers are enforcing regularity by promoting the use of network-on-chip (NoC) interconnection subsystems. This allows the integration of components designed independently.

Heterogeneous SoC architecture can bring significant benefits in terms of performance and energy efficiency. Hence, they are becoming extremely popular in academia and industry. However, there are still several open challenges, especially concerning efficient memory design and protection from cybersecurity threats, which must be addressed by the designers.

The main aim of this Special Issue is to seek high-quality submissions that address emerging challenges in complex SoC architectures, such as the design of specialized accelerators, their integration with pre-existing components, the design of scalable and efficient memory architectures, and the identification of additional vulnerabilities arising from the integration of several different components. The topics of interest include but are not limited to:

  • Novel SoC architectures and design methodologies;
  • Layout- and energy-driven SoC architectures;
  • Design space exploration methods for SoC design;
  • High power density dower electronic systems;
  • High-level synthesis and hardware/software co-design methodologies;
  • Efficient memory architectures for scalable and distributed SoC architectures.;
  • Hardware security and hardware-assisted security in SoC architectures.

Dr. Christian Pilato
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.


  • system-on-chip
  • network-on-chip
  • high-level synthesis
  • hardware/software co-design
  • hardware security

Published Papers (1 paper)

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Open AccessArticle
Antenna on Chip (AoC) Design Using Metasurface and SIW Technologies for THz Wireless Applications
by , , , , and
Electronics 2021, 10(9), 1120; https://doi.org/10.3390/electronics10091120 - 10 May 2021
Viewed by 93
This paper presents the design of a high-performance 0.45–0.50 THz antenna on chip (AoC) for fabrication on a 100-micron GaAs substrate. The antenna is based on metasurface and substrate-integrated waveguide (SIW) technologies. It is constituted from seven stacked layers consisting of copper patch–silicon [...] Read more.
This paper presents the design of a high-performance 0.45–0.50 THz antenna on chip (AoC) for fabrication on a 100-micron GaAs substrate. The antenna is based on metasurface and substrate-integrated waveguide (SIW) technologies. It is constituted from seven stacked layers consisting of copper patch–silicon oxide–feedline–silicon oxide–aluminium–GaAs–copper ground. The top layer consists of a 2 × 4 array of rectangular metallic patches with a row of subwavelength circular slots to transform the array into a metasurface. This essentially enlarges the effective aperture area of the antenna. The antenna is excited using a coplanar waveguide feedline that is sandwiched between the two silicon oxide layers below the patch layer. The proposed antenna structure reduces substrate loss and surface waves. The AoC has dimensions of 0.8 × 0.8 × 0.13 mm3. The results show that the proposed structure greatly enhances the antenna’s gain and radiation efficiency, and this is achieved without compromising its physical size. The antenna exhibits an average gain and efficiency of 6.5 dBi and 65%, respectively, which makes it a promising candidate for emerging terahertz applications. Full article
(This article belongs to the Special Issue Advances in System-on-Chip Design)
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