Special Issue "Advances in System-on-Chip Design"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 4415

Special Issue Editor

Dr. Christian Pilato
E-Mail Website
Guest Editor
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy
Interests: high-level synthesis; reconfigurable systems; system-on-chip architectures, with emphasis on memory and security aspects

Special Issue Information

Dear Colleagues,

The increasing complexity of modern system-on-chip (SoC) architectures is limited by several contrasting factors such as limited power budgets, design costs, and security concerns. On one hand, the end of Dennard’s scaling limits the number of transistors that can be active at the same time. Thus, designers are promoting specialization, resulting in heterogeneous architectures composed of several processing elements (e.g., general-purpose processors and dedicated hardware accelerators). On the other hand, the scalability of interconnection systems may limit the number of processing elements that can be integrated. Therefore, designers are enforcing regularity by promoting the use of network-on-chip (NoC) interconnection subsystems. This allows the integration of components designed independently.

Heterogeneous SoC architecture can bring significant benefits in terms of performance and energy efficiency. Hence, they are becoming extremely popular in academia and industry. However, there are still several open challenges, especially concerning efficient memory design and protection from cybersecurity threats, which must be addressed by the designers.

The main aim of this Special Issue is to seek high-quality submissions that address emerging challenges in complex SoC architectures, such as the design of specialized accelerators, their integration with pre-existing components, the design of scalable and efficient memory architectures, and the identification of additional vulnerabilities arising from the integration of several different components. The topics of interest include but are not limited to:

  • Novel SoC architectures and design methodologies;
  • Layout- and energy-driven SoC architectures;
  • Design space exploration methods for SoC design;
  • High power density dower electronic systems;
  • High-level synthesis and hardware/software co-design methodologies;
  • Efficient memory architectures for scalable and distributed SoC architectures.;
  • Hardware security and hardware-assisted security in SoC architectures.

Dr. Christian Pilato
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • system-on-chip
  • network-on-chip
  • high-level synthesis
  • hardware/software co-design
  • hardware security

Published Papers (4 papers)

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Research

Article
Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs
Electronics 2021, 10(14), 1746; https://doi.org/10.3390/electronics10141746 - 20 Jul 2021
Cited by 2 | Viewed by 720
Abstract
High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and [...] Read more.
High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits. Full article
(This article belongs to the Special Issue Advances in System-on-Chip Design)
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Article
Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications
Electronics 2021, 10(13), 1587; https://doi.org/10.3390/electronics10131587 - 30 Jun 2021
Viewed by 683
Abstract
High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining [...] Read more.
High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design. Full article
(This article belongs to the Special Issue Advances in System-on-Chip Design)
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Article
Compact and Low-Profile On-Chip Antenna Using Underside Electromagnetic Coupling Mechanism for Terahertz Front-End Transceivers
Electronics 2021, 10(11), 1264; https://doi.org/10.3390/electronics10111264 - 25 May 2021
Cited by 8 | Viewed by 795
Abstract
The results presented in this paper show that by employing a combination of metasurface and substrate integrated waveguide (SIW) technologies, we can realize a compact and low-profile antenna that overcomes the drawbacks of narrow-bandwidth and low-radiation properties encountered by terahertz antennas on-chip (AoC). [...] Read more.
The results presented in this paper show that by employing a combination of metasurface and substrate integrated waveguide (SIW) technologies, we can realize a compact and low-profile antenna that overcomes the drawbacks of narrow-bandwidth and low-radiation properties encountered by terahertz antennas on-chip (AoC). In addition, an effective RF cross-shaped feed structure is used to excite the antenna from its underside by coupling, electromagnetically, RF energy through the multi-layered antenna structure. The feed mechanism facilitates integration with the integrated circuits. The proposed antenna is constructed from five stacked layers, comprising metal–silicon–metal–silicon–metal. The dimensions of the AoC are 1 × 1 × 0.265 mm3. The AoC is shown to have an impedance match, radiation gain and efficiency of ≤ −15 dB, 8.5 dBi and 67.5%, respectively, over a frequency range of 0.20–0.22 THz. The results show that the proposed AoC design is viable for terahertz front-end applications. Full article
(This article belongs to the Special Issue Advances in System-on-Chip Design)
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Article
Antenna on Chip (AoC) Design Using Metasurface and SIW Technologies for THz Wireless Applications
Electronics 2021, 10(9), 1120; https://doi.org/10.3390/electronics10091120 - 10 May 2021
Cited by 10 | Viewed by 1120
Abstract
This paper presents the design of a high-performance 0.45–0.50 THz antenna on chip (AoC) for fabrication on a 100-micron GaAs substrate. The antenna is based on metasurface and substrate-integrated waveguide (SIW) technologies. It is constituted from seven stacked layers consisting of copper patch–silicon [...] Read more.
This paper presents the design of a high-performance 0.45–0.50 THz antenna on chip (AoC) for fabrication on a 100-micron GaAs substrate. The antenna is based on metasurface and substrate-integrated waveguide (SIW) technologies. It is constituted from seven stacked layers consisting of copper patch–silicon oxide–feedline–silicon oxide–aluminium–GaAs–copper ground. The top layer consists of a 2 × 4 array of rectangular metallic patches with a row of subwavelength circular slots to transform the array into a metasurface. This essentially enlarges the effective aperture area of the antenna. The antenna is excited using a coplanar waveguide feedline that is sandwiched between the two silicon oxide layers below the patch layer. The proposed antenna structure reduces substrate loss and surface waves. The AoC has dimensions of 0.8 × 0.8 × 0.13 mm3. The results show that the proposed structure greatly enhances the antenna’s gain and radiation efficiency, and this is achieved without compromising its physical size. The antenna exhibits an average gain and efficiency of 6.5 dBi and 65%, respectively, which makes it a promising candidate for emerging terahertz applications. Full article
(This article belongs to the Special Issue Advances in System-on-Chip Design)
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