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Advances in Algorithms and Architectures for Digital Signal Processing
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Advances in Algorithms and Architectures for Digital Signal Processing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 February 2024) | Viewed by 4479

Special Issue Editors

Prof. Dr. Doru Florin Chiper

E-Mail Website
Guest Editor
Technical Sciences Academy of Romania—ASTR, Academy of Romanian Scientists—AOSR, Faculty of Electronics, Telecommunication and Information Technology, “Gheorghe Asachi“ Technical University of Iasi, 700506 Iasi, Romania
Interests: digital signal processing (DSP); adaptive signal processing; blind equalization/identification; fast computational algorithms; parallel and VLSI algorithms and architectures for communications and DSP; high-level DSP design
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Constantin Paleologu

E-Mail Website
Guest Editor
Department of Telecommunications, University Politehnica of Bucharest, 1-3, Iuliu Maniu Blvd., 061071 Bucharest, Romania
Interests: adaptive filters; acoustic echo cancellation; sparse systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In the new era of the digital revolution, optimization and the efficient implementation of the DSP algorithms and architectures are more and more important. We can say that they represent an essential part of the research in many modern applications, e.g., multimedia, big data, IoT, etc.

For real-time implementations of such modern DSP applications, the efficient optimization of such architectures or software implementations is sometimes a critical and challenging issue. For example, real-time multimedia applications have increasingly more performance requirements due to data processing and transmission of huge data volumes at high speeds, with resource constraints specific to portable devices.

This Special Issue focuses on papers that demonstrate how these design challenges can be overcome using innovative solutions.

Topics of interest for this Special Issue include but are not limited to:

  • VLSI signal processing;
  • Signal processing methods for an efficient implementation;
  • Optimization of the VLSI implementation of multimedia blocks;
  • Low-power circuits and systems for DSP applications;
  • Efficient adaptive/learning algorithms (low complexity/fast versions, optimized parameters, etc.);
  • Tensor-based signal processing (efficient decomposition methods, low-rank approximations, etc.);
  • Sparsity-aware algorithms.

Prof. Dr. Chiper Doru Florin
Prof. Dr. Constantin Paleologu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • VLSI signal processing
  • signal processing methods for an efficient implementation
  • optimization of the VLSI implementation of multimedia blocks
  • low-power circuits and systems for DSP applications
  • efficient adaptive/learning algorithms (low complexity/fast versions, optimized parameters, etc.)
  • tensor-based signal processing (efficient decomposition methods, low-rank approximations, etc.)
  • sparsity-aware algorithms

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Further information on MDPI's Special Issue polices can be found here.

Published Papers (4 papers)

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Research

21 pages, 1205 KiB  
Article
On the Regularization of Recursive Least-Squares Adaptive Algorithms Using Line Search Methods
by Cristian-Lucian Stanciu, Cristian Anghel, Ionuț-Dorinel Fîciu, Camelia Elisei-Iliescu, Mihnea-Radu Udrea and Lucian Stanciu
Electronics 2024, 13(8), 1479; https://doi.org/10.3390/electronics13081479 - 13 Apr 2024
Viewed by 707
Abstract
Stereophonic acoustic echo cancellation (SAEC) requires the identification of four unknown impulse responses corresponding to four loudspeaker-to-microphone pairs. Recent developments in the field of adaptive filters for SAEC setups have allowed for the handling of a single complex-valued adaptive impulse response, instead of [...] Read more.
Stereophonic acoustic echo cancellation (SAEC) requires the identification of four unknown impulse responses corresponding to four loudspeaker-to-microphone pairs. Recent developments in the field of adaptive filters for SAEC setups have allowed for the handling of a single complex-valued adaptive impulse response, instead of the four classical real-valued adaptive filters. With the simplified framework provided by the widely linear (WL) model, more advanced versions of recursive least-squares (RLS) were employed in order to take advantage of their superior tracking speeds when working with highly correlated input signals (such as speech). Despite the performances and numerical stability provided by using exponentially weighted versions of the RLS family in combination with line search methods (LSMs), the SAEC configurations have limited capabilities in mitigating the negative effects caused by high-level disturbances affecting the two microphone signals. Such is the case of double-talk scenarios, which considerably reduce the update accuracy of the adaptive system. This paper analyzes a regularization technique for the named WL-RLS-LSM adaptive filters by adjusting the correlation matrix associated with the input signals and creating a reaction in the update process. The proposed method is designed to considerably slow (or even freeze) the adaptation process while the disturbance is manifested. Simulation results are discussed in order to validate the theoretical content. Full article
(This article belongs to the Special Issue Advances in Algorithms and Architectures for Digital Signal Processing)
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31 pages, 12480 KiB  
Article
PCA-Based Preprocessing for Clustering-Based Fetal Heart Rate Extraction in Non-Invasive Fetal Electrocardiograms
by Luis Oyarzún, Encarnación Castillo, Luis Parrilla, Uwe Meyer-Baese and Antonio García
Electronics 2024, 13(7), 1264; https://doi.org/10.3390/electronics13071264 - 28 Mar 2024
Viewed by 952
Abstract
Non-invasive fetal electrocardiography (NI-ECG) is based on the acquisition of signals from electrodes on the mother’s abdominal surface. This abdominal ECG (aECG) signal consists of the maternal ECG (mECG) along with the fetal ECG (fECG) and other noises and artifacts. These records allow [...] Read more.
Non-invasive fetal electrocardiography (NI-ECG) is based on the acquisition of signals from electrodes on the mother’s abdominal surface. This abdominal ECG (aECG) signal consists of the maternal ECG (mECG) along with the fetal ECG (fECG) and other noises and artifacts. These records allow the acquisition of valuable and reliable information that helps ensure fetal well-being during pregnancy. This paper proposes a procedure based on principal component analysis (PCA) to obtain a single-channel master abdominal ECG record that can be used as input to fetal heart rate extraction techniques. The new procedure requires three main processing stages: PCA-based analysis for fECG-component extraction, polarity test, and curve fitting. To show the advantages of the proposal, this PCA-based method has been used as the feeding stage to a previously developed clustering-based method for single-channel aECG fetal heart rate monitoring. The results obtained for a set of real abdominal ECG recordings from annotated public aECG databases, the Abdominal and Direct Fetal ECG Database and the Challenge 2013 Training Set A, show improved efficiency in fetal heart rate extraction and illustrate the benefits derived from the use of such a master abdominal ECG channel. This allows us to achieve proper fetal heart rate monitoring without the need for manual inspection and selection of channels to be processed, while also allowing us to analyze records that would have been discarded otherwise. Full article
(This article belongs to the Special Issue Advances in Algorithms and Architectures for Digital Signal Processing)
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20 pages, 6579 KiB  
Article
Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers
by Luca Crocetti, Emanuele Pagani, Matteo Bertolucci and Luca Fanucci
Electronics 2024, 13(3), 668; https://doi.org/10.3390/electronics13030668 - 5 Feb 2024
Cited by 1 | Viewed by 1017
Abstract
The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid [...] Read more.
The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid synchronization algorithms, the communication standards commonly used in such applications define a physical layer frame structure that is composed of a preamble, segments of modulation symbols, and segments of pilot symbols. Therefore, the detection of a frame start becomes an essential operation, whose accuracy is undermined by the large Doppler shift and quantization errors in hardware implementations. In this work, we present a design methodology for frame synchronization modules that are robust against large frequency offsets and rely on a parallel architecture to support high throughput requirements. Several algorithms are evaluated in terms of the trade-off between accuracy and resource utilization, and the best solution is exemplified through its application to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. The implementation results are reported for a Xilinx KU115 FPGA, thereby showing the capability of supporting baud rates that are greater than 2 Gbaud, as well as a corresponding throughput of 15.80 Gbps. To the best of our knowledge, this paper is the first to propose a design methodology for parallel frame synchronization modules that has applicability to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. Full article
(This article belongs to the Special Issue Advances in Algorithms and Architectures for Digital Signal Processing)
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12 pages, 907 KiB  
Article
An Efficient Reduction of Timer Interrupts for Model Checking of Embedded Assembly Programs
by Satoshi Yamane, Taro Kriyama and Yajun Wu
Electronics 2024, 13(2), 463; https://doi.org/10.3390/electronics13020463 - 22 Jan 2024
Viewed by 876
Abstract
In verifying programs for embedded systems, it is essential to reduce the verification time because state explosion may occur during model checking. One solution is to reduce the number of interrupt handler executions. In particular, when periodic interrupts such as timer interrupts are [...] Read more.
In verifying programs for embedded systems, it is essential to reduce the verification time because state explosion may occur during model checking. One solution is to reduce the number of interrupt handler executions. In particular, when periodic interrupts such as timer interrupts are incorporated, it is necessary to know the physical time. In this paper, we define a control flow automaton (CFA) that can handle time and propose an algorithm based on interrupt handler execution reduction (IHER). The proposed method reduces the number of interrupt executions, including timer interrupts. A case study verified the effectiveness of this algorithm. Full article
(This article belongs to the Special Issue Advances in Algorithms and Architectures for Digital Signal Processing)
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