Recent Advances in Low Power Digital Hardware Design
A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".
Deadline for manuscript submissions: 15 December 2026 | Viewed by 57
Special Issue Editors
Interests: AI hardware accelerator; low-power digital hardware design; hardware-software co-design; edge AI computing
Interests: VLSI design; computer architecture; hardware-software co-optimization; AI systems and chip design
Special Issue Information
Dear Colleagues,
Low-power AI chips constitute a key technological foundation for ubiquitous intelligence, serving ultra-low-power edge/IoT endpoints, always-on wake-up and event-driven sensing, and compact platforms operating under stringent power and thermal constraints. With the continued evolution of foundation models, multimodal perception, and real-time on-device decision-making, AI chips are increasingly power-envelope-limited, constrained by average and peak power caps together with stringent standby-power and leakage requirements, rather than being driven solely by peak throughput. This Special Issue emphasizes power-first cross-layer innovations for AI chips, spanning model design, accelerator micro-architectures, memory and interconnect subsystems, and circuit techniques to systematically reduce dynamic power and leakage while satisfying tight PPA (power–performance–area) trade-offs, latency targets, and reliability requirements.
We invite original research and authoritative reviews on low-power AI chip design, including but not limited to: low-power AI accelerators for CNN/Transformer/GNN workloads; ultra-low-power always-on inference engines; AI-chip power management (clock/power gating, multi-voltage domains, DVFS, and power-state control); leakage-aware and near-/sub-threshold AI circuits; memory hierarchies and interconnect systems optimized for minimal data-movement power; compute-near-memory/in-memory AI acceleration; low-power arithmetic and model adaptation (quantization, mixed precision, sparsity, and accuracy-constrained approximate computing); and tape-out/prototype validation and reproducible benchmarking supported by measured power or rigorously justified power models.
Dr. Wendong Mao
Dr. Jinming Lu
Guest Editors
Manuscript Submission Information
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Keywords
- AI hardware accelerator
- low-power digital hardware design
- hardware-software co-design
- edge AI computing
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