Advances of Electronics Research from Zhejiang University

A special issue of Electronics (ISSN 2079-9292).

Deadline for manuscript submissions: closed (10 January 2024) | Viewed by 8778

Special Issue Editors


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Guest Editor
College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
Interests: sensors; 2D materials and devices; bio-electronic devices and medical devices
Special Issues, Collections and Topics in MDPI journals
ZJU-Hangzhou Global Scientific and Technological Innovation Center, Zhejiang University, Hangzhou 310027, China
Interests: sensors; acoustic device; phononic crystal; IC design

Special Issue Information

Dear Colleagues,

Zhejiang University, founded as Qiushi Academy in 1897, is one of the oldest universities in China. It is a member of the prestigious C9 League and is selected into the national higher education plans, including Double First Class University Plan, Project 985, and Project 211. Zhejiang University is a comprehensive research university. Its research spans 12 academic disciplines, including agriculture, art, economics, education, engineering, history, law, literature, management, medicine, natural sciences, and philosophy. The aim of this Special Issue is to provide an opportunity for researchers from Zhejiang University to publish their new ideas and latest research related to the science of electronics and its applications.

Topics for this Special Issue include, but are not limited to, the following:

  1. Sensors, integrated circuits for sensor interface and sensor application;
  2. Microelectronic devices, III-V compounds and carbon-based semiconductors;
  3. Radio frequency circuit design, filters, switches and module integration;
  4. Acoustic devices and resonators, phononic crystals and metamaterials;
  5. Analytical equipment and its miniaturization;
  6. Bioelectronics, wearable devices and implantable devices;
  7. Microfluidics and labs-on-chips;
  8. Optoelectronics, photonic circuits, photonic mm-wave/THz technology;
  9. Intelligent embedded systems, on-chip AI and mobile medical wisdom;
  10. Low-power VLSI chip design, neuromorphic and in-memory computing.

Dr. Xiaozhi Wang
Dr. Feng Gao
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • microelectronics
  • bioelectronics
  • sensors
  • integrated circuit
  • radio frequency
  • acoustic devices
  • analytical equipment
  • microfluidics
  • optoelectronics
  • photonics

Published Papers (5 papers)

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Research

11 pages, 5168 KiB  
Article
High Area Efficiency Bidirectional Silicon-Controlled Rectifier for Low-Voltage Electrostatic Discharge Protection
by Yipeng Chen, Dongyan Zhao, Shicong Zhou, Xinyu Zhu, Feng Gao, Yidong Yuan, Yi Hu, Tianting Zhao, Xiaojuan Li and Shurong Dong
Electronics 2023, 12(19), 4011; https://doi.org/10.3390/electronics12194011 - 23 Sep 2023
Viewed by 972
Abstract
Continuously scaling down and decreasing operation voltages of ICs, from the 5 V TTL-compatible voltage to 3.3 V, then 1.2 V, and now 0.8 V for low-power ICs, results in more stringent electrostatic discharge protection design requirements, such as a narrow ESD design [...] Read more.
Continuously scaling down and decreasing operation voltages of ICs, from the 5 V TTL-compatible voltage to 3.3 V, then 1.2 V, and now 0.8 V for low-power ICs, results in more stringent electrostatic discharge protection design requirements, such as a narrow ESD design window, low operation voltage, and high ESD robustness. Based on traditional diode string and diode-triggered silicon-controlled rectifiers, an enhanced diode-triggered silicon-controlled rectifier is proposed to meet the requirements of low-voltage integrated circuits as bidirectional electrostatic discharge protection. The new device employs an additional PMOS and NMOS in the N-well and P-well, respectively, to offer additional current paths along the surface to significantly enhance its robustness. TCAD simulation shows that the device is triggered by both the diode strings and embedded MOS, making the device turn on faster and the current distribution more uniform during the ON state owing to the additional surface current paths. The proposed new device has excellent dual-directional ESD protection performance with a figure of merit of 4.01 mA/um2, which is about a 71% improvement compared with the conventional diode-triggered silicon-controlled rectifier. It also has higher area efficiency, lower trigger voltage, lower current leakage, and a faster turn-on speed. The proposed enhanced diode-triggered silicon-controlled rectifier is an attractive ESD protection solution for ultra-low-voltage ICs. Full article
(This article belongs to the Special Issue Advances of Electronics Research from Zhejiang University)
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21 pages, 3125 KiB  
Article
Side-Channel Attack of Lightweight Cryptography Based on MixColumn: Case Study of PRINCE
by Jizheng Xue, Xiaowen Jiang, Peng Li, Wei Xi, Changbao Xu and Kai Huang
Electronics 2023, 12(3), 544; https://doi.org/10.3390/electronics12030544 - 20 Jan 2023
Viewed by 1772
Abstract
Lightweight cryptography is implemented in unrolled architecture generally, which has the characteristics of low latency and high real-time performance but also faces the threat of Side-Channel Attack (SCA). Different from traditional loop architecture, the unrolled architecture requires separate protection against SCA in each [...] Read more.
Lightweight cryptography is implemented in unrolled architecture generally, which has the characteristics of low latency and high real-time performance but also faces the threat of Side-Channel Attack (SCA). Different from traditional loop architecture, the unrolled architecture requires separate protection against SCA in each round. This leads to the unrolled architecture that is very sensitive to the number of rounds that need to be protected against SCA. In this paper, we propose an optimized method for the chosen-input attack that can effectively increase the number of rounds of differential propagation and recover the key from the fourth round of unrolled PRINCE for the first time. This research also evaluates the hardware overhead and performance of two types of Threshold implementation (TI) for PRINCE. The experimental results indicate that TI imposes substantial hardware overhead on the circuit, therefore a specified number of protection rounds is required. Full article
(This article belongs to the Special Issue Advances of Electronics Research from Zhejiang University)
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16 pages, 1653 KiB  
Article
A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions
by Peng Li, Hongyi Jin, Wei Xi, Changbao Xu, Hao Yao and Kai Huang
Electronics 2023, 12(1), 233; https://doi.org/10.3390/electronics12010233 - 3 Jan 2023
Cited by 2 | Viewed by 1609
Abstract
Transcendental functions are an important part of algorithms in many fields. However, the hardware accelerators available today for transcendental functions typically only support one such function. Hardware accelerators that can support miscellaneous transcendent functions are a waste of hardware resources. In order to [...] Read more.
Transcendental functions are an important part of algorithms in many fields. However, the hardware accelerators available today for transcendental functions typically only support one such function. Hardware accelerators that can support miscellaneous transcendent functions are a waste of hardware resources. In order to solve these problems, this paper proposes a reconfigurable hardware architecture for miscellaneous floating-point transcendental functions. The hardware architecture supports a variety of transcendental functions, including floating-point sine, cosine, arctangent, exponential and logarithmic functions. It adopts the method of a lookup table combined with a polynomial computation and reconfigurable technology to achieve the accuracy of two units of least precision (ulp) with 3.75 KB lookup tables and one core computing module. In addition, the hardware architecture uses retiming technology to realize the different operation times of each function. Experiments show that the hardware accelerators proposed can operate at a maximum frequency of 220 MHz. The full-load power consumption and areas are only 0.923 mW and 1.40×104μm2, which are reduced by 47.99% and 38.91%, respectively, compared with five separate superfunction hardware accelerators. Full article
(This article belongs to the Special Issue Advances of Electronics Research from Zhejiang University)
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22 pages, 4330 KiB  
Article
EiCSNet: Efficient Iterative Neural Network for Compressed Sensing Reconstruction
by Ziqun Zhou, Zeyu Wang, Fengyin Liu and Haibin Shen
Electronics 2023, 12(1), 30; https://doi.org/10.3390/electronics12010030 - 22 Dec 2022
Cited by 1 | Viewed by 1539
Abstract
The rapid growth of sensing data demands compressed sensing (CS) in order to achieve high-density storage and fast data transmission. Deep neural networks (DNNs) have been under intensive development for the reconstruction of high-quality images from compressed data. However, the complicated auxiliary structures [...] Read more.
The rapid growth of sensing data demands compressed sensing (CS) in order to achieve high-density storage and fast data transmission. Deep neural networks (DNNs) have been under intensive development for the reconstruction of high-quality images from compressed data. However, the complicated auxiliary structures of DNN models in pursuit of better recovery performance lead to low computational efficiency and long reconstruction times. Furthermore, it is difficult for conventional neural network designs to reconstruct extra-high-frequency information at a very low sampling rate. In this work, we propose an efficient iterative neural network for CS reconstruction (EiCSNet). An efficient gradient extraction module is designed to replace the complex auxiliary structures in order to train the DNNs more efficiently. An iterative enhancement network is applied to make full use of the limited information available in CS for better iterative recovery. In addition, a frequency-aware weighted loss is further proposed for better image restoration quality. Our proposed compact model, EiCSNet2*1, improved the performance slightly and was nearly seven times faster than its counterparts, which shows that it has a highly efficient network design. Additionally, our complete model, EiCSNet6*1, achieved the best effect at this stage, where the average PSNR was improved by 0.37 dB for all testing sets and sampling rates. Full article
(This article belongs to the Special Issue Advances of Electronics Research from Zhejiang University)
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16 pages, 464 KiB  
Article
A Hardware Trojan-Detection Technique Based on Suspicious Circuit Block Partition
by Jiajie Mao, Xiaowen Jiang, Dehong Liu, Jianjun Chen and Kai Huang
Electronics 2022, 11(24), 4138; https://doi.org/10.3390/electronics11244138 - 12 Dec 2022
Cited by 1 | Viewed by 1632
Abstract
To ensure that a hardware Trojan remains hidden in a circuit, it is usually necessary to ensure that the trigger signal has a low testability, which has been widely recognized and proven. The most advanced testability-based detection methods are rather slow for large [...] Read more.
To ensure that a hardware Trojan remains hidden in a circuit, it is usually necessary to ensure that the trigger signal has a low testability, which has been widely recognized and proven. The most advanced testability-based detection methods are rather slow for large circuits, and the false-positive rate is not as low as that for small circuits. In this paper, a hardware Trojan, through the low testability of the trigger signal and its position characteristics in the circuit, was detected, which greatly improves the detection speed while maintaining a lower false positive rate when being applied to large circuits. First, the Sandia Controllability/Observability Analysis Program (SCOAP) was applied to obtain the 0–1 controllability of the signals in the netlist. Secondly, the controllability value was calculated by the differential amplification model, in order to facilitate K-means clustering to get better results. Then, we calculate the shortest path between each suspicious signal to get the connection between each suspicious signal. Finally, we divide the suspicious signals into several suspicious circuit blocks to screen the real trigger signal. As a result, the false-negative rate of 0% and the highest false-positive rate of 5.02% were obtained on the Trust-Hub benchmarks. Full article
(This article belongs to the Special Issue Advances of Electronics Research from Zhejiang University)
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