Integration of Emerging Memory and Neuromorphic Architecture Chips

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: 20 March 2026 | Viewed by 830

Special Issue Editors


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Guest Editor
Research Center of Integrated Circuits, Huada Semiconductor Co., Ltd., Shanghai 200050, China
Interests: CMOS; emerging memory; neuromorphic chip
Special Issues, Collections and Topics in MDPI journals
College of Computer Science and Technology, Zhejiang University, Hangzhou 310027, China
Interests: neuromorphic chip

Special Issue Information

Dear Colleagues,

With the explosive growth of data in the era of artificial intelligence and cloud computing, traditional storage and computing architectures are increasingly strained in terms of efficiency, scalability, and energy consumption. In response to these challenges, emerging storage technologies—such as non-volatile memory, in-memory computing, and neuromorphic computing—are garnering significant attention due to their potential to revolutionize data processing paradigms. Notably, the convergence of storage and computing, known as “computing-in-memory”, has become a promising approach to overcome the limitations of the von Neumann bottleneck and to enable high-speed, energy-efficient data processing.

This Special Issue aims to provide a platform for researchers, engineers, and practitioners to share the latest advances and insights in novel storage technologies and their applications in computing–storage integration. By bringing together innovative works on materials, architectures, systems, and applications, we seek to promote cross-disciplinary collaboration and stimulate progress in this rapidly evolving field.

We welcome original research articles and comprehensive reviews on topics including, but not limited to, the following:

  • New non-volatile memory materials and device technologies;
  • Architectures and systems for in-memory and in-storage computing;
  • Storage-class memory applications in AI and edge computing;
  • Data-intensive computing with emerging storage technologies;
  • Neuromorphic and bio-inspired storage systems;
  • Reliability, endurance, and performance optimization of new memory devices;
  • Hardware–software co-design for computing–storage integration.

We look forward to receiving your valuable contributions.

Dr. Yi Zhao
Dr. De Ma
Guest Editors

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Keywords

  • emerging storage technologies
  • in-memory computing
  • non-volatile memory
  • storage–computing integration
  • neuromorphic storage systems

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Published Papers (1 paper)

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Research

13 pages, 3565 KB  
Article
Dynamic Imprint and Recovery Mechanisms in Hf0.2Zr0.8O2 Anti-Ferroelectric Capacitors with FORC Characterization
by Yuetong Huo, Jianguo Li, Zeping Weng, Yaru Ding, Lijian Chen, Jiabin Qi, Yiming Qu and Yi Zhao
Electronics 2025, 14(23), 4593; https://doi.org/10.3390/electronics14234593 - 23 Nov 2025
Viewed by 484
Abstract
The conventional static imprint effect in HfxZr1−xO2 (HZO) ferroelectric (FE) devices, which degrades data retention, is generally characterized by a shift in the hysteresis loop along the electric field axis. Unlike the static imprint effect, the dynamic imprint [...] Read more.
The conventional static imprint effect in HfxZr1−xO2 (HZO) ferroelectric (FE) devices, which degrades data retention, is generally characterized by a shift in the hysteresis loop along the electric field axis. Unlike the static imprint effect, the dynamic imprint effect emerges under dynamic electric fields or actual operating conditions, making the FE film exceptionally sensitive to switching pulse parameters and domain history. In HZO anti-ferroelectric (AFE) devices, this dynamic imprint effect alters the coercive field distribution associated with domain switching and poses a significant challenge to long-term stable device operation. This study systematically investigates the dynamic imprint effect and its recovery process using a comprehensive integration of first-order reversal curve (FORC) analysis, transient current-voltage (I-V), and polarization-voltage (P-V) characterization. By analyzing localized imprint behavior under sub-cycling conditions, mechanisms and recovery pathways of imprint in AFE devices are proposed. Finally, possible physics-based mechanisms describing imprint behaviors and recovery behaviors are discussed, providing insights for optimizing AFE memory technology performance and reliability. Full article
(This article belongs to the Special Issue Integration of Emerging Memory and Neuromorphic Architecture Chips)
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