Hardware-Aware Deep Learning

Dear Colleagues,

One of the main factors that contributes to the success of deep learning (DL) is the mighty computing power provided by modern hardware, spanning from high-performance server systems to resource-limited edge devices. The edge side (e.g., embedded systems, IoT) demands not only extreme energy-efficiency but also real-time inference capability, which requires cross-stack techniques, including model compression, compilation, architecture and circuit design of AI chips, emerging devices, etc. Beyond that, recent investigations, such federated learning, also bring model training to the edge side, with the data-security and computing limitations of mobile devices taken into consideration. On the cloud side, as the DL model size grows exponentially in the last two years (e.g., OpenAI GPT3, Google switch-transformer, etc.), how to efficiently support the training and inference of those immerse models is also an emerging research direction. Without lowering their hardware cost, however, incorporating them into the paradigm of machine learning as a service (MLaaS) will be infeasible. Moreover, the security and fault tolerant capability of DL also leads to a coherent of research, such as DL against error and non-ideal effects of the target hardware (e.g., bit-error of memory system). Therefore, the aforementioned concerns motivate the research of hardware-aware deep learning, for optimized energy, latency, and even security.

Dr. Deliang Fan
Dr. Zhezhi He
Dr. Alessandro Bruno
Guest Editors

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