# Design and Validation of a Reduced Switching Components Step-Up Multilevel Inverter (RSCS-MLI)

^{1}

^{2}

^{3}

^{4}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Proposed RSCS-MLI Circuit

#### 2.1. Description and Operation

_{1}, S

_{2}, S

_{3}, S

_{4}, P

_{1}, P

_{2}, P

_{3}, P4, S

_{X}, S

_{Y}and S

_{B}. The ratio of magnitudes of the dc sources used here is 2:1 i.e., the magnitudes of dc sources are V

_{DC}and V

_{DC}/2. The 11-levels can be generated by the circuit in which five are positive (+0.5 V

_{DC}, +V

_{DC}, +1.5 V

_{DC}, +2 V

_{DC}and +2.5 V

_{DC}), five are negative levels (−0.5 V

_{DC}, −V

_{DC}, −1.5 V

_{DC}, −2 V

_{DC}and −2.5 V

_{DC}) and a zero voltage level i.e., V

_{o}= 0. The stress on the switches S

_{x}, S

_{1}, S

_{2}, P

_{1}, P

_{2}and S

_{B}is equal to the input voltage whereas the switches S

_{3}, P

_{3}, P

_{4}and S

_{4}have blocking voltage of 0.5 V

_{DC}. The floating capacitor’s voltage is maintained at V

_{DC}.

**Zero level (0 V):**The zero states can be achieved either by turning on the switches S

_{1}, S

_{2}, S

_{3}, S

_{4}or P

_{1}, P

_{2}, P

_{3}, P

_{4}. The capacitor starts charging with the path VDC, D1, C1, SY during the zero level and settles at the voltage V

_{DC}. There is no necessity of an h-bridge to change the polarity as it is an inherent feature of the topology.

**First level (+V**The first level follows the path as P

_{DC}/2):_{1}, S

_{Y}, C

_{1}, S

_{2}, S

_{3}, −V

_{DC}/2, and P

_{4}. This result in formation of first level with voltage level 0.5 V

_{DC}. The capacitor’s voltage remains settled at V

_{DC.}

**Second level (+V**For the second level with voltage magnitude of V

_{DC}):_{DC}, the switches which remain in conduction are P

_{1}, S

_{Y}, C

_{1}, S

_{2}, S

_{3}, and S

_{4}. In this mode, no changes are observed in the capacitor voltage.

**Third level (+3 V**In this level, the output is produced by the additive nature of the V

_{DC}/2):_{DC}, capacitor C

_{1}, and the −V

_{DC}/2. The conduction path is P

_{1}, V

_{DC}, S

_{X}, C

_{1}, S

_{2}, S

_{3}, −V

_{DC}/2, and P

_{4}. The capacitor starts discharging in this mode. The output of this level is 1.5V

_{DC}.

**Fourth level (+2 V**This level is obtained by following the path as P

_{DC}):_{1}, V

_{DC}, S

_{X}, C

_{1}, S

_{2}, S

_{3}, and S

_{4}. The output of this level is 2 V

_{DC}which is achieved with the help of capacitor C

_{1}.

**Fifth level (+5 V**In this level the switch SB, conducts for the first time, helping in producing the fifth level whose output is 2.5 V

_{DC}/2):_{DC}. The conduction path is as P

_{1}, V

_{DC}, S

_{X}, C

_{1}, S

_{2}, S

_{B}, P

_{3}, +V

_{DC}/2, and S

_{4}. Similarly, the negative levels are achieved as according to those given in the Table 1. Figure 2 shows the conduction diagram for the various output voltage levels.

#### 2.2. Total Standing Voltage

_{S1}+ V

_{S2}+ V

_{S3}+ V

_{S4}+ V

_{P1}+ V

_{P2}+ V

_{P3}+ V

_{P4}+ V

_{SB}+ V

_{Sx}+ V

_{Sy}+ V

_{Sb}= (2 + 2 + 0.5+ 0.5 + 2 + 2 + 0.5 + 0.5 + 1 + 1 + 0.5 + 0.5) V

_{DC}= 12.5 V

_{DC}

## 3. Modulation Technique

## 4. Power Loss Analysis

#### 4.1. Conduction Losses

_{ON}is the current flowing through the switches during conduction, R

_{Internal}is the internal resistance of the switch.

#### 4.2. Switching Losses

_{OFF,n}and E

_{ON,n}—turn off and turn on energy loss for the n switch at time t

_{OFF}and t

_{ON}, respectively. Mathematically, the power loss occurs when the switch changes its state from OFF to ON is give as:

_{ON}, I

_{ON}, T

_{ON}and V

_{OFF}, I

_{OFF}, T

_{OFF}are the respective parameters for the ON and OFF state of the switch. f

_{OUTPUT}is output voltage frequency.

_{1}= 200 W (400 Ω), Z

_{2}= 500 W (150 Ω + 70 mH), and Z

_{3}= 1 kW (60 + 100 mH) are analyzed. The reason for low loss in switches is the low switching frequency. Conduction and switching losses are obtained for these loads for different switches and are placed in Figure 6a,b, respectively. The efficiency vs load plot is shown in Figure 6c. At load 200 W (400 Ω), maximum efficiency of 97.81% is obtained.

## 5. Comparison with Different Topologies

_{switch}), diodes (N

_{diodes}), dc sources (N

_{source}), capacitors (N

_{cap}), and levels (N

_{L}). The additional parameters taken are N

_{T}, which is the sum of N

_{switch}and N

_{diode,}and N

_{L}/N

_{T}i.e., the ratio of N

_{L}and N

_{T}. Table 2 is a comparative analysis of the other topologies with the proposed topologies. In comparison with other topologies, the presented topology requires less DC sources which ultimately will reduce the size of the proposed MLI and make it economic except for the topology present in the [10]. However, this topology requires a higher number of diodes and capacitors, which tends to elevate the cost of the whole system. For the topology present in the [18], the parameter N

_{source}is the same as our topology, but N

_{switch}and N

_{cap}is more. In [19,20] N

_{source}and N

_{diode}are both high. Additionally, in [20], N

_{switch}is also higher than our proposed topology. The ratio N

_{L}/N

_{T}for the proposed topology is better than [10,18,19,25], which shows that the topology presented in this work stands better than the mentioned topologies.

## 6. Results and Analysis

#### 6.1. Simulation Outcomes

#### 6.1.1. Constant R and RL Load

#### 6.1.2. Variable R and RL Load

#### 6.1.3. Variation in Modulation Index

#### 6.2. Hardware Implementation

## 7. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 13.**Hardware results of the proposed topology (

**a**) Output Voltage (

**b**) Voltage and current waveform for resistive load (

**c**) Variation of the Current waveform for change in the R-Load.

V_{o} | S_{X} | S_{1} | S_{2} | S_{3} | S_{4} | S_{B} | S_{Y} | P_{1} | P_{2} | P_{3} | P_{4} | |
---|---|---|---|---|---|---|---|---|---|---|---|---|

Positive Voltage Levels | 2.5 V_{DC} | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 |

2 V_{DC} | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | |

1.5 V_{DC} | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | |

V_{DC} | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | |

0.5 V_{DC} | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | |

Zero Voltage Level | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |

Negative Voltage Levels | −0.5 V_{DC} | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |

−V_{DC} | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | |

−1.5 V_{DC} | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | |

−2 V_{DC} | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |

−2.5 V_{DC} | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |

Topology | N_{switch} | N_{diode} | N_{T} | N_{L}/N_{T} | N_{source} | N_{cap} | N_{L} | TSV_{P.U.} |
---|---|---|---|---|---|---|---|---|

[8] | 8 | 0 | 8 | 1.4 | 3 | 0 | 11 | 9.6 |

[9] | 8 | 0 | 8 | 1.4 | 3 | 0 | 11 | 5.6 |

[10] | 10 | 9 | 19 | 0.6 | 1 | 9 | 11 | 8 |

[18] | 12 | 1 | 13 | 0.8 | 2 | 2 | 11 | 6.4 |

[19] | 11 | 5 | 16 | 0.7 | 5 | 0 | 11 | 5 |

[20] | 14 | 0 | 14 | 0.9 | 2 | 2 | 13 | 6.33 |

[25] | 10 | 4 | 14 | 0.6 | 1 | 4 | 9 | 7 |

Proposed | 11 | 1 | 12 | 0.9 | 2 | 1 | 11 | 5 |

Components | Specification |
---|---|

DC voltage source (2) | 20V, 40V |

Fundamental frequency | 50 Hz |

Capacitor | 3000 µF |

Load | R = 100 Ω, 200 Ω, L = 250 mH |

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**MDPI and ACS Style**

Wasiq, M.; Sarwar, A.; Sarwer, Z.; Tariq, M.; Ahmad, S.; Al-Shayea, A.M.; Hossain, J.
Design and Validation of a Reduced Switching Components Step-Up Multilevel Inverter (RSCS-MLI). *Processes* **2021**, *9*, 1948.
https://doi.org/10.3390/pr9111948

**AMA Style**

Wasiq M, Sarwar A, Sarwer Z, Tariq M, Ahmad S, Al-Shayea AM, Hossain J.
Design and Validation of a Reduced Switching Components Step-Up Multilevel Inverter (RSCS-MLI). *Processes*. 2021; 9(11):1948.
https://doi.org/10.3390/pr9111948

**Chicago/Turabian Style**

Wasiq, Mohammad, Adil Sarwar, Zeeshan Sarwer, Mohd Tariq, Shafiq Ahmad, Adel M. Al-Shayea, and Jahangir Hossain.
2021. "Design and Validation of a Reduced Switching Components Step-Up Multilevel Inverter (RSCS-MLI)" *Processes* 9, no. 11: 1948.
https://doi.org/10.3390/pr9111948