New Multi-Leg Converter for DC Microgrid with Two Duty Cycles

Abstract

In recent times, important contributions and the incorporation of renewable sources, such as photovoltaic, fuel cells, etc., are the main reasons for the popularity of DC microgrids. Integrating renewable sources into the microgrid requires high-voltage, high-efficiency DC-to-DC converters. Without modification, traditional converters are not suitable for achieving the required voltage in microgrid applications, due to the requirement for a large duty cycle, inductor resistance, voltage rating of switches, reverse recovery of the diode, high current rating inductors, etc. Various converters based on the circuitry of voltage multipliers, switched inductors/capacitors, coupled inductors, transformers, etc., have been proposed in the literature and have their drawbacks. In this paper, to realize significant voltage gain with two duty cycle controls, a new multi-leg (ML) converter is recommended as a solution for use in DC microgrids. The converter is designed by incorporating multiple legs into the boost converter. The implications of the proposed converter are reduced device voltage stress, small inductors and capacitors, two-duty cycle control, triple mode operation, single-stage conversion, etc. The proposed converter’s power circuits, mode of operation, and design equations of the converter are presented. The non-ideal model of the proposed converter is discussed, and efficiency is analyzed. The effect of unequal insurance on the operation of the converter is discussed. Comparative studies of converters are provided to draw attention to the benefits of the converter. The results of the experiments are shown to prove that the analysis and performance of the converter are correct. The discontinuous mode of operation and unequal inductance case of the converter are studied with the help of a simulation model.

1. Introduction

Many nations concentrate on renewable energy systems, which are more reliable, less costly, produce no poisonous by-products during operation, and are abundant in nature. In comparison to the voltage of the DC link, the output voltage of renewable sources, such as photovoltaic and fuel cell systems, is relatively low [1,2]. The sustainable development goals in the Envision 2030 agenda of the United Nations will pave the way for a promising future for renewable energy. The Saudi Vision 2030 is consistent with these objectives. The sustainable development goals (SDG) in the Envision 2030 agenda of the United Nations will pave the way for a promising future for renewable energy. The Saudi Vision 2030 is consistent with these objectives. SDG 7 of the United Nations is a sustainable, affordable energy system, which is supported by the suggested work goals. This effort promises to provide a good, energy-efficient system by employing a new DC–DC converter (SDG 12). The authors employed methods known as “double duty control” to achieve this (SDG 9). The structure of a usual microgrid operating at 400V DC is depicted in Figure 1. Research of a more advanced nature is being conducted in order to develop a more advanced interface system for the purpose of integrating renewable energy sources with the existing microgrid. This is in response to the growing demand for renewable energy sources within the existing microgrid [3,4]. The DC–DC converters are employed to integrate different power sources with the DC bus available in a microgrid [5,6]. The advancement of loads used in the current microgrid results in the requirement of a higher voltage source to drive them, whereas the voltage generated by renewable energy sources is insufficient to power those loads. In order to feed the DC and AC loads from the power generated by renewable energy sources, power electronics converters are employed [7,8]. The employment of DC–DC converters in emerging research fields, such as intelligent systems, electric-car fast-charging systems, and spacecraft applications have led researchers to concentrate more on DC–DC converter research areas. While developing improved DC–DC converters, different properties, such as high gain, high power delivery capability, compactness in size, converters with fewer component counts, less electromagnetic interference, fewer switches, etc., are mainly focused on [9,10]. Obtaining a higher gain voltage from the conventional DC–DC converters is possible, theoretically. However, practically operating a converter with a duty ratio of ≥0.9 is highly impossible, as it leads to high instability of the voltage at the output of the converter [11,12]. Moreover, parasitic elements in the converters restrict their usage to obtain a higher voltage gain. The invention of an isolated/non-isolated converter using a transformer or coupled inductor led researchers to obtain higher voltage gain [13,14]. Isolated power converters use a transformer to physically and electrically separate the input and output of the circuit so that no direct current can flow between them. When a transformer is turned on for the first time or after a short break, the core magnetization may not be in sync with the voltage. This can cause the transformer to draw inrush current from the system. Positive voltage creates positive flux, which adds to the residual flux already on the transformer core (remember, flux is the time integral of the voltage). The core is quickly saturated as a result of this. The effective magnetizing branch reduces the transformer’s air-core impedance. The air-core impedance is about the same size as the leakage impedance of the transformer. The effective impedance is controlled by flux; thus, when the transformer core saturates, the small impedance pulls a high-magnitude current from the system. The core saturates in one direction, so the transformer draws pulses of the inrush current with a strong DC component. In general, isolated converters follow DC–AC and AC–DC conversion steps. The two-step power-conversion process, core loss, and leakage magnetic power loss lead to an increase in total system loss. Moreover, the formation of a high inrush current at the primary side increases the size of the input filter. The isolated converter system was cumbersome and expensive due to the fact that it utilized a transformer [15,16]. The voltage gain in the coupled inductor-based topologies is based on the coupling factor, number of turns, and duty ratio. Therefore, we can achieve the desired voltage gain by selecting appropriate turns of the coupling inductor and controlling the duty ratio. In [17], a converter based on the coupling of two inductors is presented to achieve voltage gain $\frac{D(n+1)}{1-D}$, where D is the duty cycle and n is coupling ratio. However, this circuitry required an additional clamp circuit to absorb the leakage of energy. In [18], a zero-voltage-switching converter based on the coupling of two inductors and one normal inductor is presented with high efficiency and voltage gain $\frac{Dn+1}{1-D}$. Nevertheless, to get rid of the voltage spike, this circuitry needed an active clamp circuit. In [19], a coupled inductor-based converter with minimal reverse recovery of the output diode and the ability to achieve voltage gain $\frac{2+n}{1-D}$ is presented. However, to construct this converter, an auxiliary boosting circuit including snubber circuitry is required. Therefore, to suppress the switch voltage spike caused due to leakage inductance, an auxiliary voltage clamp and a snubber circuit are applied, which increases the cost and size. Several other converters based on coupled inductors and other boosting techniques are discussed with advantages and disadvantages in [20].

Figure 1. Typical microgrid structure with 400 V DC bus.

Adding converters in series is a straightforward method to boost the voltage with high voltage gain. A cascaded converter is created when two or more boost converters of the same or different types are linked together [20,21,22]. However, in this, the energy is transferred from one block to another block, which results in lower efficiency since the complete efficiency is the multiplication of the efficiency of each block. For example, the first-stage stored energy transfers to the second stage, the second stage to the third stage, and so on, and the final last stage energy delivers to the load. Moreover, the voltage gain is more nonlinear, and slight changes in the duty affect the output voltage more. Thus, a precise intricate control technique is required. The rating of the reactive components progressively increases from the first stage to the last stage. Moreover, the current and voltage ratings of the components and devices also need to be higher as the total number of stages increases. Revolution in converter research leads to the invention of the switched capacitor converters as a replacement for the cascaded converters, which can provide both step-up/down voltage conversion ratios [23,24]. In the conventional switched capacitor method, generally, the number of active switches (two or more for one capacitor) is greater to charge the capacitor and discharge the capacitor into the load. There are several topologies available in the literature, where a switched capacitor based on a diode can be connected between the primary side inductance and load [20]. However, these types of converters work on the principle of two-stage power transfer: first, the transfer of energy from the inductor to the intermediate switched capacitor, and second, the transfer of energy from the intermediate switched capacitor to the load side capacitor. In [23], the high voltage gain is achieved by using a voltage multiplier, which is formed by using several switched capacitor stages. In this converter, two diodes and two capacitors are required to add one additional stage on the output side. However, a single high current rating inductor is required on the input side. Moreover, the charging of one capacitor from another capacitor creates multiple loops, which decreases the efficiency of the converter. The impulse current ripple can be observed during the charging of the capacitor of the converter due to the voltage level difference between the input and capacitor voltage. Additionally, there is an initial transient spike in the input current due to the charging of capacitors directly from the input voltage. However, the impulse current is reduced suddenly due to equal potential at the capacitors and input voltage. To overcome the disadvantages of transfer energy loss of capacitors and loss of voltage regulation, a new soft-charging-based DC–DC switched-capacitor-type converter is suggested in [25]. Additionally, to avoid this issue, a filter can be used, or the charge and discharge of capacitors can be controlled with inductors, as explained in [25]. Since leakage current is also a concern with 3-level converters, a standard 3-level DC–DC buck–boost converter is proposed in [26] for solar applications. The suggested converter is comparable to the standard 3-level DC–DC converter in that it has a low leakage current and retains the benefit of high efficiency due to its lower voltage stress on switching components.

Recently, several converters have been proposed that combine the properties of a traditional converter or an interleaved structure with a voltage multiplier cell [27,28]. These schemes provide large conversion ratios and have reduced voltage stress. However, they are accompanied by the inherent disadvantages of a large number of switched capacitor circuits. To overcome these constraints, converters [29,30,31] are proposed that use a concept of the switched inductor to realize a high voltage. The voltage gain is not significantly improved by using several components and devices. In [32,33], high voltage gain is obtained through microgrid application-based converters by controlling two duty ratios. Furthermore, the use of a single duty cycle to operate the converter limits its range of voltage gain capability. Despite using three switches and two inductors, the converter voltage gain is moderate. In [34], the voltage gain is intensified by using multiple active–passive inductor cells. In the improved version, the inductor structure was replaced with multiple switched inductors, which resulted in higher voltage gain [35]. The use of several inductors resulted in the bulkiness of the converter and required several numbers of diodes. The overall system cost also increased. Theoretically, high voltage gain can be attained using an existing converter [34,35], which uses a single duty ratio. Additionally, using a classical boost converter, higher voltage gain can be attained at a duty ratio closer to unity (infinity at duty = 1). However, practically, these converters suffer to achieve high step-up voltage gain due to the low range of the duty cycle, the effect of the series resistance of high-rated capacitors and inductors, effective electromagnet interference (EMI), and high rating components and semiconductor devices. Moreover, the switches of these converters are continuously on for a longer time when operating at a higher duty ratio. Hence, there is a requirement for a large heat sink.

In this paper, a new converter called the “multi-leg (ML) converter” for the DC microgrid is presented. The converter is designed by incorporating multiple legs into the boost converter. The implications of the proposed converter are reduced device voltage stress of devices; small inductors and capacitors; two-duty-cycle control; triple mode operation; and single-stage conversion. The benefits of the proposed configurations are that the operating range is increased by operating the converter in three modes with a double duty ratio, and hence the converter can be operated at a higher duty ratio (the sum of two duty ratios). Moreover, the energy is transferred without multiple energy transfer loops, which increases efficiency and performance. The main contribution of the proposed circuit is that the proposed converter’s key features include high voltage gain; two-duty cycle control; low-rated semiconductor devices; flexibility in selecting a duty cycle to attain maximum voltage gain, etc. The high voltage gain can be attained by increasing the legs of the converter and by choosing appropriate duty cycles. The proposed converter is mainly based on the low energy in the magnetic field, which results in the reduced size of inductors. The current through each inductor is also lessened, with a reduction in the ripple inductor current. Another objective is to design a converter with low current stress on switches and decrease the current through the inductor. Furthermore, the structure is made without a coupled inductor, classical switched inductor, transformer, classical switched capacitor, or voltage multiplier. The suggested converter’s non-ideal model is explained, and its efficiency is examined. The effect of unequal inductance in the converter is explored. The converter’s discontinuous mode of operation and unequal inductance situation were also investigated and verified. The results of the experiments prove that the analysis and performance of the converter are correct.

The article is arranged as follows: Section 1 discusses why the proposed converter is important and its motivation. In Section 2, Section 3 and Section 4, the power circuitry, modes of operation, and voltage gain analysis are discussed. In Section 5, the non-ideal mode and efficiency analysis of the converter are discussed. Section 6 presents the analysis of the converter by considering unequal inductors. Section 7, Section 8 and Section 9 present the design, control scheme, and comparison with similar converters, respectively. The findings of a hardware prototype of the converter and simulation results are presented in Section 10. Finally, Section 11 summarizes the findings.

2. Multi-Leg (ML) Converter

Figure 2 depicts the proposed multi-leg (ML) converter’s circuit. The presented converter circuitry combines the multiple active–passive leg (APL) structures and voltage lift circuitry in the middle of the typical boost converter. In Figure 2, the power circuit has the parts of a traditional boost converter, such as the switch S, inductor L, diode D, and capacitor C. In the proposed converter, a n parallel multi-leg structure is designed using switches $S_1$ to $S_n$, inductors $L_1$ to $L_n$, capacitors capacitor $C_1$ to $C_n$, and diodes $D_1$ to $D_n$ that are connected to achieve high voltage gain. The diode $D^{{}^{\prime }}$ and capacitor $C^{{}^{\prime }}$ are used to lift the voltage to a higher level. The control switch $S_o$ is utilized to operate the converter in triple mode. Furthermore, the switches $S_o$ operate in a single direction by connecting series diodes $D_o$ in series to prevent the input source from short circuiting.

Figure 2. Power circuit of ML converter.

The lossless model of the proposed converter is assumed to explain modes of operation. The inductors $L_1$ to $L_n$ are considered to be of the same inductance level. Switches $S_1$ to $S_n$ are controlled by the pulse of duty cycle $k_1$, while switch $S_o$ is controlled by the pulse of duty cycle $k_2$. The gate pulse of switch $S_o$ is displaced by time $k_{1}T$, where the time period is T. The value of the duty ratio is chosen in such a way that its addition is always less than unity, i.e., $k_1+k_2<1$.

3. Continuous Conduction Mode

The suggested ML converter will function in three different ways. The voltage and current waveforms of reactive components and semiconductor devices are depicted in Figure 3.

Figure 3. Voltage and current typical waveforms in CCM.

3.1. MODE-I ($T_0$ to $T_1$)

Figure 4a illustrates the proposed ML converter circuitry for mode I. Switches S and $S_1$ to $S_n$ are switched on, while switch $S_o$ remains turned off. The input current is divided into parallel legs to charge inductors L and $L_1$ to $L_n$, and capacitors $C_1$ to $C_n$. At the same time, the input supply charges capacitor $C^{\prime }$ via diode $D^{\prime }$ and switch S. It is noteworthy that the diodes $D_o$ and D are reverse biased, and the diodes $D^{{}^{\prime }}$ and $D_1$ to $D_n$ are forward biased. Additionally, all the passive components, i.e., inductors L and $L_1$ to $L_n$, and $C^{\prime }$ and $C_1$ to $C_n$ are charged in parallel. The capacitor C supplies energy to the load R. The input voltage $v_{in}$ is applied across the inductors L, $L_1$, $L_2$, …, and $L_n$, as well as the capacitors $C^{{}^{\prime }}$, $C_1$, $C_2$, …, and $C_n$, during this mode. Therefore,

$$\left\{\begin{array}{cc}{V}_L=V_{in}\hfill & \\ V_{Lj}=V_{in}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ V_{C^{\prime }}=V_{in}\hfill & \\ V_{Ck}=V_{in}\hfill & \mathrm{where},k=1\mathrm{to}n\hfill \end{array}\right.$$

(1)

where $V_{in}$ is the average value of input voltage; $V_L$, $V_{L1}$, $V_{L2}$, …, and $V_{Ln}$ are the average voltages across inductors L, $L_1$, $L_2$, …, and $L_n$, respectively; $V_{C^{\prime }}$, $V_{C1}$, $V_{C2}$, …, and $V_{Cn}$ are capacitors $C^{\prime }$, $C_1$, $C_2$, …, and $C_n$ are average voltages, respectively. The current at the converter’s input and output terminals is given by

$$\left\{\begin{array}{cc}{i}_{in}=i_L+\sum _{j=1}^{j=n}{i}_{Lj}+i_{C^{\prime }}+\sum _{k=1}^{k=n}{i}_{Ck}\hfill & \\ i_{out}=-i_C\simeq \frac{V_{out}}{R}\hfill \end{array}\right.$$

(2)

where $i_{in}$ and $i_{out}$ are instantaneous input and output currents, respectively; $V_{out}$ is the average output voltage; $i_L$, $i_{L1}$, $i_{L2}$, …, and $i_{Ln}$ represent instantaneous currents flowing through inductors L, $L_1$, $L_2$, …, and $L_n$, respectively; and instantaneous currents through capacitors C, $C^{{}^{\prime }}$, $C_1$, $C_2$, …, and $C_n$ are denoted by $i_C$, $i_{C^{\prime }}$, $i_{C1}$, $i_{C2}$, …, and $i_{Cn}$, respectively. The current ripple via inductors L, $L_1$, $L_2$, …, and $L_n$, i.e., $\Delta i_L$, $\Delta i_{L1}$, $\Delta i_{L2}$, …, and $\Delta i_{Ln}$, and voltage ripple across capacitors $C^{{}^{\prime }}$, $C_1$, $C_2$, …, and $C_n$, i.e., $\Delta v_{C^{\prime }}$, $\Delta v_{C1}$, $\Delta v_{C2}$ …, and $\Delta v_{Cn}$, can be expressed as

$$\left\{\begin{array}{cc}\Delta i_L=\frac{V_{in}}{Lf}{k}_1\hfill & ,\Delta v_{C^{\prime }}=\frac{I_{C^{\prime }}}{C^{\prime }f}{k}_1\hfill \\ \Delta i_{Lj}=\frac{V_{in}}{L_{j}f}{k}_1\hfill & ,\Delta v_{Ck}=\frac{I_{Ck}}{C_{k}f}{k}_1\hfill \end{array}\right.\mathrm{where},j,k=1\mathrm{to}n$$

(3)

where f is the switching frequency of the converter.

Figure 4. Operating modes, (a) mode-I, (b) mode-II, and (c) mode-III.

The current through capacitors $C_1$ to $C_n$ and $C^{\prime }$ can be expressed as

$$\left\{\begin{array}{cc}{i}_{C^{\prime }}=i_S-i_L\hfill & \\ i_{Cj}=i_{Sj}-i_{Lj}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(4)

where $i_{C^{\prime }}$, $i_{C1}$, …, and $i_{Cn}$ are the current through capacitors $C^{\prime }$ and $C_1$ to $C_n$.

3.2. MODE-II ($T_1$ to $T_2$)

Figure 4b illustrates the proposed ML converter circuitry for mode-II. Switches S and $S_1-S_n$ are turned off in this mode, whereas switch $S_o$ is turned on. During this mode, stored energy in the capacitors $C_1$, $C_2$, …, and $C_{n-1}$, along with the input voltage, charges the inductors L, $L_1$, …, and $L_n$ in series. The diodes D, $D^{{}^{\prime }}$, and $D_1$ to $D_n$ are not conducting due to reverse biasing, whereas the diodes $D_o$ are forward biased in this mode. Inductors L, $L_1$ to $L_n$ are charged and capacitors $C_1$ to $C_{n-1}$ are discharged. It is noteworthy to mention that the energy of capacitors $C^{\prime }$ and $C_n$ remains as it is, and capacitor C supplies power to load R. The summation of the $V_{in}$ and capacitors $C_1$ to $C_{n-1}$ voltages is reflected across the series connection of inductors L, $L_1$, …, and $L_n$. Therefore,

$$V_{in}+\sum _{k=1}^{k=n-1}{V}_{Ck}=V_L+\sum _{j=1}^{j=n}{V}_{Lj}$$

(5)

By substituting capacitor voltages from (1) in (5),

$$\left\{\begin{array}{cc}{V}_L=n{\left(n+1\right)}^{-1}{V}_{in}\hfill & ,V_{C^{\prime }}=V_{in}\hfill \\ V_{Lj}=n{\left(n+1\right)}^{-1}{V}_{in}\hfill & ,V_{Ck}=V_{in}\hfill \end{array}\right.\mathrm{where},j,k=1\mathrm{to}n$$

(6)

The current at the converter’s input and output is given by

$$\left\{\begin{array}{cc}{i}_L=i_{Lj}=i_{in}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ i_{out}=-i_C\simeq \frac{V_{out}}{R}\hfill \end{array}\right.$$

(7)

The current ripple through inductors L, $L_1$ to $L_n$ and voltage ripple across capacitors $C_1$ to $C_{n-1}$ can be obtained as

$$\left\{\begin{array}{cc}\Delta i_L=\frac{n{\left(n+1\right)}^{-1}{V}_{in}}{Lf}{k}_2\hfill & \\ \Delta i_{Lj}=\frac{n{\left(n+1\right)}^{-1}{V}_{in}}{L_{j}f}{k}_2\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ \Delta v_{Ck}=\frac{I_{in}}{C_{k}f}{k}_2\hfill & \mathrm{where},k=1\mathrm{to}n-1\hfill \end{array}\right.$$

(8)

The current through capacitors $C_1$ to $C_n$ and $C^{\prime }$ are as follows:

$$\left\{\begin{array}{cc}{i}_{C^{\prime }}=0\hfill & \\ i_{Cj}=i_{Lj}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ i_{Cn}=0\hfill \end{array}\right.$$

(9)

3.3. MODE-III ($T_2$ to $T_3$)

Figure 4c illustrates the proposed ML converter circuitry for mode-III. In this mode, switches S, $S_o$, and $S_1-S_n$ are disabled. Inductors L, $L_1$, …, and $L_n$, as well as capacitors $C^{{}^{\prime }}$, $C_1$, $C_2$, …, and $C_n$, are serially discharged with input voltage $V_{in}$ to supply power to load R and capacitor $C_o$.

The diode D is forward biased, and reverse-biased diodes are $D^{{}^{\prime }}$, $D_o$, $D_1$, $D_2$, …, $D_n$. The voltage across load R is the sum of the voltages across the input $V_{in}$, capacitors $C^{{}^{\prime }}$, $C_1$ to $C_n$, and the inductors L, $L_1$, to $L_n$. Therefore,

$$V_{out}=V_{in}+\sum _{k=1}^{k=n}{V}_{Ck}+V_{C^{\prime }}-V_L-\sum _{j=1}^{j=n}{V}_{Lj}$$

(10)

By substituting capacitor voltages from (1) in (10),

$$\left\{\begin{array}{cc}{V}_L=\left(\frac{n+2}{n+1}\right)V_{in}-\left(\frac{1}{n+1}\right)V_{out}\hfill & ,V_{C^{\prime }}=V_{in}\hfill \\ V_{Lj}=\left(\frac{n+2}{n+1}\right)V_{in}-\left(\frac{1}{n+1}\right)V_{out}\hfill & ,V_{Ck}=V_{in}\hfill \end{array}\right.\mathrm{where},j,k=1\mathrm{to}n$$

(11)

The current at the converter’s input and output is given by

$$\left\{\begin{array}{cc}{i}_L=i_{Lj}=i_{in}=i_C+\frac{V_{out}}{R}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ i_{out}=i_{in}-i_C\hfill \end{array}\right.$$

(12)

The current ripple through inductors L, $L_1$ to $L_n$ and voltage ripple across capacitors $C_1$ to $C_{n-1}$ can be obtained as

$$\left\{\begin{array}{cc}\Delta i_L=\frac{\left(n+2\right)V_{in}-V_{out}}{\left(n+1\right)Lf}\left(1-k_1-k_2\right)\hfill & \\ \Delta i_{Lj}=\frac{\left(n+2\right)V_{in}-V_{out}}{\left(n+1\right)L_{j}f}\left(1-k_1-k_2\right)\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ \Delta v_{C^{\prime }}=\Delta v_{Ck}=\frac{I_{in}}{C_{k}f}\left(1-k_1-k_2\right)\hfill & \mathrm{where},k=1\mathrm{to}n\hfill \end{array}\right.$$

(13)

The current through capacitors $C_1$ to $C_n$ and $C^{\prime }$ is as follows:

$$\left\{\begin{array}{cc}{i}_{C^{\prime }}=i_L\hfill & \\ i_{Cj}=i_{Lj}\hfill & j=1\mathrm{to}n\hfill \end{array}\right.$$

(14)

The voltage gain of the ML converter is calculated using (1), (6) and (11):

$$G_{ML,ccm}=\frac{V_{out}}{V_{in}}=\frac{n+2-k_1-2k_2}{1-k_1-k_2}$$

(15)

4. Discontinuous Conduction Mode

The ML converter has four modes of operation. Figure 5 shows waveforms of reactive components and semiconductors.

Figure 5. Voltage and current typical waveforms in DCM.

4.1. MODE-I ($T_0$ to $T_1$)

This mode is similar to CCM mode-I. The currents via inductors L, $L_1$, $L_2$, …, and $L_n$ grow linearly, and their peak values are as follows:

$$\left\{\begin{array}{cc}{I}_{L-max1}=\frac{V_{in}{k}_{1}T}{L}\hfill & \hfill \\ I_{Lj-max1}=\frac{V_{in}{k}_{1}T}{L_j}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(16)

where $I_{L-max1}$, $I_{L1-max1}$, …, $I_{Ln-max1}$ are the peak values of the current via inductors L, $L_1$, …, $L_n$, respectively, in mode-I. Upon the completion of the period (at $t=k_{1}T$), all inductor currents attained the mode-I peak value. Therefore,

$$I_{L-max1}=I_{Lj-max1}=\frac{V_{in}{k}_{1}T}{L}=\frac{V_{in}{k}_{1}T}{L_j}\mathrm{where},j=1\mathrm{to}n$$

(17)

4.2. MODE-II ($T_1$ to $T_2$)

This mode is similar to CCM mode-II. The currents via inductors L, $L_1$, $L_2$, …, and $L_n$ grow linearly, and their peak values are as follows:

$$\left\{\begin{array}{cc}\begin{array}{cc}\hfill I_{L-max2}& =I_{L-max1}+\frac{n{V}_{in}{k}_{2}T}{\left(n+1\right)L}\hfill \\ & =\frac{V_{in}}{L}\left(k_{1}T+\frac{n{k}_{2}T}{n+1}\right)\hfill \end{array}\hfill & \\ \begin{array}{cc}\hfill I_{Lj-max2}& =I_{Lj-max1}+\frac{n{V}_{in}{k}_{2}T}{\left(n+1\right)L_j}\hfill \\ & =\frac{V_{in}}{L_j}\left(k_{1}T+\frac{n{k}_{2}T}{n+1}\right)\hfill \end{array}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(18)

where $I_{L-max2}$, $I_{L1-max2}$, …, $I_{Ln-max2}$ are the peak values of the current via inductor L, $L_1$, …, $L_n$, respectively, in mode-II. At the completion of the period (at $t=k_{1}T+k_{2}T$), all inductor currents attained the mode-II peak value. Therefore,

$$\begin{array}{cc}\hfill I_{L-max2}& =I_{Lj-max2}\hfill \\ & =\frac{V_{in}}{L}\left(k_{1}T+\frac{n{k}_{2}T}{n+1}\right)\hfill \\ & =\frac{V_{in}}{L_j}\left(k_{1}T+\frac{n{k}_{2}T}{n+1}\right)\mathrm{where},j=1\mathrm{to}n\hfill \end{array}$$

(19)

4.3. MODE-III ($T_2$ to $T_3$)

This mode is similar to CCM mode-III. The currents via inductors L, $L_1$, $L_2$, …, and $L_n$ decrease linearly from their peak value and reach zero at the completion of this mode. The peak value of currents via inductors L, $L_1$, $L_2$, …, and $L_n$ in mode-III are calculated as follows:

$$\left\{\begin{array}{cc}\begin{array}{cc}\hfill I_{L-max3}& =\frac{V_{out}-\left(n+2\right)V_{in}{k}_{3}T}{\left(n+1\right)L}\hfill \end{array}\hfill & \\ \begin{array}{cc}\hfill I_{Lj-max3}& =\frac{V_{out}-\left(n+2\right)V_{in}{k}_{3}T}{\left(n+1\right)L_j}\hfill \end{array}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(20)

where $I_{L-max3}$, $I_{L1-max3}$, …, $I_{Ln-max3}$ represent the maximum current values via inductors L, $L_1$, …, and $L_n$ in mode-III, respectively. At $t=k_{1}T+k_{2}T+k_{3}T$, all the inductor currents reached zero levels.

4.4. MODE-IV ($T_3$ to $T_4$)

The suggested ML converter circuitry for mode-IV, i.e., DCM, is shown in Figure 6. Switches S, $S_1-S_n$, and $S_o$ stay turned off, and the current in all inductors is zero. All the diodes are reverse biased, and the capacitor C supplies energy to the load R.

Figure 6. ML converter in DCM.

The peak currents across all of the inductors in mode-II and -III are the same. As a result, by combining (15) and (17),

$$\left\{\begin{array}{cc}\begin{array}{cc}\hfill \frac{V_{in}}{L}\left(k_{1}T+\frac{n{k}_{2}T}{n+1}\right)& =\frac{V_{out}-\left(n+2\right)V_{in}{k}_{3}T}{\left(n+1\right)L}\hfill \end{array}\hfill & \\ \begin{array}{cc}\hfill \frac{V_{in}}{L_j}\left(k_{1}T+\frac{n{k}_{2}T}{n+1}\right)& =\frac{V_{out}-\left(n+2\right)V_{in}{k}_{3}T}{\left(n+1\right)L_j}\hfill \end{array}\hfill & \mathrm{where}j=1\mathrm{to}n\hfill \end{array}\right.$$

(21)

By solving (21), the value of $k_3$ is obtained as

$$\begin{array}{cc}\hfill k_3& =\frac{V_{in}\left[\left(n+1\right)k_1+n{k}_2\right]}{V_{out}-\left(n+2\right)V_{in}}\hfill \end{array}$$

(22)

The average capacitor C current is zero and can also be expressed as

$$\begin{array}{cc}\hfill I_C& =\frac{1}{2}{k}_3{I}_{L-max3}-I_{out}\hfill \\ & =\frac{V_{in}^{2}T{\left[\left(n+1\right)k_1+n{k}_2\right]}^2}{2\left(n+1\right)\left[V_{out}-\left(n+2\right)V_{in}\right]L}-\frac{V_{out}}{R}=0\hfill \end{array}$$

(23)

Using (23), the ML converter’s DCM voltage gain is obtained as

$$G_{ML,dcm}=\frac{V_{out}}{V_{in}}=\frac{n+2}{2}+\sqrt{\frac{{\left(n+2\right)}^2}{4}+\frac{{\left[\left(n+1\right)k_1+n{k}_2\right]}^2}{2{\beta }_L\left(n+1\right)}}$$

(24)

where ${\beta }_L$ is normalized inductors time constant which is expressed as $\frac{Lf}{R}=\frac{L_{1}f}{R}=\dots =\frac{L_{n}f}{R}$.

The boundary normalized inductor time constant ${\beta }_{LB}$ is expressed as

$${\beta }_{LB}=\frac{\left[\left(n+1\right)k_1+n{k}_2\right]{\left(1-k_1-k_2\right)}^2}{2\left(n+1\right)\left[\left(n+2\right)-k_1-2k_2\right]}$$

(25)

Figure 7a,b shows the plot of ${\beta }_{LB}$ versus duty cycle $k_1$ and $k_2$ for $n=1$ and 2, respectively; where the CCM and DCM areas are noticeable. The ML converter operates in CCM when ${\beta }_L$ is larger than ${\beta }_{LB}$. Additionally, to operate the ML converter in CCM, the conditions are as follows:

$$\begin{array}{cc}\hfill {\beta }_{LB}& =\frac{\left[\left(n+1\right)k_1+n{k}_2\right]{\left(1-k_1-k_2\right)}^2}{2\left(n+1\right)\left[\left(n+2\right)-k_1-2k_2\right]}\hfill \\ & <\left({\beta }_L=\frac{Lf}{R}=\frac{L_{j}f}{R}\right)\mathrm{where},j=1\mathrm{to}n\hfill \end{array}$$

(26)

Figure 7. Boundary for CCM and DCM, (a) $n=1$, (b) $n=2$.

5. Non-Ideal Model and Efficiency Analysis of ML Converter

The consideration is given to the existence of non-idealities and an illustration of the non-idealistic circuit of the ML converter is given in Figure 8. It is possible to illustrate the non-ideal properties of inductors by taking into account the resistance $r_L$ that is connected in series with each inductor. The non-ideal characteristics of switches are illustrated by considering on-state resistance $r_S$ in series with each switch. Due to the fact that diodes are not ideal, $r_D$ denotes their resistance, and $V_{DT}$ denotes their threshold voltage. Consider $V_{rL}$, $V_{rS}$, and $V_{rD}$ as voltage drops across resistances $r_L$, $r_S$, and $r_D$, respectively.

Figure 8. ML converter with non-idealities.

5.1. MODE-I [$T_0-T_1$]

The inductors’ voltages can be found by

$$\left\{\begin{array}{c}{V}_L=V_{L1}=V_{in}-V_{drop1},V_{drop1}=V_{rS}+V_{rL}\hfill \\ V_{L2}=V_{in}-V_{drop2},V_{drop2}=V_{rL}+V_{rS}+V_{rD}+V_{DT}\hfill \\ ⋮\hfill \\ V_{Ln}=V_{in}-V_{dropn},V_{dropn}=V_{rL}+V_{rS}+\left(n-1\right)(V_{rD}+V_{DT})\hfill \\ I_L=I_{in}-I_{L1}-I_{L2}-\cdots -I_{Ln}\hfill \end{array}\right\}$$

(27)

The capacitors’ C average voltage and current can be found by

$$I_C=\frac{-V_{out}}{R},V_C=V_{out}$$

(28)

5.2. MODE-II [$T_1-T_2$]

The inductors’ voltages can be found by

$$V_L = V_{L1}=\dots =V_{Ln}=\frac{n{V}_{in}}{n+1}-V_{drop},V_{drop}=\frac{(n+1)V_{rL}+V_{rS}}{n+1}$$

(29)

The capacitors’ C average voltage and current can be found by

$$I_C=\frac{-V_{out}}{R},V_C=V_{out}$$

(30)

5.3. State-III [$t_2-t_3$]

The inductors’ voltages can be found by

$$V_L=V_{L1}=...=V_{Ln}=\frac{\left(n+2\right)V_{in}-V_{out}}{n+1}-V_{drop}^{\prime },V_{drop}^{\prime }=\frac{(n+1)V_{rL}+V_{rD}+V_{DT}}{n+1}$$

(31)

The capacitors’ C average voltage and current can be found by

$$I_C=\frac{-V_{out}}{R}+I_L,V_C=V_{out}$$

(32)

By applying the capacitor-charged balanced principle on capacitor $C_o$, the currents of inductors L, $L_1$, $L_2$, …, and $L_n$ are

$$I_L=\frac{V_{out}}{R}{\left(1-k_1-k_2\right)}^{-1}$$

(33)

The voltage gain with considering non-idealities is

$$\frac{V_{out}}{V_{in}}=\frac{X-k_1-2k_2-\frac{Y{V}_{rS}}{V_{in}}-\frac{(X-1)V_{rL}}{V_{in}}-\frac{Z(V_{rD}+V_{DT})}{V_{in}}}{1-k_1-k_2}$$

(34)

where $X=n+2$, $Y=k_1(n+2)+k_2$, and $Z=1+\frac{n(n-1)-2}{2}{k}_1-k_2$. The total switching loss in power $\left(P_{TSL}\right)$ due switches can be found by

$$P_{TSL}=P_{loss-S}+P_{loss-So}+\sum _{j=0}^n{P}_{loss-Sj}$$

(35)

The total loss $\left(P_{TSL}\right)$ with considering switching rising $R_t$ and falling $F_t$ switches time can be obtained as

$$P_{TSL}=\frac{1}{T}\left(I_S{V}_S\left(R_{t-S}+F_{t-S}\right)+I_{So}{V}_{So}\left(R_{t-So}+F_{t-So}\right)+\sum _{j=1}^n{I}_{Sj}{V}_{Sj}\left(R_{t-Sj}+F_{t-Sj}\right)\right)$$

(36)

The power at the input side of the converter can be found by

$$\begin{array}{cc}\hfill & P_{total-in}=V_{in}\left(I_L+I_{C^{\prime }}\right)k_1+V_{in}{k}_1\left(\sum _{j=1}^n{I}_{Lj}+\sum _{j=1}^n{I}_{Ci}\right)\hfill \\ & +\frac{I_L}{n+1}{V}_{in}{k}_2+V_{in}{k}_2\sum _{j=1}^n\frac{I_{Lj}}{n+1}+\left(1-k_1-k_2\right)V_{in}{I}_L+P_{TSL}\hfill \end{array}$$

(37)

The power at the output side of the converter can be found by $P_o^{total}=V_o^2/R$. Using, (34)–(37), the efficiency of ML converter $\eta$ can be found by

$$\eta ={\left(\frac{1+n{k}_1}{(n+2)-k_1-k_2-\left(\hslash \right)}+\frac{R{V}_{in}}{V_{out}^2}\left(I_{C^{\prime }}+\sum _{i=1}^n{I}_{Ci}\right)k_1+\frac{R}{V_{out}^2}{P}_{TSL}\right)}^{-1}$$

(38)

where

$$\begin{array}{cc}\hfill \hslash & =\frac{\left(X-1\right)V_{rL}}{V_{in}}+\frac{Y{V}_{rS}}{V_{in}}+\frac{Z(V_{rD}+V_{DT})}{V_{in}}\hfill \\ & =\frac{(n-1)V_{rL}}{V_{in}}+\frac{\left(k_1(n+2)+k_2\right)V_{rS}}{V_{in}}+\frac{\left(1+\frac{n(n-1)-2}{2}{k}_1-k_2\right)(V_{rD}+V_{DT})}{V_{in}}\hfill \end{array}$$

(39)

From (39), when the non-ideality factors $X,$ Y, and Z are reduced as well as when the ratio of switching loss to output power is lowered, the efficiency of the system improves. From (39) and (38), it is observed that higher efficiency can be obtained by selecting the appropriate duty cycle to achieve the desired voltage gain. The voltage drop is greater when the duty ratio $k_2$ of the converter is high. Moreover, the low value of the duty ratio $k_1$ and the higher value of the duty ratio $k_2$ result in low efficiency. Therefore, to achieve higher efficiency, it is suggested that the duty ratio $k_1$ should be high as compared to $k_2$.

6. ML Converter with the Discrepancy in Inductors

The current and voltage characteristics of the ML converter are different than the ideal case when inductances L, $L_1$ to $L_n$ are not equal due to tolerances in the magnetic component. Additional operating modes will occur between actual mode-I and mode-II due to different currents in the inductors at the end of mode-I. These additional modes occur to make an equal current in the inductors since in mode-II, all the inductors are in series. It is noteworthy to mention that, for switching inductor-based circuitry, the current through inductors will be different, and some component voltages may be different than the ideal if unequal inductors are used [31,32,35]. The ratings of the components are based on the unequal inductances cases. There are many possible combinations of unequal inductances that occur in ML converters. The cases where $L>L_1$ and $L=L_2=L_3...L_n$ are considered to explain the operation of the ML converter with the discrepancy in the inductor. A similar analysis can be made for other cases and the additional intermediate molds depend on the number of unequal inductances. The inductor currents for the considered case are shown in Figure 9.

Figure 9. Current waveforms through inductors when $L>L_1$ and $L=L_2=L_3...L_n$.

6.1. MODE-I [$T_0-T_1$]

The switches S and $S_1$ to $S_n$ are switched on, while switch $S_o$ remains switched off. This mode equivalent circuitry is similar to the circuitry of CCM mode-I. The inductors’ voltages can be found by

$$\left\{\begin{array}{cc}{V}_L=V_{in}\hfill & \\ V_{Lj}=V_{in}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(40)

The currents via inductors L, $L_1$, $L_2$, …, and $L_n$ grow linearly. However, since $L>L_1$ and $L=L_2=L_3...L_n$, the current through inductors L, $L_2$, …, and $L_n$ is low as compared to the current through inductor $L_1$.

The voltages across switches are

$$\left\{\begin{array}{cc}{V}_S=0,V_{Sj}=0\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ V_{So}=-V_{in}\hfill \end{array}\right.$$

(41)

The voltages across the diodes are

$$\left\{\begin{array}{cc}{V}_D=-(V_{out}-V_{in}),V_{Dj}=V_{D^{\prime }}=0\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(42)

6.2. MODE-II(A) [$T_1-T_2^{\prime }$]

The switches S, and $S_1$ to $S_n$ are switched off, while switch $S_o$ is switched on. This is the additional mode that occurs due to the considered discrepancies in the inductors. The equivalent circuit is shown in Figure 10. The inductors’ voltages can be found by

$$\left\{\begin{array}{cc}{V}_L=V_{in}\hfill & \\ V_{L1}=0\hfill & \\ V_{Lj}=V_{in}\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(43)

Figure 10. Equivalent circuit of ML converter in mode II(A) when $L>L_1$ and $L=L_2=L_3...L_n$.

The currents via inductors L, $L_2$, …, and $L_n$ are the same and still grow linearly, and the current through $L_1$ is freewheel and constant.

The voltages across switches are

$$\left\{\begin{array}{cc}{V}_S=0,V_{Sj}=V_{in}\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \\ V_{So}=0\hfill \end{array}\right.$$

(44)

The voltages across diodes are

$$\left\{\begin{array}{cc}{V}_D=-(V_{out}-2V_{in}),V_{D1}=-V_{in},V_{Dj}=V_{D^{\prime }}=0\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(45)

This mode will end when the currents through all the inductors become the same.

6.3. MODE-II(B) [$T_2^{\prime }-T_2$]

The switches S, and $S_1$ to $S_n$ are still switched off, while switches $S_o$ remain switched on. This mode is similar to CCM mode-II. The inductors’ voltages can be found by

$$\left\{\begin{array}{cc}{V}_L=\frac{L}{nL+L_1}\left(n{V}_{in}\right)\hfill & \\ V_{L1}=V_{in}=\frac{L_1}{nL+L_1}\left(n{V}_{in}\right)\hfill & \\ V_{Lj}=V_{in}=\frac{L_j}{n{L}_j+L_1}\left(n{V}_{in}\right)\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(46)

At the end of this mode, the current through all the inductance reaches maximum value.

The voltages across switches are

$$\left\{\begin{array}{c}{V}_S=-\frac{L}{nL+L_1}\left(n{V}_{in}\right)+V_{in},V_{S1}=-\frac{L_1}{nL+L_1}\left(n{V}_{in}\right)+V_{in}\hfill \\ V_{Sj}=V_{Sj-1}-\frac{L_j}{n{L}_j+L_1}\left(n{V}_{in}\right)+V_{in}\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(47)

The voltages across diodes are

$$\left\{\begin{array}{cc}{V}_D=-(V_{out}-2V_{in}),V_{D1}=-\left(1-\frac{n{L}_1}{nL+L_1}\right)V_{in}\hfill & \\ V_{D^{\prime }}=V_{Dj}=-\left(1-\frac{n{L}_j}{n{L}_j+L_1}\right)V_{in}\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(48)

6.4. MODE-III [$T_2-T_3$]

All the switches are switched off, and the equivalent circuitry is similar to CCM mode-III circuitry. The inductors’ voltages can be found by

$$\left\{\begin{array}{cc}{V}_L=\frac{L}{nL+L_1}\left((n+2)V_{in}-V_{out}\right)\hfill & \\ V_{L1}=V_{in}=\frac{L_1}{nL+L_1}\left((n+2)V_{in}-V_{out}\right)\hfill & \\ V_{Lj}=V_{in}=\frac{L_j}{n{L}_j+L_1}\left((n+2)V_{in}-V_{out}\right)\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(49)

At the end of this mode, the current through all the inductance reaches the minimum value.

The voltages across switches are

$$\left\{\begin{array}{cc}{V}_S=-\frac{L}{nL+L_1}\left((n+2)V_{in}-V_{out}\right)+V_{in}\hfill & \\ V_{S1}=-\frac{L_1}{nL+L_1}\left((n+2)V_{in}-V_{out}\right)+V_{in}\hfill & \\ V_{Sj}=V_{S(j-1)}-\frac{L_j}{n{L}_j+L_1}\left((n+2)V_{in}-V_{out}\right)+V_{in}\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(50)

The voltages across diodes are

$$\left\{\begin{array}{cc}{V}_D=0,V_{D1}=-\left(V_{in}-\frac{L_1}{nL+L_1}\left((n+2)V_{in}-V_{out}\right)\right)\hfill & \\ V_{D^{\prime }}=V_{Dj}=-\left(V_{in}-\frac{L_j}{n{L}_j+L_1}\left((n+2)V_{in}-V_{out}\right)\right)\hfill & \mathrm{where},j=2\mathrm{to}n\hfill \end{array}\right.$$

(51)

By using the inductor volt second balance principle, the voltage gain of the converter is calculated as

$$G_{ML,ccm}^{L1>L2,L1=L3...Ln}=\frac{V_{out}}{V_{in}}=\frac{n+2-k_1-2(k_1^{\prime }+k_2^{″})}{1-k_1-(k_2^{\prime }+k_2^{″})}$$

(52)

where $k_2^{\prime }$ and $k_2^{″}$ are the duty ratio for modes II(A) and II(B), respectively. We know $k_2^{\prime }+k_2^{″}=k_2$. Therefore, the voltage gain is rewritten as,

$$G_{ML,ccm}^{L>L1,L2=L3...=Ln}=\frac{V_{out}}{V_{in}}=\frac{n+2-k_1-2k_2}{1-k_1-k_2}$$

(53)

The difference between the two inductor currents is due to the small practical difference in the inductance. Split mode-II into two sub-modes (mode-II(A) and -II(B)), and the current profiles of the inductors are different. However, finally, the voltage gain will be the same as (15). This is well known and also proved for other switched inductor-based circuitry; this was discussed by various authors in [31,32,35]. For the case where $L>L_1$ and $L=L_2=L_3...L_n$, the voltage across diodes and switches is discussed above. However, for the other combination of discrepancy in inductors, the voltage across switches and diodes is different, and can be analyzed similarly as the above.

7. Design of ML Converter

For a specified voltage gain, the duty cycle can be determined as follows:

$$G_{ML,ccm}=\frac{V_{out}}{V_{in}}=\frac{n+2-k_1-2k_2}{1-k_1-k_2}=\frac{1}{1-F_{ML}\left(k_1,k_2\right)}$$

(54)

where $F_{ML}(k_1,k_2)$ is a function of duty cycles $k_1$ and $k_2$, and it is obtained as

$$F_{ML}\left(k_1,k_2\right)=\frac{n+1-k_2}{n+2-k_1-2k_2}$$

(55)

By using Equations (54) and (55), one can easily obtain the required duty cycle for the given voltage gain. For the purpose of design, the worst efficiency factor can be incorporated into the duty cycle calculation as the designed converter must also deliver the dissipated energy. Thus, while calculating the required duty cycle in Equation (56), we considered the worst-case scenarios of Equations (54) and (55) by adding the worst efficiency ${\eta }_w$ factor. This calculation method gives a more realistic duty cycle than just the equation without the efficiency factor. Therefore, the duty cycle parameters are designed with respect to the worst efficiency ${\eta }_w$ of the system as explained in [36]. The proposed system duty cycle while operating in ${\eta }_w$ is denoted by

$$F_{ML}\left(k_1,k_2\right)=1-\frac{{\eta }_w}{G_{ML,ccm}}$$

(56)

The critical inductances of legs, i.e., $L_c$, is calculated as

$$L_c=\frac{k_1+n{\left(n+1\right)}^{-1}{k}_2}{f\Delta i_L}{V}_{in}=\frac{k_1+n{\left(n+1\right)}^{-1}{k}_2}{f\times 40\%\mathrm{of}{I}_L}{V}_{in}$$

(57)

In this proposed system, the inductor current ripple, denoted by $\Delta i_L$, is estimated to be 40% of the $I_L$, where $I_L$ is the average current through inductor L. The critical current rating inductor, i.e., $I_{Lc}$, is calculated as

$$I_{Lc}>I_L+0.5\Delta i_L$$

(58)

The critical capacitances $C_{1,c}$, $C_{2,c}$, …, and $C_{n,c}$ are calculated as follows:

$$C_{k,c}=\frac{1-k_1-k_2}{f\times 1\%\mathrm{of}{V}_{in}}\mathrm{where},k=1\mathrm{to}n$$

(59)

The critical voltage ratings of $C_1$, $C_2$, …, and $C_n$ capacitors are found as follows:

$$V_{Ck,c}=V_{in}\mathrm{where},k=1\mathrm{to}n$$

(60)

The critical voltage rating of capacitor $C_o$, i.e., $V_{Co,c}$, is obtained as

$$V_{Co,c}=V_{out}\mathrm{or}\frac{I_{out}}{R}$$

(61)

The critical capacitance of the output capacitor $C_o$, i.e., $C_{o,c}$ is obtained as

$$C_{o,c}=\frac{k_1{V}_{out}+k_2{V}_{out}}{\Delta V_{Co}Rf}=\frac{\left(k_1+k_2\right)V_{out}}{Rf\times 1\%\mathrm{of}{V}_{out}}$$

(62)

The relation between the input voltage and capacitor voltages can be obtained by

$$v_{in}-v_{Cj}-i_{Cj}\left(R_{path}\right)=0\mathrm{where}j=1,2\dots n$$

(63)

where $R_{path}$ is the equivalent of all the resistance present in the charging loop or path, which includes the on-state resistance of switches, forward resistance of the diode, and ESR of the switch. The switching spike across the capacitor occurs due to the difference between $v_{in}$ and $v_{Cj}$, which can be minimized by selecting the appropriate device in the path, which has low internal resistance. For switches, the on-state resistance and the diode forward resistance should be minimal. This switching spike can also be reduced by selecting an appropriate capacitor with an accurate capacitance rating with low effective series resistance (ESR).

The critical voltages across the switches S, $S_o$, $S_1$, $S_2$, … and $S_n$, i.e., $V_S$, $V_{So,c}$, $V_{S1,c}$, $V_{S2,c}$, …, and $V_{Sn,c}$, are

$$\left\{\begin{array}{cc}{V}_{S,c}=\frac{V_{in}}{n+1}\left(\frac{n+1-k_2}{1-k_1-k_2}\right)\hfill & \\ V_{So,c}=V_{in}\left(\frac{n+k_1}{1-k_1-k_2}\right)\hfill & \\ V_{Sj,c}=\frac{j{V}_{in}}{n+1}\left(\frac{n+1-k_2}{1-k_1-k_2}\right)\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(64)

The critical voltages across the diodes D, $D_o$,$D_1$, $D_2$, …, and $D_n$, i.e., $V_{D,c}$, $V_{Do,c}$, $V_{D1,c}$, $V_{D2,c}$, …, and $V_{Dn,c}$ are

$$\left\{\begin{array}{cc}{V}_{D,c}=V_{in}\left(\frac{n+1-k_2}{1-k_1-k_2}\right)\hfill & \\ V_{Do,c}=\frac{V_{in}}{n+1}\left(\frac{n+1-k_2}{1-k_1-k_2}\right)\hfill & \\ V_{Dj,c}=\frac{V_{in}}{n+1}\left(\frac{n+1-k_2}{1-k_1-k_2}\right)\hfill & \mathrm{where},j=1\mathrm{to}n\hfill \end{array}\right.$$

(65)

It is important that to design the converter, the ratings of all the components and semiconductor devices should be greater than the calculated critical value. Additionally, the on-state resistance of the switches, and forward resistance and the threshold voltage of the diode should be as minimal as possible.

8. Possible Control Schemes for the ML Converter

The converter derives its output voltage from the two duty ratios $k_1$ and $k_2$. The plot of the voltage gain versus duty ratio $k_2$ for a different fixed values of duty ratio $k_1$, versus duty ratio $k_1$ for different fixed value of duty ratio $k_2$, and versus duty ratio $k_1$ and $k_2$, is shown in Figure 11. The voltage gain depends on both duty ratios $k_1$ and $k_2$, and the condition $k_1+k_2<1$ must be satisfactory to operate the converter. Therefore, both $k_1$ and $k_2$ are related to each other, and the desired voltage gain is possible to achieve in multiple ways by varying any one or both duty ratios.

Figure 11. Voltage gain (a) versus duty ratio $k_2$ for different fixed value of duty ratio $k_1$, (b) versus duty ratio $k_1$ for different fixed value of duty ratio $k_2$, and (c) versus duty ratio $k_1$ and $k_2$.

Due to the benefits of the two duty ratios, there are three ways to manage the control functioning of the converter:

• Scheme-1: Fixed duty ratio $k_1$ and a adjust duty ratio $k_2$,
• Scheme-2: Fixed duty ratio $k_2$ and a adjust duty ratio $k_1$,
• Scheme-3: Adjust both duty ratios $k_1$ and $k_2$.

8.1. Control Scheme-1

First, we fixed the duty ratio $k_1$ to achieve desired voltage gain based on the plot shown in Figure 11a. The value of duty ratio $k_1$ depends on the maximum and minimum values of the required voltage gain in the case of input voltage perturbation. For example, if the required minimum voltage gain (when input voltage is at maximum level) is 6.8, and the required maximum voltage gain (when the input voltage is at minimum level) is 26, then $k_1$ can be fixed at 0.4 and control $k_2$ from 0.1 to 0.5. Therefore, adjusting the duty ratio $k_2$ allows the output voltage $V_{out}$ to be controlled and maintained at a constant level whenever there is a change in the input voltage $V_{in}$. Figure 12 illustrates the pulses that are associated with this method in which the duty ratio $k_2$ is adjusted by a value of $\pm \Delta k_2$ in order to generate the suitable output voltage $V_{out}$. The difference in input voltage $\mp \Delta V_{in}$ determines the value of $\pm \Delta k_2$.

Figure 12. Control scheme-1, (X: gate pulse for switches S, $S_1-S_n$, Y: variation in the duty cycle of switch $S_o$ when voltage is increased at the input side, Z: variation in the duty cycle of switch $S_o$ when voltage is decreased at the input side).

8.2. Control Scheme-2

First, we fixed the duty ratio $k_2$ to achieve the desired voltage gain based on the plot shown in Figure 11b. The value of duty ratio $k_2$ depends on the maximum and minimum values of the required voltage gain in the case of input voltage perturbation. For example, if the required minimum voltage gain (when the input voltage is at a maximum level) is 5.5 and the required maximum voltage gain (when the input voltage is at minimum level) is 28, then $k_2$ can be fixed at 0.3 and control $k_1$ from 0.1 to 0.6. Therefore, adjusting the duty ratio $k_1$ allows the output voltage $V_{out}$ to be controlled and maintained at a constant level whenever there is a change in the input voltage $V_{in}$. Figure 13 illustrates the pulses that are associated with this method, in which the duty ratio $k_1$ is adjusted by a value of $\pm \Delta k_1$ in order to generate the suitable output voltage $V_{out}$. The difference in input voltage $\mp \Delta V_{in}$ determines the value of $\pm \Delta k_1$. Here, the duty ratio $k_2$ is shifted according to a change in the value of $k_1$.

Figure 13. Control scheme-2, (X: variation in the duty cycle of switches S, $S_1-S_n$, when voltage is increased at the input side, Y: variation in the duty cycle of switches S, $S_1-S_n$, when voltage is decreased at the input side, $Z_1$: the fixed duty cycle of switch $S_o$ is shifted when the voltage is increased at the input side, $Z_2$: the fixed duty cycle of switch $S_o$ is shifted when voltage is decreased at the input side).

8.3. Control Scheme-3

The desired voltage gain can be achieved by varying both duty ratios $k_1$ and $k_2$ based on the plot shown in Figure 11c and maintaining the condition $k_1+k_2<1$. Therefore, when the input voltage $V_{in}$ changes, the duty ratios $k_1$ and $k_2$ are used to control and keep the output voltage $V_{out}$ steady. Figure 14 shows the pulses that are used in this method. The duty ratios $k_1$ and $k_2$ are changed by $\pm \Delta k_1$ and $\pm \Delta k_2$ to obtain the suitable output voltage $V_{out}$. The values of $\pm \Delta k_1$ and $\pm \Delta k_2$ are determined by the change in $\mp \Delta V_{in}$. Both $k_1$ and $k_2$ duty ratio values changed and were dependent on one another during the disturbance.

Figure 14. Control scheme-3, (X: variation in the duty cycle of switches S, $S_1-S_n$ when voltage is increased at the input side, Y: variation in the duty cycle of switches S, $S_1-S_n$ when voltage is decreased at the input side, $Z_1$: the duty cycle of switch $S_o$ is shifted and varies when voltage is increased at the input side, $Z_2$: the fixed duty cycle of switch $S_o$ is shifted and varies when voltage is decreased at the input side).

9. Comparison of ML and Recent Converters

The findings of a comparison between the ML converter and other similar converters that were recently proposed are tabulated in Table 1. The novel converter developed in papers [31,32,33,34,35] is a variant on the simple boost converter. The converter is designed by adding one additional leg with voltage lift and active switched inductor techniques. The converter presented in [34,35] has the facility of choosing the number of legs, which is also one of the benefits of the proposed ML converter. One active switch is required to add one leg of the converter [34,35] and the proposed ML converter. However, the converter presented in the literature [35] requires five diodes and two inductors to design one leg of the converter, whereas the proposed ML converter requires only one inductor, one diode, and one capacitor to design one leg of the converter. Therefore, compared to [35], the proposed converter uses a smaller number of passive elements while designing the system. This results in the complexity of the converter being simplified, the overall cost of the system being reduced, and the converter being more compact. The ML converter shows an enormous increase in voltage gain when compared to [31,32,33,34]. The converter [33] and ML converter operates at two different duty cycles, allowing for greater variety in the duty cycle selection for the converter. This is the uniqueness of the ML converter. This characteristic of the ML converter permits two-duty cycle control, which is not achievable with ordinary single-switch converters. The switch-normalized voltage in the ML converter is lower than in the converters described in [33,34,35]. This enables the application of the ML converter using low-voltage rating devices. In the ML converter, an additional switch is employed to facilitate two different duty cycle operations of the converter. However, the switch voltage stress is less than the suggested converter’s output voltage. Additionally, the intermediate diodes utilized in this converter have a lower PIV rating than the converter’s output voltage. The PIV rating of the diodes decreases as the number of legs of the proposed converter increases. Therefore, diodes with lower PIV ratings than the output voltage are used to design the proposed converter system.

Table 1. Comparison of converters.

Para.	CB	[31]			[33]	[34]	[35]	ML Converter
		I	II	III
$N_S$	1	2	2	3	3	n + 1	n + 2	n + 2
$N_L$	1	2	2	2	2	n + 2	$2n$ + 4	n + 1
$N_C$	1	1	2	3	1	1	1	n + 1
$N_D$	1	1	2	3	2	$2n$ + 1	$5n$ + 6	n + 2
$G_{ML,ccm}$	$\frac{1}{1-k}$	$\frac{1+k}{1-k}$	$\frac{2}{1-k}$	$\frac{3-k}{1-k}$	$\frac{1-k_1}{1-k_1-k_2}$	$\frac{1+(n+1)k}{1-k}$	$\frac{1+(2n+3)k}{1-k}$	$\frac{n+2-k_1-2k_2}{1-k_1-k_2}$
$N_V^S$	1	$\frac{G_{ML,ccm}+1}{2G_{ML,ccm}}$	$\frac{1}{2}$	$\frac{G_{ML,ccm}-1}{2G_{ML,ccm}}$	$\begin{array}{c}{S}_1\twoheadrightarrow \frac{G_{ML,ccm}+1}{2G_{ML,ccm}}\\ S_2\twoheadrightarrow 1\end{array}$	$\begin{array}{c}S\twoheadrightarrow \frac{G_{ML,ccm}+n+1}{(n+2)G_{ML,ccm}}\\ S^{\prime }\twoheadrightarrow \frac{(1+n)G_{ML,ccm}+1}{(n+2)G_{ML,ccm}}\\ S_j\twoheadrightarrow \frac{j{G}_{ML,ccm}+\left(n-j+2\right)}{(n+2)G_{ML,ccm}}\end{array}$	$\begin{array}{c}{S}^{\prime }\twoheadrightarrow \frac{(1+n)G_{ML,ccm}+1}{(n+2)G_{ML,ccm}}\\ S\twoheadrightarrow \frac{G_{ML,ccm}+n+1}{(n+2)G_{ML,ccm}}\\ S_j\twoheadrightarrow \frac{j{G}_{ML,ccm}+\left(n-j+2\right)}{(n+2)G_{ML,ccm}}\end{array}$	$\begin{array}{c}S\twoheadrightarrow \frac{G_{ML,ccm}-1}{(n+1)G_{ML,ccm}}\\ S_o\twoheadrightarrow \frac{G_{ML,ccm}-2}{G_{ML,ccm}}\\ S_j\twoheadrightarrow \frac{j\left(G_{ML,ccm}-1\right)}{(n+1)G_{ML,ccm}}\end{array}$
$N_{PIV}^{ID}$	-	-	$\frac{-1}{2}$	$\frac{1-G_{ML,ccm}}{2G_{ML,ccm}}$	$\frac{-1}{G_{ML,ccm}}$	$\begin{array}{c}{D}_{1,j}\twoheadrightarrow \frac{-1}{G_{ML,ccm}}\\ D_{2,j}\twoheadrightarrow \frac{1-G_{ML,ccm}}{\left(n+2\right)G_{ML,ccm}}\end{array}$	$\begin{array}{c}{D}_1,D_4\twoheadrightarrow \frac{-1}{G_{ML,ccm}}\\ D_2\twoheadrightarrow \frac{1-G_{ML,ccm}}{\left(n+2\right)G_{ML,ccm}}\\ D_3,D_5\twoheadrightarrow \frac{1-G_{ML,ccm}}{\left(2n+4\right)G_{ML,ccm}}\end{array}$	$\begin{array}{c}{D}^{\prime }\twoheadrightarrow \frac{1-G_{ML,ccm}}{(n+1)G_{ML,ccm}}\\ D_1,\cdots ,D_n\twoheadrightarrow \frac{1-G_{ML,ccm}}{\left(n+1\right)G_{ML,ccm}}\end{array}$
$N_{PIV}^{LD}$	$-1$	$-\frac{G_{ML,ccm}+1}{G_{ML,ccm}}$	$-1$	$-\frac{G_{ML,ccm}-1}{G_{ML,ccm}}$	$-\frac{G_{ML,ccm}+1}{G_{ML,ccm}}$	$-\frac{G_{ML,ccm}+1}{G_{ML,ccm}}$	$-\frac{G_{ML,ccm}+1}{G_{ML,ccm}}$	$-\frac{G_{ML,ccm}-1}{G_{ML,ccm}}$
TDC:	No	No	No	No	Yes	No	No	Yes

$N_S$: switches, $N_L$: inductors, $N_C$: capacitor, $N_D$: diode, $N_v^S$: normalized voltage stress on the switch, $N_{PIV}^{ID}$: normalized PIV on intermediate diode, $N_{PIV}^{LD}$: normalized PIV on load side diode, TDC: two-duty ratio control.

10. Validation of the ML Converter

10.1. Equal Case of Inductances: Experimental Findings

The suggested converter behavior is examined experimentally, and the parameters are tabulated in Table 2. The prototype of the multi-leg (ML) converter with n = 2 is shown in Figure 15. The power density of the designed prototype is calculated as

$$P_{density}=\frac{P_{out}}{Volume}=\frac{500\mathrm{W}}{7\mathrm{cm}\times 15.2\mathrm{cm}\times 15.1\mathrm{cm}}=0.32{\mathrm{W}/\mathrm{cm}}^3$$

(66)

where $P_{density}$ is the power density, $P_{out}$ is the output power, and $Volume$ is the product of the length, width, and height of the designed prototype.

Table 2. Parameters of designed ML converter.

Parameters	Value /Model
$v_{in}$	32–40 V
$v_{out}$	400 V
n	2
f	50 kHz
L, $L_1$, $L_2$	400 $\mathsf{\mu }$H/10 A
$C_1$, $C_2$, $C^{{}^{\prime }}$	100 $\mathsf{\mu }$F/50 V
C	220 $\mathsf{\mu }$F/450 V
S, $S_1$, $S_2$	STW46NF30
$S_o$	IRFP360PBF
$D^{\prime }$, $D_1$, $D_2$	STTH3002W
D	STTH6004W

Figure 15. Prototype of multi-leg (ML) converter with n = 2.

The voltage waveforms at the input and output are shown in Figure 16a. The output voltage of 399.8 V is achieved by supplying 36.3 V at the input voltage. It is tested that the suggested ML converter steps up the input voltage by a factor of 10. The experimental waveforms of the output voltage and output current are depicted in Figure 16b. It is perceived that the high gain converter delivers a voltage and current of 399.7 V and 1.25 A, respectively, at the output of the converter, which confirms the output power of 499.62 W. Figure 16c shows the input current and inductor L current waveforms. The average input current is 14.63 A, and the average current through inductor L is 4.77 A.

Figure 16. Results, (a) $v_{out}$ and $v_{in}$, (b) $v_{out}$ and $i_{out}$, (c) $i_{in}$ and $i_L$, (d) $v_S$, $v_{S1}$, $v_{S2}$, and $v_{So}$, (e) $v_{C1}$ and $v_{C2}$, (f) $v_{C^{\prime }}$ and $v_{Co}$, (g) $i_{L1}$, $i_{L2}$, $v_{C1}$ and $v_{C2}$.

The voltages across switches S, $S_1$, $S_2$, and $S_o$ are shown in Figure 16d. In mode-I, switches S, $S_1$, and $S_2$ are all turned on, and the voltage across switch $S_o$ is −35.7 V. The switch $S_o$ is turned on in mode-II. It is observed that the switches S, $S_1$, and $S_2$ are turned off, and the voltages across S, $S_1$, and $S_2$ are 12.6 V, 12.5 V, and 25.5 V, respectively. All the switches are turned off in mode-III. It is observed that the voltages across S, $S_1$, and $S_2$ and $S_o$ are 122.3 V, 122.1 V, 243.4 V, and 328.3 V, respectively. The voltages across capacitors $C_1$ and $C_2$ are shown in Figure 16e. The average voltages across the capacitor are 36.1 V and 35.8 V, respectively. The voltages of capacitors $C^{{}^{\prime }}$ and $C_o$ are shown in Figure 16f. The average voltage of capacitor $C^{{}^{\prime }}$ is 35.9 V and that of capacitor $C_o$ is 399.8 V. Figure 16g depicts the inductor $L_1$ and $L_2$ current and the capacitor $C_1$ and $C_2$ voltage waveform. The average currents through inductors $L_1$ and $L_2$ are 4.54 A and 4.63 A, respectively.

The proposed converter’s efficiency is measured at different output powers. Figure 17a shows a graph of efficiency versus load power. At a load power of 500 W, it can be seen that the prototype’s experimental efficiency is 93.61%. To analyze the discrepancies between theoretical and experimental efficiency, the plot of efficiency versus power is also drawn theoretically, as shown in Figure 17a. It is found that the theoretical efficiency of the converter is 94.2% at 500 W. Therefore, the differences between theoretical calculated efficiency and experimental efficiency are 0.47%. It is also found that the differences between theoretical calculated efficiency and experimental efficiency are almost consistent when the power is increased from 100 W to 500 W.

Figure 17. Plots: (a) efficiency curve for different powers, (b) loss distribution when output power 500 W.

Figure 17b shows the loss distribution of the converter at a power of 500 W. It is found that switches cause 45.7% of the total losses in theory and 47.3% of the total losses in practice. It is also found that 37.4% of the total losses occur in the didoes in theory and 33.2% of the total losses occur in practice. It is observed that the switches experience maximum losses in the converter as compared to other devices. It is investigated that theoretically and experimentally, 16.9% and 17.4% losses occur, respectively, due to reactive components.

10.2. Discontinuous Conduction Mode Validation-Simulation Results

To investigate the performance of the ML converter in DCM, a simulation model is developed by considering three legs in the converter. To operate the converter in the DCM mode, the switching frequency is reduced to 25 kHz, all the inductor values are reduced to 325 $\mathsf{\mu }$H, and the converter is operated at low power by considering the load (R) value 1000 $\Omega$, and all of the capacitors’ value is 100 $\mathsf{\mu }$F. For the given specification, the normalized inductors’ time constant value for each inductor is calculated as ${\beta }_L=\frac{Lf}{R}=\frac{L_{1}f}{R}=\frac{L2f}{R}=\frac{L3f}{R}=\frac{325\mathsf{\mu }\mathrm{H}\times 25\mathrm{kHz}}{1000}=2.6\times {10}^{-3}$. The expected voltage gain of the ML converter at duty ratios $k_1=0.35$ and $k_2=0.25$ is calculated by using (24) which is equal to 11.29. Figure 18a shows the obtained waveform of $v_{out}$, $v_{in}$, $i_L$, and $i_{out}$, where the input voltage is 40 V. It can be observed that the inductor L current is increased in mode-I and -II, decreased to zero in mode-III, and remains zero till the start of the next mode-I. The current ripple through inductor L is 8 A and the average current is 4.13 A. The average value obtained output voltage is 449.7 V and the output current is 1.12 A. The output voltage and current ripples are 3.1 V and 0.6 mA, respectively. Figure 18b shows the obtained waveform of $v_{out}$, $v_{S1}$, $i_{L1}$, and $v_{L1}$, where the input voltage is kept constant at 40 V. It can be observed that the inductor $L_1$ current is increased in mode-I and -II, decreased to zero in mode-III, and remains zero till the start of the next mode-I. The current ripple through inductor L is 8 A, and the average current is 4.12 A, which is the same as the current through inductor L. The voltages across the switch $S_1$ in mode-II and -III are 10.2 V and 102.3 V, respectively. The voltages across the inductor $L_1$ in mode-I, -II, and -III are 40 V, 29.8 V, and −62.5 V, respectively. In DCM mode, the voltage across inductor $L_1$ drops to zero. All of the investigated values confirm the presented DCM theoretical analysis.

Figure 18. Simulation results in DCM mode, (a) $v_{out}$, $v_{in}$, $i_L$, and $i_{out}$ (b) $v_{out}$, $v_{S1}$, $i_{L1}$, and $v_{L1}$.

10.3. Unequal Case of Inductances-Simulation Results

To investigate the performance of the ML converter with unequal inductances, a simulation model by considering $L_1=500$ $\mathsf{\mu }\mathrm{H}$ and $L=L_2=L_3=700$$\mathsf{\mu }\mathrm{H}$ (70% discrepancy in inductance $L_1$) is developed, and the load (R) value of 320 $\Omega$ is connected at the output. The performance is investigated at duty ratio $k_1=0.35$ and $k_2=0.25$, with the switching frequency of 50 kHz. All the capacitors’ values are 100 $\mathsf{\mu }$F. Figure 19a shows the obtained waveform of $v_{in}$, $i_{in}$, $v_{out}$, and $i_{out}$, where the input voltage is 40 V. The average values of the output voltage and current are 400.2 V and 1.26 A. The average input current is 12.7 A. Figure 19b shows the obtained waveforms of $i_L$, $i_{L1}$, $i_{L2}$, and $i_{L3}$. It can be observed that the currents through inductors L, $L_2$, and $L_3$ are the same in each mode since $L=L_2=L_3$. However, the current through inductor $L_1$ in mode-I is slightly greater than the current through inductor L due to $L>L_1$. Mode-II is divided into sub-mode-II(A) and -II(B). In mode-II(A), the current of inductor $L_1$ holds a constant value, and this mode ends when the current through all of the inductors becomes equal. In mode- II(B) and -III, the currents through all the inductors are equal. It is observed that the peak-to-peak value of all the inductor currents is the same and equal to 0.6 A. However, the average current through inductor $L_1$ is higher than the average current through inductors L, $L_2$, and $L_3$ since $L>L_1$. Figure 19c shows the obtained waveform of $v_L$, $v_S$, $v_{L1}$, and $v_{S1}$. In mode-I, the average voltage across inductors L and $L_1$ is the same and equal to 40 V. In mode-II(A), the voltages across inductors L and $L_1$ are different and equal to 40 V and 0 V, respectively, which is expected due to $L\ne L_1$. This unequal voltage across inductors results in unequal voltages across switches. The average voltage across switches S and $S_1$ are 0 V and 40 V. In mode-II(B), the average voltages across inductors L and $L_1$ are 33.2 V and 23.07 V, respectively, which is expected due to $L\ne L_1$. The average voltages across switches S and $S_1$ are 6.9 V and 18.1 V in mode-II(B), respectively. In mode-III, the average voltages across inductors L and $L_1$ are −54.1 V and −38.8 V, respectively, which is expected due to $L\ne L_1$. The average voltages across switches S and $S_1$ are 94.2 V and 78.8 V, respectively. All of the investigated values confirm the presented theoretical analysis for the unequal case of inductance.

Figure 19. Simulation results when $L>L_1$ and $L=L_2=L_3...L_n$, (a) $v_{in}$, $i_{in}$, $v_{out}$, and $i_{out}$, (b) $i_L$, $i_{L1}$, $i_{L2}$, and $i_{L3}$, (c) $v_L$, $v_S$, $v_{L1}$, and $v_{S1}$.

11. Conclusions

A novel DC–DC converter called the “multi-leg” (ML) converter is proposed to obtain a high voltage. The ML converter is designed by inserting multiple legs into a standard boost converter. Each leg is made up of a switch, an inductor, a diode, and a capacitor. The switches are turned on and off in such a way that the ML converter functions in three modes, and the output voltage is controlled through two duty cycles. As a result, the recommended converter allows for greater flexibility in selecting the duty cycle for switches. Other advantages of the ML converter include the following: (1) the size of inductors is less since following the principle of the switched inductor, (2) low current rating inductors, (3) less diodes than contemporary converters, (4) providing flexibility in the selection of legs, (5) low voltage rating devices, (6) low voltage rating capacitors in intermediate stages, (7) modular structure, etc. The converter operable in CCM and DCM operational analysis, design, and comparison is detailed and presented in this paper. The non-ideal model and various possible control schemes based on the selection of duty ratios to achieve constant voltage at the output are presented. Using an experimentally developed prototype, the performance of the ML converter for the equal inductances case is validated. Theoretically and experimentally, 16.9% and 17.4% losses, respectively, occur due to reactive components. At a load power of 500 W, the measured efficiency of the developed prototype is 93.53%. The DCM operation and unequal case of inductance are validated through a simulation model. Due to high voltage gain, unidirectional power flow, wide duty range operation, and flexibility in control and selection of duty ratio, the proposed converter is more suitable for 400 V DC microgrid PV applications. One of the SDG 7 objectives of the UN is a reliable, affordable energy system, which is supported by the suggested work targets. This effort promises to achieve SDG 12 by providing a high voltage gain converter system by employing a double-duty technique.