Loss-Driven Design Methodology for MHz-Class GaN QSW Buck Converters with a PCB Air-Core Inductor in SWaP-Constrained Aerospace Applications

Abstract

Aerospace power systems, including satellites in low earth orbit (LEO) and geostationary earth orbit (GEO), face stringent thermal constraints to minimize size, weight, and power (SWaP). Gallium nitride (GaN) devices offer superior radiation hardness—critical for the harsh space environment—and MHz-level switching capabilities. This high-frequency operation minimizes passive components, particularly magnetics, thereby reducing the overall volume. However, above 10 MHz, magnetic cores become impractical due to material limitations. To address these issues, this article proposes a design methodology for a GaN-based quasi-square-wave (QSW) buck converter integrated with a PCB air-core inductor. First, the impact of the switching frequency and dead time on the zero-voltage switching (ZVS) condition is elaborated. Then, a power loss model accounting for various loss mechanisms is presented. To overcome high GaN body diode reverse conduction loss, an auxiliary diode is employed. Based on the model, a design procedure is developed to optimize the inductor for 10 MHz operation while maximizing efficiency. To validate the design, a 28 V/12 V, 18 W prototype was built and tested. Experimental results demonstrate a peak efficiency of 86.5% at 10 MHz. The auxiliary diode improves efficiency by 4%, verifying reverse conduction loss mitigation. Thermal analysis confirms a full-load case temperature of 62.2 °C, providing a 47.8 °C safety margin compliant with aerospace derating standards. These findings validate the solution for high-frequency, space-constrained aerospace applications.

1. Introduction

Modern aerospace platforms of satellites require high-performance power distribution networks (PDNs) [1]. As shown in Figure 1, the 28 V DC bus serves as the standard low-voltage DC (LVDC) supply, which powers the payload through a DC-DC buck converter. However, these power systems face stringent size, weight, and power (SWaP) constraints, especially in microsatellites like CubeSats. As standardized nanosatellites ($10\times 10\times 10{\mathrm{cm}}^3$), their limited vertical spacing between stacked PCBs (<10 mm) precludes bulky magnetic inductors. Additionally, the weight is strictly capped at 1.33 kg/unit [2] to mitigate high launch costs (>$10,000/kg), and the limited power generation (<2 W) [3] demands high efficiency to minimize thermal dissipation in the vacuum environment [4]. Therefore, it is essential to increase the switching frequency to the MHz range to miniaturize passive components while maintaining high efficiency [5,6].

To enable high-frequency operation in such harsh environments, gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are the preferred technology [7,8]. Compared with silicon (Si), GaN devices offer faster switching speeds and intrinsic radiation hardness. This radiation resilience is critical for aerospace applications, which face continuous exposure to high-energy particles. The absence of a gate oxide layer provides immunity to the total ionizing dose (TID). Additionally, the minimized sensitive volume mitigates single event effects (SEEs) [9]. Finally, the high bond energy of GaN ensures resistance to displacement damage. However, applying GaN HEMTs has a critical limitation: the lack of an intrinsic body diode. This characteristic results in a high reverse voltage drop, causing significant reverse conduction losses during the dead-time period [10,11].

The buck converter is a fundamental topology to step down the 28 V DC bus to 12 V for aerospace electronic payloads. While traditional converters typically operate with hard-switching, this method causes significant switching losses at high frequencies. To address this, the quasi-square-wave (QSW) topology is adopted. By employing synchronous rectification (SR), the QSW converter allows the inductor current to reverse direction. This negative current helps discharge the parasitic output capacitance ($C_{oss}$) of the switches, enabling zero-voltage switching (ZVS) [12,13,14]. Besides improving efficiency, ZVS effectively mitigates electromagnetic interference (EMI). It eliminates the rapid discharge of $C_{oss}$, thereby suppressing current spikes and high-frequency voltage ringing. Driven by these advantages, the GaN-based QSW buck converter has been extensively investigated for high-density power conversion. For instance, Ref. [15] demonstrated a high-efficiency solution for cellphone fast-charging applications. Similarly, Refs. [16,17] developed compact prototypes for portable devices, showing that GaN-based designs outperformed their Si-based counterparts in both efficiency and size.

However, these existing works primarily adopted inductors with magnetic cores. The QSW topology inherently generates a high inductor current ripple. To prevent magnetic saturation caused by this ripple, a core with a high saturation current rating is required. This typically results in a bulky and heavy component, which counteracts the weight-saving benefits of high-frequency operation. Since the inductance required for QSW operation is relatively small, the PCB air-core inductor becomes a viable and attractive option. Unlike magnetic inductors, air-core designs eliminate saturation issues completely and are immune to core losses. Previous studies [18,19,20,21] have confirmed that utilizing air-core inductors in GaN QSW converters can achieve higher efficiencies compared with ferrite inductors.

While implementing air-core inductors on PCBs is attractive, it presents a significant trade-off between physical footprint and efficiency. For instance, planar spirals offer high inductance but consume excessive board space [22]. Conversely, compact single-turn structures minimize size but suffer from severe AC resistance due to current crowding [23]. To overcome this limitation, this paper proposes a vertically stacked four-layer PCB inductor, offering a superior solution for SWaP-constrained aerospace applications.

To address these challenges, this paper presents a loss-driven design methodology for a 10 MHz GaN-based QSW buck converter designed for SWaP-constrained aerospace platforms. First, this work uses an air-core inductor to avoid magnetic saturation and reduce system weight. This approach removes the frequency limits of magnetic materials and meets the strict weight constraints of satellite payloads. Second, an auxiliary Schottky diode is connected in parallel with the synchronous switch (SyncFET) to reduce high reverse conduction losses. As such, the converter remains within aerospace thermal derating limits, even in vacuum environments where cooling is difficult. Finally, a systematic design procedure is developed to balance efficiency and power density. This procedure ensures ZVS and satisfies the rigorous noise standards for aerospace electronics.

The rest of this paper is organized as follows. Section 2 analyzes the circuit operation and ZVS conditions. Section 3 presents the comprehensive loss modeling. Section 4 details the proposed design procedure. Section 5 presents the experimental validation, followed by the conclusion in Section 6.

2. Theoretical Analysis of ZVS Operation and EMI Mechanisms

2.1. ZVS Transition Analysis

The circuit diagram and steady-state waveforms of the QSW buck converter are shown in Figure 2. $Q_1$ represents the control FET (CtrlFET), while $Q_2$ is the synchronous FET (SyncFET). To mitigate the high reverse voltage drop typical of GaN FET body diodes, an auxiliary Schottky diode $D_{au}$ is placed anti-parallel to $Q_2$ to minimize reverse conduction loss during the freewheeling dead time.

The switching transition dynamics reveal a distinct asymmetry between the two switches. The synchronous FET ($Q_2$) achieves ZVS inherently during the first dead time ($t_1$∼$t_2$), as the positive inductor current naturally discharges its output capacitance.

In contrast, achieving ZVS for the control FET ($Q_1$) is the primary design challenge. As illustrated in the equivalent circuit of the second dead time (Figure 3, $t_3$∼$t_4$), both switches are OFF. To discharge the parasitic output capacitance of $Q_1$ ($C_{oss1}$) before it turns on, the inductor current must flow in the reverse direction (negative polarity). Consequently, the converter design must ensure that the inductor current ripple is large enough to generate sufficient negative current ($I_{neg}$) to fully extract the charge from $C_{oss1}$ within the dead-time limit.

Applying Kirchhoff’s current law (KCL), the following equation can be derived:

$$I_N=-C_{oss1}{\displaystyle \frac{d{v}_{DS1}}{dt}}+(C_{oss2}+C_j){\displaystyle \frac{d{v}_{DS2}}{dt}}.$$

(1)

where $I_N$ is the negative peak current of the inductor current. As the dead time is short enough, $I_N$ is assumed to be a constant value to simplify the analysis. Considering that $d{v}_{DS1}/dt=-d{v}_{DS2}/dt$ and $C_{oss1}=C_{oss2}=C_{oss}$, the minimum dead time can be derived as

$$t_{d,min}={\displaystyle \frac{(2C_{oss}+C_j)(V_{in}+V_{bd})}{I_N}}$$

(2)

where $V_{bd}$ is the knee voltage of the body diode of GaN FET, since it becomes considerable for the low-voltage VRs application. The negative peak current $I_N$ and positive peak current $I_P$ can be derived from the ripple current $I_r$, as given by

$$I_N={\displaystyle \frac{I_r}{2}}-I_{out}$$

(3)

$$I_P={\displaystyle \frac{I_r}{2}}+I_{out}$$

(4)

$$I_{out}={\displaystyle \frac{V_{out}}{R_L}}$$

(5)

$$I_r=I_P-I_N={\displaystyle \frac{(V_{in}-V_{out})t_{on}}{L}}$$

(6)

$$V_{out}=t_{on}f{V}_{in}$$

(7)

where $t_{on}$ is the on-time of $Q_1$. As the dead time becomes considerable in one switching cycle for the high-frequency application, $t_{on}$ is given by

$$t_{on}=D/f-t_d$$

(8)

where D is the duty cycle. Based on the discussion above, there is one pre-condition, $I_N>0$, that must be satisfied or else the operation mode will be changed to CCM. Combine (3)∼(8), the following equation can be derived:

$$f<{\displaystyle \frac{1-D}{2L/R_L-t_d}}.$$

(9)

Thus, for a given inductance, there is a maximum frequency to ensure the DCM operation.

The maximum dead time should meet the condition that $Q_1$ needs to turn on before the negative inductor current returns to zero, as given by

$$t_{d,max}={\displaystyle \frac{L{I}_N}{V_{in}-V_{out}}}.$$

(10)

To summarize, the dead time should be as small as possible to minimize the reverse conduction loss as presented in the previous section. In addition, the minimum dead time should also consider the margin to avoid the arm shoot-through, which is limited by the converter hardware design. By comparing (2) and (10), it can be found that a large $I_N$ allows a wide margin for the selection of dead time. For the extreme condition when $I_N$ is too small, $t_{d,max}$ may become smaller than $t_{d,min}$, which leads to the partial ZVS. Assuming $t_{d,max}>t_{d,min}$, the minimum value of $I_N$ can be derived, as given by

$$I_N>\sqrt{{\displaystyle \frac{(2C_{oss}+C_j)(V_{in}+V_{bd})(V_{in}-V_{out})}{L}}}.$$

(11)

Since the increase in f will lead to a smaller $I_N$, there will be a maximum value for f to meet the ZVS condition. Assuming the right hand side of (11) to be $I_{N,min}$, the following relationship can be derived after combining (3), (6), and (8):

$$f<{\displaystyle \frac{D}{{\displaystyle \frac{2(I_{N,min}+I_{out})L}{V_{in}-V_{out}}}+t_d}}.$$

(12)

Finally, the maximum value of f can be given by

$$f_{max}={\left|{\displaystyle \frac{1-D}{{\displaystyle \frac{2L}{R_L}}-t_d}},{\displaystyle \frac{D}{{\displaystyle \frac{2(I_{N,min}+I_{out})L}{V_{in}-V_{out}}}+t_d}}\right|}_{\min }.$$

(13)

2.2. EMI Analysis and Mitigation Strategies

Operating at 10 MHz introduces specific electromagnetic interference (EMI) challenges for sensitive aerospace payloads. As depicted in Figure 4, the EMI sources primarily stem from two mechanisms: (1) the high switching-node voltage slew rate ($dv/dt$), and (2) the pulsed current loops ($di/dt$) during switching transitions.

To address these issues under strict SWaP constraints where bulky shielding is limited, a multi-layered mitigation strategy is implemented. First, unlike hard-switching topologies, the proposed QSW operation achieves ZVS, which naturally eliminates the abrupt capacitive discharge of $C_{oss}$ and significantly reduces the $dv/dt$ slope and high-frequency ringing at the source. Simultaneously, the physical area of the high-$di/dt$ loop (labeled as the “hot loop” in Figure 4) is minimized through an optimized vertical layout; this reduction in parasitic inductance is critical for limiting voltage overshoots and radiated emissions. Furthermore, a solid ground plane is employed to shield the electric field, while the utilized air-core inductor ensures linear magnetic characteristics free from magnetostriction and Barkhausen noise, thereby preventing the injection of nonlinear magnetic interference into adjacent precision sensors.

3. Evaluation of Power Loss

3.1. Device Power Loss Calculation

Due to the unsymmetrical operation modes between the CtrlFET and SyncFET, the power losses for each device needs to be discussed separately. The EPC GaN FET EPC2014C (40 V, 10 A) is used as both the CtrlFET and SyncFET. The gate driver IC uses the TI half-bridge GaN driver LMG1205, with a 1.2 A source current and 5 A sink current. The Rohm Schottky diode RB160VYM-40FH (40 V, 1 A) is used as the auxiliary diode.

3.1.1. CtrlFET

The power loss of CtrlFET $Q_1$ consists of the switching loss $P_{sw,1}$ and the conduction loss $P_{cond,1}$.

Since the ZVS at the turn-on transient is achieved for $Q_1$, $P_{sw,1}$ only needs to consider the turn-off loss, as given by

$$P_{sw,1}=E_{off1}\left(I_P\right)f$$

(14)

where $E_{off1}$ is the turn-off energy of $Q_1$ at the current of $I_P$, and it can be obtained from the double pulse test (DPT) simulation, with the circuit diagram shown in Figure 5, where $R_{G1}$ and $R_{G2}$ are the gate resistances for $Q_1$ and $Q_2$, respectively, $L_{loop}$ is the stray inductance of the power loop.

$$E_{off}=38.4-1.78I+1.08I^2\left(\mathrm{nJ}\right).$$

(15)

The gate resistance consists of the internal resistances of the gate-driver-integrated circuit (IC) and GaN FET and the external gate resistance. In this study, $R_{G1}$ = $R_{G2}$ = 3 $\mathrm{\Omega }$. $L_s$ consists of the packaging inductances of GaN FET, the decoupling capacitor, and the stray inductance of PCB. With advanced packaging technology such as the land grid array (LGA), the packaging inductance can be as low as 0.1 nH. The packaging inductance contributed by the decoupling capacitor can be minimized by using several surface mounted device (SMD) ceramic capacitors in parallel. Thus, the PCB stray inductance $L_s$ dominates $L_{loop}$. Using the Ansys Q3D Extractor, $L_s$ is extracted to be 1.7 nH, and thus, $L_{loop}$ is estimated around 2 nH. Details on the PCB design will be presented in the following section. Finally, $E_{off1}$ can be obtained by the SPICE simulation with $V_{in}$ = 12 V and $I_L$ = 1∼5 A, as shown in Figure 6. The relationship between $E_{off}$ and I can be approximated by a second-order curve fitting, as given by

$P_{cond,1}$ needs to consider the power dissipation on the on-resistance $R_{ds,on}$ of $Q_1$ when it is on and the additional reverse conduction loss during the dead time $t_d$. To simplify the analysis, it is assumed that $I_N$ flows through $D_{b1}$ during the entire dead time. Thus, $P_{cond,1}$ is given by

$$P_{cond,1}=(I_{out}^2+{\displaystyle \frac{1}{12}}{I}_r^2)R_{ds,on}{t}_{on}f+I_N(I_N{R}_{bd}+V_{bd})t_{d}f$$

(16)

where $R_{bd}$ is the on-resistance of GaN FET.

3.1.2. SyncFET

The power loss of SyncFET $Q_2$ only consists of conduction loss $P_{cond,2}$, since $D_{au}$ commutates with $Q_1$ during the switching transient. In addition, $D_{b2}$ will not shunt any current due to the existence of $D_{au}$. Thus, $P_{cond,2}$ needs to consider the power dissipation on the on-resistance of $Q_2$, as given by

$$P_{cond,2}=(I_{out}^2+{\displaystyle \frac{1}{12}}{I}_r^2)R_{ds,on}{t}_{off}f.$$

(17)

3.1.3. Auxiliary Diode

Due to the absence of reverse recovery charge in the Schottky diode, its turn-off loss is normally neglected. Thus, the power loss of external diode $D_{au}$ only needs to consider the power dissipation during the dead time $t_d$, as given by

$$P_{cond,D}=I_P(I_P{R}_d+V_d)t_{d}f$$

(18)

where $R_d$ and $V_d$ are the on-resistance and knee voltage of the external Schottky diode, respectively.

3.1.4. Gate Driver

The gate driver loss $P_{qg}$ is due to the charging and discharging of the gate charge. For the converter operating in a high-frequency condition, $P_{qg}$ can no longer be neglected, as given by

$$P_{qg}=V_g{Q}_{g}f$$

(19)

where $V_g$ is the peak-to-peak output voltage of gate driver and $Q_g$ is the gate charge of GaN FET.

All of the device parameters for GaN FET EPC2014C and Schottky diode RB160VYM-40FH are summarized in

Table 1. Device parameters for GaN FET EPC2014C and Schottky diode RB160VYM-40FH.

Parameter	Value
$R_{ds,on}$	12 mΩ
$R_{bd}$	30 mΩ
$V_{bd}$	2.2 V
$Q_g$	2 nC
$C_{oss}$	150 pF
$V_g$	5 V
$R_d$	135 mΩ
$V_d$	0.28 V
$C_j$	20 pF

. It should be noted that the room temperature is specified.

3.2. Inductor Loss Calculation

Due to the absence of a magnetic core, the inductor loss only needs to consider the winding loss, which is contributed by both of the DC resistance ($R_{dc}$) and AC resistance ($R_{ac}$). For the inductor operated at a relatively low frequency of around 100 kHz, the winding loss is mainly due to $R_{dc}$, since the current density shows little change in the cross-section of the conductor. With the increase in frequency, the winding loss will increase dramatically due to the eddy current effect, which consists of the skin effect and proximity effect. Both of them give rise to the non-uniform current distribution across the conductor.

In this work, a spiral air-core inductor is designed using a four-layer PCB, as Figure 7 shows. The thickness of each copper layer is 1 oz or 35 μm, while the thicknesses of the dielectric layers are 0.2 mm, 1.2 mm, and 0.2 mm from the top to bottom sides. $R_{dc}$ is extracted to be 50 mΩ using the Ansys Q3D Extractor. $R_{ac}$ is extracted using the Eddy Current Solver of Ansys Maxwell. Figure 8 shows $R_{ac}$ in the frequency of 5∼15 MHz. Similar to the previous discussion, a second-order curve fitting is applied, and thus, $R_{ac}$ is given by

$$R_{ac}=193+5f-0.175f^2\left(m\mathrm{\Omega }\right)$$

(20)

where the unit of f is MHz. It can be concluded that $R_{ac}$ is much higher than $R_{dc}$. Figure 9a,b further show the simulation of the cross section of current density at DC (10${}^{-8}$ Hz) and the 10 MHz frequency, respectively. It can be found that for the DC condition, the current is uniformly distributed across the conductor, while at 10 MHz, the current is concentrated at the edge. The peak current density at 10 MHz is 10 times than that of the DC condition. Thus, for the converter operated at 10 MHz in this work, $R_{ac}$ leads to a remarkable inductor power dissipation, as given by

$$P_{ind}=(I_{out}^2+{\displaystyle \frac{1}{12}}{I}_r^2)R_{ac}.$$

(21)

Table 2. Calculated loss breakdown at full-load condition ($V_{in}=28$ V, $V_{out}=12$ V, $P_{out}=16$ W, $f_s=10$ MHz).

Component	Loss Mechanism	Symbol	Power Loss (W)
Air-core Inductor	Winding Loss	$P_{ind}$	0.924
GaN Top FET ($Q_1$)	Switching Loss	$P_{sw,1}$	0.484
	Conduction Loss	$P_{cond,1}$	0.313
GaN SyncFET ($Q_2$)	Reverse Conduction	$P_{cond,D}$	0.324
	Gate Charge Loss	$P_{qg}$	0.100
	Conduction Loss	$P_{cond,2}$	0.028
Total	Sum	$P_{total}$	2.173

summarizes the calculated loss breakdown at full load ($P_{out}=16$ W). The air-core inductor loss ($P_{ind}$) dominates, accounting for approximately 42.5% of the total power dissipation. This is the accepted trade off for eliminating magnetic saturation and minimizing weight. Regarding semiconductor losses, the reverse conduction loss ($P_{cond,D}=0.324$ W) is significant, notably exceeding the conduction loss of the main switch ($P_{cond,1}$). This confirms the importance of the proposed thermal management strategy to address the dead-time-related heat generation.

4. Converter Design Procedure

Since the converter designed in this work does not use the standard SMD inductor, an iterative design procedure is proposed with the consideration of inductor design.

4.1. Design Specifications and Methodology

The detailed design specifications are listed in

Table 3. Design specifications of the proposed GaN QSW buck converter.

Parameter	Symbol	Value
Input Voltage	$V_{in}$	28 V
Output Voltage	$V_{out}$	12 V
Load Resistance	$R_L$	8 $\mathrm{\Omega }$
Switching Frequency	$f_s$	10 MHz
Dead Time	$t_d$	10 ns
Current Ripple Ratio	r	<10

, where the key parameters are selected to comply with aerospace standards. Specifically, the input voltage $V_{in}$ is set to 28 V, aligning with the standard DC bus voltage defined in MIL-STD-704F for satellite and aircraft power systems. The switching frequency $f_s$ is pushed to 10 MHz to minimize the size and weight of passive components, thereby satisfying the strict SWaP constraints. The output voltage $V_{out}$ is regulated at 12 V to serve as an intermediate bus for downstream payloads. The device selection is firstly conducted according to these specifications.

A flow chart for the design procedure is shown in Figure 10. The initial operating conditions for the converter are assumed with $f\approx$ 10 MHz and $t_d\approx$ 10 ns. Thus, the inductance is estimated to be 300 nH from (9). To ensure enough margin, the inductance needs to be smaller than this value to ensure the DCM operation. Then, the ripple ratio ($r=I_r/I_{out}$) is verified to ensure it is sufficiently large to achieve ZVS. Meanwhile, f is compared with $f_{max}$, as illustrated by (13). If the relationship is satisfied, $t_d$ needs to be slightly adjusted to meet the relationship of $t_{d,min}<t_d<t_{d,max}$; otherwise, the inductor must be re-designed. The design process concludes with the step of loss optimization.

4.2. Parameter Optimization

From the discussion of Section 3, it can be concluded that a higher f leads to a smaller current ripple; thus, the conduction loss ($P_{cond,1}$, $P_{cond,2}$, $P_{cond,D}$) and $P_{ind}$ decrease. However, $P_{sw,1}$ increases with the increase in f. As a consequence, there is an optimal f to achieve the highest efficiency.

Figure 11 shows the efficiency $\eta$ at different values of f when L = 50 nH, 100 nH, 150 nH, 200 nH, and 250 nH. It should be noted that the ranges of frequency are different. This is because the minimum frequency is limited by the current ripple, while the maximum frequency is limited by the ZVS condition. From Figure 11, it can be found that it is impossible to achieve the design target of 10 MHz frequency when $L>$ 150 nH, even though a higher efficiency can be achieved with a larger L. If L is too small (50 nH), the efficiency is too low. For all the situations, $\eta$ shows an increasing tendency with the increase in f before the converter finally enters the partial-ZVS operation. Thus, f should be close to $f_{max}$ to achieve the highest $\eta$. In addition, it is suggested that L should be within 100∼150 nH for a 10 MHz frequency operation.

4.3. Prototype Implementation and Verification

Figure 12 shows the prototype of the QSW buck converter, which is designed by a 4-layer PCB with the size of 16 mm × 10 mm. Due to the extremely high switching frequency, both of the input and output capacitors ($C_{in}$ and $C_{out}$) can just use the multi-layer ceramic capacitors (MLCCs). To reduce $L_{loop}$, the vertical power loop is adopted for the PCB design to enhance the magnetic canceling effect, which is also a recommended layout design for GaN FET [24].

The load inductance can be extracted using the Eddy Current Solver of Ansys Maxwell, as Figure 13 shows. It can be found that L does not show a significant variation in the frequency range of 5∼15 MHz. Thus, it is assumed to be a constant value of 130 nH. According to (13), $f_{max}$ is estimated to be 11 MHz. In addition, $t_{d,min}$ and $t_{d,max}$ are calculated to be 7.4 ns and 10.5 ns, respectively. Thus, it is reasonable to set f = 10 MHz and $t_d$ = 10 ns.

Finally, Figure 14 shows the calculated total power loss $P_{loss}$ and $\eta$ in the frequency range of 4∼10 MHz when L = 130 nH. It can be found that a maximum efficiency of 88% can be achieved at f = 10 MHz, which is close to the upper limit of the ZVS condition. Although $\eta$ still shows an increasing tendency, the converter may work at the partial-ZVS condition when f is above 11 MHz, thus leading to a reduced $\eta$.

Figure 15 shows the calculated loss breakdown. It can be found that $P_{ind}$ almost dominates $P_{loss}$. Only when f reaches as high as 10 MHz, $P_{sw,1}$ becomes close to $P_{ind}$. In addition, $P_{cond,1}$ is much larger than $P_{cond,2}$ due to the effect of the body diode, which means the auxiliary diode is very effective in reducing the reverse conduction loss. The power loss without the auxiliary diode is investigated to further prove its effectiveness, which means $P_{cond,2}$ should be re-calculated as

$$P_{cond,2}=(I_{out}^2+{\displaystyle \frac{1}{12}}{I}_r^2)R_{ds,on}{t}_{off}f+I_P(I_P{R}_{bd}+V_{bd})t_{d}f.$$

(22)

For f = 10 MHz, $P_{cond,2}$ is calculated to be 0.95 W, which is much larger than the situation with the auxiliary diode ($P_{cond,2}$ = 0.03 W, $P_{cond,D}$ = 0.32 W).

Figure 14. Calculated results of $P_{loss}$ and $\eta$ for f = 4∼10 MHz when L = 130 nH.

Figure 14. Calculated results of $P_{loss}$ and $\eta$ for f = 4∼10 MHz when L = 130 nH.

Figure 15. Calculated loss breakdown for f = 4∼10 MHz when L = 130 nH.

Figure 15. Calculated loss breakdown for f = 4∼10 MHz when L = 130 nH.

5. Result and Discussion

5.1. Experimental Setup

The efficiency of the QSW buck converter is tested by the experiment, as shown in Figure 16. The core part of the converter is designed with a high density and placed in the center of a 50 mm × 50 mm PCB. The test points are placed outside the core part for easy measurement. The input capacitors use four parallel 50 V, 4.7 μF MLCCs in the 0805 package, while the output capacitors uses three parallel 25 V, 4.7 μF MLCCs in the 0603 package. The external gate resistances for both $Q_1$ and $Q_2$ are 2 $\mathrm{\Omega }$. The open-loop synchronous pulse width modulation (PWM) signals for both $Q_1$ and $Q_2$ are generated by the micro-controller. A multi-channel power supply is used to provide the input powers of $V_{in}$ = 28 V and $V_g$ = 5 V to the test board. An electronic load is used as the load resistance. The input voltage/current ($V_{in}$, $I_{in}$) and output voltage/current ($V_{out}$, $I_{out}$) are connected to the power analyzer to measure the converter efficiency. In addition, the waveforms of the gate-source voltage and drain-source voltage of $Q_2$ ($v_{gs2}$, $v_{ds2}$) and output voltage $V_{out}$ are measured by the oscilloscope.

Figure 17a–c show the waveforms of $v_{gs2}$, $v_{ds2}$, and $V_{out}$ when f = 8 MHz, 10 MHz, and 12 MHz, respectively. It can be found that the ZVS can be easily achieved for the situations of f = 8 MHz and 10 MHz, which can be observed from the remarkable positive voltage spike of $v_{ds2}$. In addition, the voltage slew rate of $v_{ds2}$ decreases with the increase in f. It is because of smaller ripple currents at higher frequencies; thus, it takes a longer time to finish the charging of $C_{oss2}$ and $C_j$. For f = 12 MHz, only the partial ZVS can be achieved, which leads to a reduction in $\eta$.

5.2. Effect of Dead Time

Figure 18a,b show the waveforms of $v_{gs2}$, $v_{ds2}$, and $V_{out}$ when $T_d$ = 5 ns and 15 ns, respectively. The efficiencies for these two conditions are 85.2% and 85.1%, respectively, both of which are lower than 85.9% at 10 ns. This is also because only the partial ZVS is achieved as predicted by the theoretical calculation in (2) and (10), with $t_{d,min}$ = 7.4 ns and $t_{d,max}$ = 10.5 ns. For $T_d$ = 5 ns, $T_d$ is too short to finish the charging of $C_{oss2}$ and $C_j$. For $T_d$ = 15 ns, $T_d$ is too long such that the direction of inductor current becomes reverse, which leads to the discharging of $C_{oss2}$ and $C_j$. Thus, $v_{ds2}$ begins to decrease. The experimental results match well with the theoretical calculation.

5.3. Effect of Auxiliary Diode

The effect of auxiliary diode on $\eta$ is further evaluated by removing it. Figure 19 shows the measured results of $\eta$ with and without the auxiliary diode. The test conditions are the same as f = 6∼14 MHz and $T_d$ = 10 ns. It can be found that the maximum value of $\eta$ is reduced from 85.9% to 81.9% when the diode is removed, which proves its effectiveness in efficiency improvement. Figure 20 further shows the measured waveforms when f = 10 MHz and $T_d$ = 10 ns without the auxiliary diode. It can be found that although the ZVS can be achieved at the turn-on transition of $Q_1$, the freewheeling current flows through the body diode of $Q_2$ when $Q_1$ is off, thus leading to a significant negative voltage spike and a higher reverse conduction loss.

5.4. Thermal Performance and Derating Verification

Thermal management is a critical reliability constraint for aerospace payloads, particularly in vacuum environments where convective cooling is absent. In compliance with the ECSS-Q-ST-30-11C space product assurance standard, power semiconductors must operate within strict derating limits. For GaN HEMTs in space missions, a maximum junction temperature ($T_j$) of 110 °C is typically enforced to ensure long-term reliability.

To verify the thermal viability of the proposed design, a steady-state thermal analysis was conducted. Since active air cooling is unavailable in space, the converter relies exclusively on conductive heat transfer through the PCB and radiative dissipation. Due to the low thermal mass of the compact GaN-on-PCB assembly, the converter was operated continuously until the thermal readings stabilized, indicating that equilibrium had been reached.

Figure 21a presents the thermal profile at the full-load condition (16 W). The maximum temperature was observed on the SyncFET at 62.2 °C. Comparing this experimental result with the aerospace derating limit, the thermal safety margin is calculated as

$$T_{margin}=T_{limit}-T_{measured}={110}^{\circ }\mathrm{C}-{62.2}^{\circ }\mathrm{C}={47.8}^{\circ }\mathrm{C}$$

(23)

This substantial margin of 47.8 °C validates that the vertical PCB layout effectively dissipates the heat generated by reverse conduction, making the converter suitable for vacuum operation.

Figure 21. Steady-state thermal images: (a) at full-load condition ($P_o=18$ W); (b) at the peak efficiency operating point ($\eta =86.5\%$).

Figure 21. Steady-state thermal images: (a) at full-load condition ($P_o=18$ W); (b) at the peak efficiency operating point ($\eta =86.5\%$).

For further evaluation, Figure 21b shows the thermal image at the peak efficiency operating point. Due to the minimized switching losses achieved by the ZVS design, the maximum temperature on the SyncFET drops to 53 °C. This low thermal stress further confirms the effectiveness of the proposed soft-switching methodology.

Finally, the experimental results are compared with the design requirements in

Table 4. Comparison between design requirements and experimental results.

Parameter	Symbol	Requirement/Standard	Measured Result	Conclusion
Input Voltage	$V_{in}$	28 V (Sat. Bus)	28 V	Compliant
Output Voltage	$V_{out}$	12 V (Load Req.)	12.0 V	Regulated
Case Temperature	$T_{case}$	< 110 °C (Derating)	62.2 °C	Safe Margin
Peak Efficiency	${\eta }_{peak}$	Maximized	86.5%	Optimized
Soft Switching	ZVS	Full ZVS Range	Achieved	Verified

. The data confirms that the prototype complies with the electrical specifications. Notably, the converter achieves a peak efficiency of 86.5% and maintains a sufficient thermal margin, satisfying the strict aerospace derating standards.

6. Conclusions and Future Work

In this work, a comprehensive design methodology for a 10 MHz GaN-based QSW buck converter with an integrated air-core PCB inductor was proposed and validated. This design addresses the limitations of magnetic core materials at high frequencies, making it suitable for aerospace applications requiring radiation hardness and high power density. Specifically, a two-turn, four-layer circular PCB air-core inductor was optimized to balance the trade off between physical footprint and AC resistance. Furthermore, an auxiliary diode was employed to effectively reduce the high reverse conduction loss of the GaN device.

In conclusion, a 10 MHz GaN-based QSW buck converter was designed and tested. The experimental results show that the converter achieves a peak efficiency of 86.5%. Specifically, the use of an auxiliary diode increases the measured peak efficiency by 4% (from 81.9% to 85.9%) at 10 MHz. Furthermore, the thermal analysis confirms a maximum case temperature of 62.2 °C. This results in a safety margin of 47.8 °C relative to the aerospace derating limit of 110 °C. These quantitative findings prove that the proposed design is effective for high-frequency aerospace power applications.

It should be noted that implementing closed-loop control at 10 MHz presents significant challenges due to the ultra-short switching period (100 ns). Standard digital controllers face limitations in ADC sampling speed and calculation delay within this tight time budget. Therefore, future work will focus on an FPGA-based closed-loop control to ensure dynamic response. Additionally, using coupled inductors will be investigated to reduce current ripples while maintaining high efficiency.